defacd6ae1
USB3 and PCIE0 of k1x shares a combo phy. BIT(8) of APMU register APMU_PCIE_CLK_RES_CTRL_0 is designed for USB3 to reset the combo phy without resetting the PCIE0. Change-Id: I1935d228b1c4c8d81fd280a8dc245806539d7104 Signed-off-by: Junzhong Pan <junzhong.pan@spacemit.com>
139 lines
3.5 KiB
C
139 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#ifndef __DT_BINDINGS_RESET_SAPCEMIT_K1X_H__
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#define __DT_BINDINGS_RESET_SAPCEMIT_K1X_H__
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//APBC
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#define RESET_UART1 1
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#define RESET_UART2 2
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#define RESET_GPIO 3
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#define RESET_PWM0 4
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#define RESET_PWM1 5
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#define RESET_PWM2 6
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#define RESET_PWM3 7
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#define RESET_PWM4 8
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#define RESET_PWM5 9
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#define RESET_PWM6 10
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#define RESET_PWM7 11
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#define RESET_PWM8 12
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#define RESET_PWM9 13
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#define RESET_PWM10 14
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#define RESET_PWM11 15
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#define RESET_PWM12 16
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#define RESET_PWM13 17
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#define RESET_PWM14 18
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#define RESET_PWM15 19
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#define RESET_PWM16 20
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#define RESET_PWM17 21
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#define RESET_PWM18 22
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#define RESET_PWM19 23
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#define RESET_SSP3 24
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#define RESET_UART3 25
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#define RESET_RTC 26
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#define RESET_TWSI0 27
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#define RESET_TIMERS1 28
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#define RESET_AIB 29
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#define RESET_TIMERS2 30
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#define RESET_ONEWIRE 31
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#define RESET_SSPA0 32
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#define RESET_SSPA1 33
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#define RESET_DRO 34
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#define RESET_IR 35
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#define RESET_TWSI1 36
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#define RESET_TSEN 37
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#define RESET_TWSI2 38
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#define RESET_TWSI4 39
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#define RESET_TWSI5 40
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#define RESET_TWSI6 41
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#define RESET_TWSI7 42
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#define RESET_TWSI8 43
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#define RESET_IPC_AP2AUD 44
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#define RESET_UART4 45
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#define RESET_UART5 46
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#define RESET_UART6 47
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#define RESET_UART7 48
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#define RESET_UART8 49
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#define RESET_UART9 50
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#define RESET_CAN0 51
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//MPMU
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#define RESET_WDT 52
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//APMU
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#define RESET_JPG 53
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#define RESET_CSI 54
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#define RESET_CCIC2_PHY 55
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#define RESET_CCIC3_PHY 56
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#define RESET_ISP 57
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#define RESET_ISP_AHB 58
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#define RESET_ISP_CI 59
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#define RESET_ISP_CPP 60
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#define RESET_LCD 61
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#define RESET_DSI_ESC 62
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#define RESET_V2D 63
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#define RESET_MIPI 64
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#define RESET_LCD_SPI 65
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#define RESET_LCD_SPI_BUS 66
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#define RESET_LCD_SPI_HBUS 67
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#define RESET_LCD_MCLK 68
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#define RESET_CCIC_4X 69
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#define RESET_CCIC1_PHY 70
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#define RESET_SDH_AXI 71
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#define RESET_SDH0 72
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#define RESET_SDH1 73
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#define RESET_USB_AXI 74
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#define RESET_USBP1_AXI 75
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#define RESET_COMBO_PHY 76
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#define RESET_USB3_0 77
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#define RESET_QSPI 78
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#define RESET_QSPI_BUS 79
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#define RESET_DMA 80
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#define RESET_AES 81
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#define RESET_VPU 82
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#define RESET_GPU 83
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#define RESET_SDH2 84
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#define RESET_MC 85
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#define RESET_EM_AXI 86
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#define RESET_EM 87
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#define RESET_AUDIO_SYS 88
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#define RESET_HDMI 89
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#define RESET_PCIE0 90
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#define RESET_PCIE1 91
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#define RESET_PCIE2 92
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#define RESET_EMAC0 93
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#define RESET_EMAC1 94
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//APBC2
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#define RESET_SEC_UART1 95
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#define RESET_SEC_SSP2 96
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#define RESET_SEC_TWSI3 97
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#define RESET_SEC_RTC 98
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#define RESET_SEC_TIMERS0 99
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#define RESET_SEC_KPC 100
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#define RESET_SEC_GPIO 101
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#define RESET_RCPU_HDMIAUDIO 102
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#define RESET_RCPU_CAN 103
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#define RESET_RCPU_I2C0 104
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#define RESET_RCPU_SSP0 105
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#define RESET_RCPU_IR 106
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#define RESET_RCPU_UART0 107
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#define RESET_RCPU_UART1 108
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#define RESET_RCPU2_PWM0 109
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#define RESET_RCPU2_PWM1 110
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#define RESET_RCPU2_PWM2 111
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#define RESET_RCPU2_PWM3 112
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#define RESET_RCPU2_PWM4 113
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#define RESET_RCPU2_PWM5 114
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#define RESET_RCPU2_PWM6 115
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#define RESET_RCPU2_PWM7 116
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#define RESET_RCPU2_PWM8 117
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#define RESET_RCPU2_PWM9 118
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#define RESET_NUMBER 119
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#endif /* __DT_BINDINGS_RESET_SAPCEMIT_K1X_H__ */
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