OERV-BSP/kernel-spacemit-k1
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Merge remote-tracking branch 'internal/k1-bl-v2.2.y' into k1-bl-v2.2.y

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This commit is contained in:
James Deng
2025-06-26 17:57:39 +08:00
parent 50626b4a9d 9513d7530f
commit cecd843d17
77 changed files with 2409 additions and 3866 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
arch/riscv/boot/dts/spacemit/Makefile
View File

@@ -1,13 +1,12 @@
dtb-$(CONFIG_SOC_SPACEMIT_K1PRO) += k1-pro_sim.dtb k1-pro_fpga.dtb k1-pro_fpga_1x4.dtb \
k1-pro_fpga_2x2.dtb k1-pro_qemu.dtb k1-pro_verify.dtb
dtb-$(CONFIG_SOC_SPACEMIT_K1X) += k1-x_fpga.dtb k1-x_fpga_1x4.dtb k1-x_fpga_2x2.dtb k1-x_evb.dtb \
k1-x_deb2.dtb k1-x_deb1.dtb k1-x_hs450.dtb k1-x_kx312.dtb \
k1-x_MINI-PC.dtb k1-x_MUSE-N1.dtb k1-x_mingo.dtb \
k1-x_deb2.dtb k1-x_deb1.dtb k1-x_MINI-PC.dtb k1-x_MUSE-N1.dtb \
k1-x_MUSE-Pi.dtb k1-x_milkv-jupiter.dtb m1-x_milkv-jupiter.dtb \
k1-x_MUSE-Book.dtb k1-x_lpi3a.dtb k1-x_MUSE-Card.dtb \
k1-x_MUSE-Paper.dtb k1-x_MUSE-Paper-mini-4g.dtb \
k1-x_MUSE-Paper-mini-4g.dtb \
k1-x_baton-camera.dtb k1-x_FusionOne.dtb k1-x_InnoBoard-Pi.dtb \
k1-x_ZT001H.dtb k1-x_uav.dtb k1-x_MUSE-Paper2.dtb \
k1-x_bit-brick.dtb k1-x_LX-V10.dtb k1-x_NetBridge-C1.dtb \
k1-x_MUSE-Pi-Pro.dtb
k1-x_MUSE-Pi-Pro.dtb k1-x_som.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

18
arch/riscv/boot/dts/spacemit/k1-x.dtsi
View File

@@ -1029,8 +1029,11 @@
apb-clk-rate = <122880000>;
resets = <&reset RESET_AUDIO_SYS>;
reset-names = "core_reset";
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
firmware-name = "esos.elf";
power-domains = <&power K1X_PMU_AUD_PWR_DOMAIN>;
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};
@@ -1108,9 +1111,9 @@
spi2: spi@f0613000 {
compatible = "spacemit,k1x-spi";
reg = <0x0 0xf0613000 0x0 0x30>;
reg = <0x0 0xf0613000 0x0 0x34>;
k1x,ssp-id = <2>;
k1x,ssp-clock-rate = <26000000>;
k1x,ssp-clock-rate = <51200000>;
k1x,ssp-disable-dma;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
cpuidle,pm-runtime,sleep;
@@ -1127,10 +1130,9 @@
spi3: spi@d401c000 {
compatible = "spacemit,k1x-spi";
reg = <0x0 0xd401c000 0x0 0x30>;
reg = <0x0 0xd401c000 0x0 0x34>;
k1x,ssp-id = <3>;
k1x,ssp-clock-rate = <26000000>;
k1x,ssp-disable-dma;
k1x,ssp-clock-rate = <51200000>;
dmas = <&pdma0 DMA_SSP3_RX 1
&pdma0 DMA_SSP3_TX 1>;
dma-names = "rx", "tx";
@@ -1943,8 +1945,7 @@
clock-names = "emac-clk", "ptp-clk";
resets = <&reset RESET_EMAC0>;
reset-names = "emac-reset";
interrupts = <131>;
interrupt-parent = <&intc>;
interrupts-extended = <&intc 131>;
mac-address = [ 00 00 00 00 00 00 ];
ptp-support;
ptp-clk-rate = <10000000>;
@@ -1967,8 +1968,7 @@
clock-names = "emac-clk", "ptp-clk";
resets = <&reset RESET_EMAC1>;
reset-names = "emac-reset";
interrupts = <133>;
interrupt-parent = <&intc>;
interrupts-extended = <&intc 133>;
mac-address = [ 00 00 00 00 00 00 ];
ptp-support;
ptp-clk-rate = <10000000>;

4
arch/riscv/boot/dts/spacemit/k1-x_FusionOne.dts
View File

@@ -645,6 +645,7 @@
SDHCI_QUIRK2_BROKEN_PHY_MODULE
)>;
spacemit,rx_dline_reg = <0x0>;
spacemit,tx_delaycode = <0x9f 0x78>;
spacemit,rx_tuning_limit = <50>;
spacemit,sdh-freq = <375000000>;
status = "okay";
@@ -868,9 +869,6 @@
&rcpu {
/* pinctrl-names = "default"; */
/* pinctrl-0 = <&pinctrl_rcpu>; */
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

7
arch/riscv/boot/dts/spacemit/k1-x_InnoBoard-Pi.dts
View File

@@ -819,7 +819,7 @@
#address-cells = <0x1>;
#size-cells = <0x0>;
rgmii0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id4f51.e91b";
device_type = "ethernet-phy";
reg = <0x1>;
phy-mode = "rgmii";
@@ -859,7 +859,7 @@
#address-cells = <0x1>;
#size-cells = <0x0>;
rgmii1: phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id4f51.e91b";
device_type = "ethernet-phy";
reg = <0x1>;
phy-mode = "rgmii";
@@ -1099,9 +1099,6 @@
&rcpu {
/* pinctrl-names = "default"; */
/* pinctrl-0 = <&pinctrl_rcpu>; */
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

4
arch/riscv/boot/dts/spacemit/k1-x_LX-V10.dts
View File

@@ -468,6 +468,7 @@
ext_rtc: rtc {
compatible = "pmic,rtc,spm8821";
status = "disabled";
};
ext_adc: adc {
@@ -911,9 +912,6 @@
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

5
arch/riscv/boot/dts/spacemit/k1-x_MINI-PC.dts
View File

@@ -14,7 +14,7 @@
/ {
model = "spacemit k1-x MINI-PC board";
modules_usrload = "8852bs";
modules_usrload = "rtw89_core, rtw89_pci, rtw89_8852b, rtw89_8852be";
cpus: cpus {
#address-cells = <1>;
@@ -850,9 +850,6 @@
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

3
arch/riscv/boot/dts/spacemit/k1-x_MUSE-Book.dts
View File

@@ -828,9 +828,6 @@
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

3
arch/riscv/boot/dts/spacemit/k1-x_MUSE-Card.dts
View File

@@ -900,9 +900,6 @@
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

3
arch/riscv/boot/dts/spacemit/k1-x_MUSE-N1.dts
View File

@@ -743,8 +743,5 @@
};
&rcpu {
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

5
arch/riscv/boot/dts/spacemit/k1-x_MUSE-Paper-mini-4g.dts
View File

@@ -816,7 +816,7 @@
SDHCI_QUIRK2_BROKEN_PHY_MODULE
)>;
spacemit,rx_dline_reg = <0x0>;
spacemit,tx_delaycode = <0x30>;
spacemit,tx_delaycode = <0xa8 0x78>;
spacemit,rx_tuning_limit = <50>;
spacemit,sdh-freq = <375000000>;
status = "okay";
@@ -1068,9 +1068,6 @@
};
&rcpu {
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

1280
arch/riscv/boot/dts/spacemit/k1-x_MUSE-Paper.dts
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File diff suppressed because it is too large Load Diff

5
arch/riscv/boot/dts/spacemit/k1-x_MUSE-Paper2.dts
View File

@@ -916,7 +916,7 @@
SDHCI_QUIRK2_BROKEN_PHY_MODULE
)>;
spacemit,rx_dline_reg = <0x0>;
spacemit,tx_delaycode = <0xaf>;
spacemit,tx_delaycode = <0xa8 0x78>;
spacemit,rx_tuning_limit = <50>;
spacemit,sdh-freq = <375000000>;
status = "okay";
@@ -1253,9 +1253,6 @@
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

39
arch/riscv/boot/dts/spacemit/k1-x_MUSE-Pi-Pro.dts
View File

@@ -297,14 +297,14 @@
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_2>;
status = "disabled";
pinctrl-0 = <&pinctrl_i2c3_0>;
status = "okay";
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_2>;
status = "disabled";
pinctrl-0 = <&pinctrl_i2c4_0>;
status = "okay";
};
&i2c5 {
@@ -620,6 +620,12 @@
>;
};
pinctrl_rpwm7_0: rpwm7_0_grp {
pinctrl-single,pins = <
K1X_PADCONF(GPIO_52, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* rcpu_pwm7 */
>;
};
pinctrl_gmac0: gmac0_grp {
pinctrl-single,pins =<
K1X_PADCONF(GPIO_00, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rxdv */
@@ -770,7 +776,7 @@
SDHCI_QUIRK2_BROKEN_PHY_MODULE
)>;
spacemit,rx_dline_reg = <0x0>;
spacemit,tx_delaycode = <0xaf>;
spacemit,tx_delaycode = <0xa8 0x78>;
spacemit,rx_tuning_limit = <50>;
spacemit,sdh-freq = <375000000>;
status = "okay";
@@ -966,7 +972,9 @@
&spi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssp3_0>;
status = "disabled";
k1x,ssp-disable-dma;
status = "okay";
k1x,ssp-clock-rate = <25600000>;
};
&pwm_bl {
@@ -1081,9 +1089,10 @@
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};
&r_uart0 {
status = "okay";
};
@@ -1112,3 +1121,15 @@
sound-dai = <&es8326>;
};
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4_1>;
status = "okay";
};
&rpwm7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rpwm7_0>;
status = "okay";
};

15
arch/riscv/boot/dts/spacemit/k1-x_MUSE-Pi.dts
View File

@@ -188,6 +188,10 @@
status = "okay";
};
&r_uart0 {
status = "okay";
};
&pwm14 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm14_1>;
@@ -294,7 +298,7 @@
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_2>;
status = "disabled";
status = "okay";
};
&i2c6 {
@@ -717,7 +721,7 @@
SDHCI_QUIRK2_BROKEN_PHY_MODULE
)>;
spacemit,rx_dline_reg = <0x0>;
spacemit,tx_delaycode = <0x9f>;
spacemit,tx_delaycode = <0x8f 0x5f>;
spacemit,rx_tuning_limit = <50>;
spacemit,sdh-freq = <375000000>;
status = "okay";
@@ -936,7 +940,9 @@
&spi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssp3_0>;
status = "disabled";
k1x,ssp-disable-dma;
status = "okay";
k1x,ssp-clock-rate = <25600000>;
};
&pwm_bl {
@@ -1063,9 +1069,6 @@
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

7
arch/riscv/boot/dts/spacemit/k1-x_NetBridge-C1.dts
View File

@@ -94,8 +94,8 @@
linux,cma {
compatible = "shared-dma-pool";
/* alloc memory from 0x40000000~0x80000000 */
alloc-ranges = <0 0x40000000 0 0x40000000>;
/* alloc memory from 0x40000000~0x70000000 */
alloc-ranges = <0 0x40000000 0 0x30000000>;
/* size of cma buffer is 384MByte */
size = <0 0x18000000>;
/* start address is 1Mbyte aligned */
@@ -744,9 +744,6 @@
&rcpu {
/* pinctrl-names = "default"; */
/* pinctrl-0 = <&pinctrl_rcpu>; */
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "disabled";
};

5
arch/riscv/boot/dts/spacemit/k1-x_ZT001H.dts
View File

@@ -688,7 +688,7 @@
SDHCI_QUIRK2_BROKEN_PHY_MODULE
)>;
spacemit,rx_dline_reg = <0x0>;
spacemit,tx_delaycode = <0xaf>;
spacemit,tx_delaycode = <0xa8 0x78>;
spacemit,rx_tuning_limit = <50>;
spacemit,sdh-freq = <375000000>;
status = "okay";
@@ -934,9 +934,6 @@
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

3
arch/riscv/boot/dts/spacemit/k1-x_baton-camera.dts
View File

@@ -899,9 +899,6 @@
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

3
arch/riscv/boot/dts/spacemit/k1-x_bit-brick.dts
View File

@@ -1019,9 +1019,6 @@
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

5
arch/riscv/boot/dts/spacemit/k1-x_deb1.dts
View File

@@ -706,7 +706,7 @@
SDHCI_QUIRK2_BROKEN_PHY_MODULE
)>;
spacemit,rx_dline_reg = <0x0>;
spacemit,tx_delaycode = <0x8f>;
spacemit,tx_delaycode = <0x8f 0x5f>;
spacemit,rx_tuning_limit = <50>;
spacemit,sdh-freq = <375000000>;
status = "okay";
@@ -1032,9 +1032,6 @@
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

4
arch/riscv/boot/dts/spacemit/k1-x_deb2.dts
View File

@@ -625,6 +625,7 @@
SDHCI_QUIRK2_BROKEN_PHY_MODULE
)>;
spacemit,rx_dline_reg = <0x0>;
spacemit,tx_delaycode = <0x8f 0x5f>;
spacemit,rx_tuning_limit = <50>;
spacemit,sdh-freq = <375000000>;
status = "okay";
@@ -982,9 +983,6 @@
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

3
arch/riscv/boot/dts/spacemit/k1-x_evb.dts
View File

@@ -870,9 +870,6 @@
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

838
arch/riscv/boot/dts/spacemit/k1-x_hs450.dts
View File

@@ -1,838 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2023 Spacemit, Inc */
/dts-v1/;
#include "k1-x.dtsi"
#include "k1-x-efuse.dtsi"
#include "k1-x_pinctrl.dtsi"
#include "lcd/lcd_lt8911_edp_1920x1200.dtsi"
#include "k1-x-lcd.dtsi"
#include "k1-x-hdmi.dtsi"
#include "k1-x_opp_table.dtsi"
#include "k1-x_thermal_cooling.dtsi"
/ {
model = "spacemit k1-x hs450 board";
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <24000000>;
cpu_0: cpu@0 {
cpu-ai = "true";
};
cpu_1: cpu@1 {
cpu-ai = "true";
};
cpu_2: cpu@2 {
reg = <2>;
cpu-ai = "true";
};
cpu_3: cpu@3 {
reg = <3>;
cpu-ai = "true";
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu_0>;
};
core1 {
cpu = <&cpu_1>;
};
core2 {
cpu = <&cpu_2>;
};
core3 {
cpu = <&cpu_3>;
};
};
cluster1 {
core0 {
cpu = <&cpu_4>;
};
core1 {
cpu = <&cpu_5>;
};
core2 {
cpu = <&cpu_6>;
};
core3 {
cpu = <&cpu_7>;
};
};
};
};
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x80000000>;
};
memory@100000000 {
device_type = "memory";
reg = <0x1 0x00000000 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
/* alloc memory from 0x40000000~0x70000000 */
alloc-ranges = <0 0x40000000 0 0x30000000>;
/* size of cma buffer is 384MByte */
size = <0 0x18000000>;
/* start address is 1Mbyte aligned */
alignment = <0x0 0x100000>;
linux,cma-default;
/* besides hardware, dma for ex. buffer can be used by memory management */
reusable;
};
/* reserved 384K for dpu, including mmu table(256K) and cmdlist(128K) */
dpu_resv: dpu_reserved@2ff40000 {
compatible = "shared-dma-pool";
reg = <0x0 0x2ff40000 0x0 0x000C0000>;
no-map;
};
};
chosen {
bootargs = "earlycon=sbi console=ttyS0,115200n8 loglevel=8 swiotlb=65536 rdinit=/init";
stdout-path = "serial0:115200n8";
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc4v0_baseboard: vcc4v0-baseboard {
compatible = "regulator-fixed";
regulator-name = "vcc4v0_baseboard";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <4000000>;
regulator-max-microvolt = <4000000>;
vin-supply = <&dc_12v>;
};
vcc_touchpad: vcc-touchpad {
compatible = "regulator-fixed";
regulator-name = "vcc_touchpad";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
regulator-boot-on;
gpios = <&gpio 112 0>;
vin-supply = <&ldo_7>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_2>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&pwm14 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm14_1>;
status = "okay";
};
&dpu_online2_dsi {
memory-region = <&dpu_resv>;
spacemit-dpu-bitclk = <1000000000>;
dsi_1v2-supply = <&ldo_17>;
vin-supply-names = "dsi_1v2";
status = "okay";
};
&dsi2 {
status = "okay";
force-attached = "lcd_lt8911_edp_1920x1200";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dsi1_output: endpoint@1 {
reg = <1>;
remote-endpoint = <&lt8911exb_in>;
};
};
};
edp_panel: panel@0 {
status = "ok";
// compatible = "spacemit,edp-panel";
};
};
&lcds {
status = "okay";
};
&dpu_online2_hdmi {
memory-region = <&dpu_resv>;
status = "disabled";
};
&hdmi{
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_0>;
use-no-edid;
status = "disabled";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
spacemit,i2c-fast-mode;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "disabled";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_0>;
spacemit,i2c-fast-mode;
status = "okay";
es8326: es8326@19{
compatible = "everest,es8326";
reg = <0x19>;
#sound-dai-cells = <0>;
interrupt-parent = <&gpio>;
interrupts = <126 1>;
spk-ctl-gpio = <&gpio 127 0>;
everest,jack-detect-inverted;
everest,mic1-src = [44];
everest,mic2-src = [66];
status = "okay";
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_2>;
status = "okay";
touchpad: hid@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
hid-descr-addr = <0x0020>;
post-power-on-delay-ms = <200>;
vdd-supply = <&vcc_touchpad>;
interrupt-parent = <&gpio>;
interrupts = <62 2>;
status = "okay";
};
};
&i2c6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c6_2>;
clock-frequency = <100000>;
status = "okay";
lt8911exb_i2c@29 {
compatible = "lontium,lt8911exb";
reg = <0x29>;
reset-gpio = <&gpio 81 0>;
enable-gpio = <&gpio 83 0>;
bl-gpio = <&gpio 82 0>;
status = "okay";
port {
lt8911exb_in: endpoint {
remote-endpoint = <&dsi1_output>;
};
};
};
};
&i2c8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c8>;
status = "okay";
pm853: pmic@30 {
compatible = "spacemit,pm853";
reg = <0x30>;
vcc_sys-supply = <&vcc4v0_baseboard>;
dcdc5-supply = <&dcdc_5>;
dcdc2-supply = <&dcdc_2>;
regulators {
compatible = "pmic,regulator,pm853";
/* buck */
dcdc_1: DCDC_REG1 {
regulator-name = "dcdc1";
regulator-min-microvolt = <480000>;
regulator-max-microvolt = <3160000>;
regulator-always-on;
};
dcdc_2: DCDC_REG2 {
regulator-name = "dcdc2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3950000>;
regulator-always-on;
};
dcdc_3: DCDC_REG3 {
regulator-name = "dcdc3";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3950000>;
};
dcdc_4: DCDC_REG4 {
regulator-name = "dcdc4";
regulator-min-microvolt = <480000>;
regulator-max-microvolt = <3160000>;
regulator-always-on;
};
dcdc_5: DCDC_REG5 {
regulator-name = "dcdc5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3950000>;
regulator-always-on;
};
/* ldo */
ldo_1: LDO_REG1 {
regulator-name = "ldo1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
};
ldo_2: LDO_REG2 {
regulator-name = "ldo2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo_3: LDO_REG3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
};
ldo_4: LDO_REG4 {
regulator-name = "ldo4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
};
ldo_5: LDO_REG5 {
regulator-name = "ldo5";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1900000>;
regulator-always-on;
};
ldo_6: LDO_REG6 {
regulator-name = "ldo6";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
};
ldo_7: LDO_REG7 {
regulator-name = "ldo7";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1950000>;
regulator-always-on;
};
ldo_8: LDO_REG8 {
regulator-name = "ldo8";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
};
ldo_9: LDO_REG9 {
regulator-name = "ldo9";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo_10: LDO_REG10 {
regulator-name = "ldo10";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
};
ldo_11: LDO_REG11 {
regulator-name = "ldo11";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1950000>;
};
ldo_12: LDO_REG12 {
regulator-name = "ldo12";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
};
ldo_13: LDO_REG13 {
regulator-name = "ldo13";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
};
ldo_14: LDO_REG14 {
regulator-name = "ldo14";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo_15: LDO_REG15 {
regulator-name = "ldo15";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1950000>;
};
ldo_16: LDO_REG16 {
regulator-name = "ldo16";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
};
ldo_17: LDO_REG17 {
regulator-name = "ldo17";
regulator-min-microvolt = <100000>;
regulator-max-microvolt = <1350000>;
};
ldo_18: LDO_REG18 {
regulator-name = "ldo18";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1950000>;
regulator-always-on;
};
ldo_19: LDO_REG19 {
regulator-name = "ldo19";
regulator-min-microvolt = <100000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
};
ldo_20: LDO_REG20 {
regulator-name = "ldo20";
regulator-min-microvolt = <100000>;
regulator-max-microvolt = <1350000>;
};
ldo_21: LDO_REG21 {
regulator-name = "ldo21";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1950000>;
};
ldo_22: LDO_REG22 {
regulator-name = "ldo22";
regulator-min-microvolt = <100000>;
regulator-max-microvolt = <1350000>;
};
sw_1: SWITCH_REG1 {
regulator-name = "switch1";
};
};
};
sy8810l: sy8810l@70 {
compatible = "spacemit,sy8810l";
reg = <0x70>;
dcdc1-supply = <&dcdc_1>;
regulators {
compatible = "pmic,regulator,sy8810l";
edcdc_1: EDCDC_REG1 {
regulator-name = "edcdc1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
};
};
};
&pinctrl {
pinctrl-single,gpio-range = <
&range GPIO_49 2 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_3V_DS4)
&range GPIO_58 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_62 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_3V_DS4)
&range GPIO_63 2 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_65 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
&range GPIO_66 2 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_74 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
&range GPIO_80 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_3V_DS4)
&range GPIO_81 3 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
&range GPIO_90 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_91 2 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
&range DVL0 2 (MUX_MODE1 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_110 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_112 2 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_3V_DS4)
&range GPIO_114 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_115 3 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_123 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_125 3 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
>;
pinctrl_rcpu: pinctrl_rcpu_grp {
pinctrl-single,pins = <
K1X_PADCONF(GPIO_47, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* r_uart0_tx */
K1X_PADCONF(GPIO_48, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* r_uart0_rx */
>;
};
};
&gpio{
gpio-ranges = <
&pinctrl 49 GPIO_49 2
&pinctrl 58 GPIO_58 1
&pinctrl 62 GPIO_62 6
&pinctrl 74 GPIO_74 1
&pinctrl 80 GPIO_80 4
&pinctrl 90 GPIO_90 3
&pinctrl 96 DVL0 2
&pinctrl 110 GPIO_110 1
&pinctrl 112 GPIO_112 1
&pinctrl 114 GPIO_114 4
&pinctrl 123 GPIO_123 1
&pinctrl 125 GPIO_125 3
>;
};
/* SD */
&sdhci0 {
pinctrl-names = "default","fast";
pinctrl-0 = <&pinctrl_mmc1>;
pinctrl-1 = <&pinctrl_mmc1_fast>;
bus-width = <4>;
cd-gpios = <&gpio 80 0>;
cd-inverted;
vmmc-supply = <&ldo_4>;
vqmmc-supply = <&ldo_9>;
no-mmc;
no-sdio;
spacemit,sdh-host-caps-disable = <(
MMC_CAP_UHS_SDR12 |
MMC_CAP_UHS_SDR25
)>;
spacemit,sdh-quirks = <(
SDHCI_QUIRK_BROKEN_CARD_DETECTION |
SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
)>;
spacemit,sdh-quirks2 = <(
SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
SDHCI_QUIRK2_BROKEN_PHY_MODULE |
SDHCI_QUIRK2_SET_AIB_MMC
)>;
spacemit,aib_mmc1_io_reg = <0xD401E81C>;
spacemit,apbc_asfar_reg = <0xD4015050>;
spacemit,apbc_assar_reg = <0xD4015054>;
spacemit,rx_dline_reg = <0x0>;
spacemit,tx_dline_reg = <0x0>;
spacemit,tx_delaycode = <0x7f>;
spacemit,rx_tuning_limit = <50>;
spacemit,sdh-freq = <204800000>;
status = "okay";
};
/* SDIO */
&sdhci1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc2>;
bus-width = <4>;
non-removable;
vqmmc-supply = <&ldo_7>;
no-mmc;
no-sd;
keep-power-in-suspend;
/* bcmdhd use private oob solution rather than dat1/standard wakeup */
/delete-property/ enable-sdio-wakeup;
spacemit,sdh-host-caps-disable = <(
MMC_CAP_UHS_DDR50 |
MMC_CAP_NEEDS_POLL
)>;
spacemit,sdh-quirks = <(
SDHCI_QUIRK_BROKEN_CARD_DETECTION |
SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
)>;
spacemit,sdh-quirks2 = <(
SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
SDHCI_QUIRK2_BROKEN_PHY_MODULE
)>;
spacemit,rx_dline_reg = <0x0>;
spacemit,rx_tuning_limit = <50>;
spacemit,sdh-freq = <375000000>;
status = "okay";
};
/* eMMC */
&sdhci2 {
bus-width = <8>;
non-removable;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
no-sd;
no-sdio;
spacemit,sdh-quirks = <(
SDHCI_QUIRK_BROKEN_CARD_DETECTION |
SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
)>;
spacemit,sdh-quirks2 = <(
SDHCI_QUIRK2_PRESET_VALUE_BROKEN
)>;
spacemit,sdh-freq = <375000000>;
status = "okay";
};
&usbphy {
status = "okay";
};
&udc {
/*spacemit,udc-mode = <MV_USB_MODE_OTG>;*/
spacemit,udc-mode = <MV_USB_MODE_UDC>;
status = "okay";
};
&ehci {
spacemit,reset-on-resume;
spacemit,udc-mode = <MV_USB_MODE_OTG>;
status = "disabled";
};
&otg {
usb-role-switch;
role-switch-user-control;
spacemit,reset-on-resume;
role-switch-default-mode = "peripheral";
vbus-gpios = <&gpio 123 0>;
status = "disabled";
};
&usbphy1 {
status = "okay";
};
&udc1 {
/*spacemit,udc-mode = <MV_USB_MODE_UDC>;*/
spacemit,udc-mode = <MV_USB_MODE_OTG>;
status = "disabled";
};
&ehci1 {
spacemit,reset-on-resume;
status = "okay";
};
&otg1 {
usb-role-switch;
role-switch-user-control;
spacemit,reset-on-resume;
role-switch-default-mode = "host";
vbus-gpios = <&gpio 123 0>;
status = "disabled";
};
&usb2phy {
status = "okay";
};
&combphy {
status = "okay";
};
&usbdrd3 {
status = "okay";
reset-on-resume;
dwc3@c0a00000 {
dr_mode = "host";
phy_type = "utmi";
snps,hsphy_interface = "utmi";
snps,dis_enblslpm_quirk;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,parkmode-disable-ss-quirk;
};
};
&pcie1_rc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1_3>;
status = "okay";
};
&imggpu {
status = "okay";
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <26500000>;
m25p,fast-read;
broken-flash-reset;
status = "okay";
};
};
&pwm_bl {
pwms = <&pwm14 2000>;
brightness-levels = <
0 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60
60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60
60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60
60 60 60 60 60 60 60 60 60 60 60 60 60 61 62 63
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255
>;
default-brightness-level = <128>;
status = "okay";
};
&cpu_0 {
clst-supply = <&edcdc_1>;
};
&cpu_1 {
clst-supply = <&edcdc_1>;
};
&cpu_2 {
clst-supply = <&edcdc_1>;
};
&cpu_3 {
clst-supply = <&edcdc_1>;
};
&cpu_4 {
clst-supply = <&edcdc_1>;
};
&cpu_5 {
clst-supply = <&edcdc_1>;
};
&cpu_6 {
clst-supply = <&edcdc_1>;
};
&cpu_7 {
clst-supply = <&edcdc_1>;
};
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};
&i2s0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sspa0_0>;
status = "okay";
};
&hdmiaudio {
status = "disabled";
};
&sound_hdmi {
status = "disabled";
simple-audio-card,cpu {
sound-dai = <&hdmiaudio>;
};
};
&sound_codec {
status = "okay";
simple-audio-card,name = "snd-es8326";
spacemit,mclk-fs = <64>;
simple-audio-card,codec {
sound-dai = <&es8326>;
};
};
&watchdog {
spa,wdt-enable-restart-handler;
};

865
arch/riscv/boot/dts/spacemit/k1-x_kx312.dts
View File

@@ -1,865 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2023 Spacemit, Inc */
/dts-v1/;
#include "k1-x.dtsi"
#include "k1-x-efuse.dtsi"
#include "k1-x_pinctrl.dtsi"
#include "lcd/lcd_lt8911_edp_1920x1080.dtsi"
#include "k1-x-lcd.dtsi"
#include "k1-x-hdmi.dtsi"
#include "k1-x_opp_table.dtsi"
#include "k1-x_thermal_cooling.dtsi"
/ {
model = "spacemit k1-x kx312 board";
modules_usrload = "rtw89_core, rtw89_pci, rtw89_8852b, rtw89_8852be";
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <24000000>;
cpu_0: cpu@0 {
cpu-ai = "true";
};
cpu_1: cpu@1 {
cpu-ai = "true";
};
cpu_2: cpu@2 {
reg = <2>;
cpu-ai = "true";
};
cpu_3: cpu@3 {
reg = <3>;
cpu-ai = "true";
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu_0>;
};
core1 {
cpu = <&cpu_1>;
};
core2 {
cpu = <&cpu_2>;
};
core3 {
cpu = <&cpu_3>;
};
};
cluster1 {
core0 {
cpu = <&cpu_4>;
};
core1 {
cpu = <&cpu_5>;
};
core2 {
cpu = <&cpu_6>;
};
core3 {
cpu = <&cpu_7>;
};
};
};
};
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x80000000>;
};
memory@100000000 {
device_type = "memory";
reg = <0x1 0x00000000 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
/* alloc memory from 0x40000000~0x70000000 */
alloc-ranges = <0 0x40000000 0 0x30000000>;
/* size of cma buffer is 384MByte */
size = <0 0x18000000>;
/* start address is 1Mbyte aligned */
alignment = <0x0 0x100000>;
linux,cma-default;
/* besides hardware, dma for ex. buffer can be used by memory management */
reusable;
};
/* reserved 384K for dpu, including mmu table(256K) and cmdlist(128K) */
dpu_resv: dpu_reserved@2ff40000 {
compatible = "shared-dma-pool";
reg = <0x0 0x2ff40000 0x0 0x000C0000>;
no-map;
};
};
chosen {
bootargs = "earlycon=sbi console=ttyS0,115200n8 loglevel=8 swiotlb=65536 rdinit=/init";
stdout-path = "serial0:115200n8";
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc4v0_baseboard: vcc4v0-baseboard {
compatible = "regulator-fixed";
regulator-name = "vcc4v0_baseboard";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <4000000>;
regulator-max-microvolt = <4000000>;
vin-supply = <&dc_12v>;
};
vcc_touchpad: vcc-touchpad {
compatible = "regulator-fixed";
regulator-name = "vcc_touchpad";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
regulator-boot-on;
gpios = <&gpio 49 0>;
vin-supply = <&ldo_8>;
};
spacemit_lid:spacemit_lid {
compatible = "spacemit,k1x-lid";
scan-interval-ms = <1000>;
lid-gpios = <&gpio 74 0>;
};
rf_pwrseq: rf-pwrseq {
compatible = "spacemit,rf-pwrseq";
status = "okay";
wlan_pwrseq: wlan-pwrseq {
compatible = "spacemit,wlan-pwrseq";
regon-gpios = <&gpio 76 0>;
device_type = "pcie";
};
bt_pwrseq: bt-pwrseq {
compatible = "spacemit,bt-pwrseq";
reset-gpios = <&gpio 78 0>;
};
};
};
&pinctrl {
pinctrl_uart3_0: uart3_0_grp {
pinctrl-single,pins =<
K1X_PADCONF(GPIO_81, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_txd */
K1X_PADCONF(GPIO_82, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_rxd */
/* K1X_PADCONF(GPIO_83, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2))*/ /* uart3_cts_n */
/* K1X_PADCONF(GPIO_84, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2))*/ /* uart3_rts_n */
>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_0>;
status = "okay";
};
&pwm14 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm14_1>;
status = "okay";
};
&dpu_online2_dsi {
memory-region = <&dpu_resv>;
spacemit-dpu-bitclk = <933000000>;
dsi_1v2-supply = <&ldo_5>;
vin-supply-names = "dsi_1v2";
status = "okay";
};
&dsi2 {
status = "okay";
force-attached = "lcd_lt8911_edp_1920x1080";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dsi1_output: endpoint@1 {
reg = <1>;
remote-endpoint = <&lt8911exb_in>;
};
};
};
edp_panel: panel@0 {
status = "ok";
compatible = "spacemit,edp-panel";
};
};
&lcds {
status = "okay";
};
&dpu_online2_hdmi {
memory-region = <&dpu_resv>;
status = "okay";
};
&hdmi{
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_0>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_0>;
spacemit,i2c-fast-mode;
status = "okay";
eeprom@50{
compatible = "atmel,24c02";
reg = <0x50>;
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&power K1X_PMU_DUMMY_PWR_DOMAIN>;
status = "okay";
mac_address0: mac_address0@0 {
reg = <0x0 6>;
};
mac_address1: mac_address1@6 {
reg = <0x6 6>;
};
};
es8326: es8326@19{
compatible = "everest,es8326";
reg = <0x19>;
#sound-dai-cells = <0>;
interrupt-parent = <&gpio>;
interrupts = <126 1>;
spk-ctl-gpio = <&gpio 127 0>;
everest,jack-detect-inverted;
everest,mic1-src = [44];
everest,mic2-src = [66];
status = "okay";
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_2>;
status = "okay";
touchpad: hid@2d {
compatible = "hid-over-i2c";
reg = <0x2d>;
hid-descr-addr = <0x0020>;
post-power-on-delay-ms = <200>;
vdd-supply = <&vcc_touchpad>;
interrupt-parent = <&gpio>;
interrupts = <50 2>;
status = "okay";
};
battery: battery@b {
compatible = "sbs,sbs-battery";
reg = <0x0b>;
sbs,i2c-retry-count = <2>;
sbs,poll-retry-count = <1>;
};
};
&i2c6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c6_2>;
clock-frequency = <100000>;
status = "okay";
lt8911exb_i2c@29 {
compatible = "lontium,lt8911exb";
reg = <0x29>;
reset-gpio = <&gpio 114 0>;
enable-gpio = <&gpio 83 0>;
bl-gpio = <&gpio 75 0>;
standby-gpio = <&gpio 92 0>;
status = "okay";
port {
lt8911exb_in: endpoint {
remote-endpoint = <&dsi1_output>;
};
};
};
};
&i2c8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c8>;
status = "okay";
spm8821@41 {
compatible = "spacemit,spm8821";
reg = <0x41>;
interrupt-parent = <&intc>;
interrupts = <64>;
status = "okay";
vcc_sys-supply = <&vcc4v0_baseboard>;
dcdc5-supply = <&dcdc_5>;
regulators {
compatible = "pmic,regulator,spm8821";
/* buck */
dcdc_1: DCDC_REG1 {
regulator-name = "dcdc1";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3450000>;
regulator-ramp-delay = <5000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <650000>;
};
};
dcdc_2: DCDC_REG2 {
regulator-name = "dcdc2";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3450000>;
regulator-ramp-delay = <5000>;
regulator-always-on;
};
dcdc_3: DCDC_REG3 {
regulator-name = "dcdc3";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <5000>;
regulator-always-on;
};
dcdc_4: DCDC_REG4 {
regulator-name = "dcdc4";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <5000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
dcdc_5: DCDC_REG5 {
regulator-name = "dcdc5";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3450000>;
regulator-ramp-delay = <5000>;
regulator-always-on;
};
dcdc_6: DCDC_REG6 {
regulator-name = "dcdc6";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3450000>;
regulator-ramp-delay = <5000>;
regulator-always-on;
};
/* aldo */
ldo_1: LDO_REG1 {
regulator-name = "ldo1";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <500000>;
};
};
ldo_2: LDO_REG2 {
regulator-name = "ldo2";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <500000>;
};
};
ldo_3: LDO_REG3 {
regulator-name = "ldo3";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <500000>;
};
};
ldo_4: LDO_REG4 {
regulator-name = "ldo4";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <500000>;
};
};
/* dldo */
ldo_5: LDO_REG5 {
regulator-name = "ldo5";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <500000>;
};
};
ldo_6: LDO_REG6 {
regulator-name = "ldo6";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <500000>;
};
};
ldo_7: LDO_REG7 {
regulator-name = "ldo7";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <500000>;
};
};
ldo_8: LDO_REG8 {
regulator-name = "ldo8";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-always-on;
};
ldo_9: LDO_REG9 {
regulator-name = "ldo9";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
};
ldo_10: LDO_REG10 {
regulator-name = "ldo10";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-always-on;
};
ldo_11: LDO_REG11 {
regulator-name = "ldo11";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
};
sw_1: SWITCH_REG1 {
regulator-name = "switch1";
};
};
pmic_pinctrl: pinctrl {
compatible = "pmic,pinctrl,spm8821";
gpio-controller;
#gpio-cells = <2>;
spacemit,npins = <6>;
/**
* led_pins: led-pins {
* pins = "PIN3";
* function = "sleep";
* bias-disable = <0>;
* drive-open-drain = <0x1>;
* };
*/
};
pwr_key: key {
compatible = "pmic,pwrkey,spm8821";
};
ext_rtc: rtc {
compatible = "pmic,rtc,spm8821";
};
ext_adc: adc {
compatible = "pmic,adc,spm8821";
};
};
};
&pinctrl {
pinctrl-single,gpio-range = <
&range GPIO_49 2 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_3V_DS4)
&range GPIO_58 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
&range GPIO_63 2 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
&range GPIO_65 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
&range GPIO_66 2 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_3V_DS4)
&range PRI_TDI 2 (MUX_MODE1 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
&range PRI_TCK 1 (MUX_MODE1 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range PRI_TDO 1 (MUX_MODE1 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
&range GPIO_74 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
&range GPIO_76 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_3V_DS4)
&range GPIO_78 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_3V_DS4)
&range GPIO_80 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_3V_DS4)
&range GPIO_81 3 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
&range GPIO_90 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_91 2 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
&range DVL0 2 (MUX_MODE1 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_110 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_114 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_115 2 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_123 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_124 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
&range GPIO_125 3 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
>;
pinctrl_rcpu: pinctrl_rcpu_grp {
pinctrl-single,pins = <
K1X_PADCONF(GPIO_47, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* r_uart0_tx */
K1X_PADCONF(GPIO_48, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* r_uart0_rx */
>;
};
};
&gpio{
gpio-ranges = <
&pinctrl 49 GPIO_49 2
&pinctrl 58 GPIO_58 1
&pinctrl 63 GPIO_63 5
&pinctrl 70 PRI_TDI 4
&pinctrl 74 GPIO_74 1
&pinctrl 76 GPIO_76 1
&pinctrl 78 GPIO_78 1
&pinctrl 80 GPIO_80 4
&pinctrl 90 GPIO_90 3
&pinctrl 96 DVL0 2
&pinctrl 110 GPIO_110 1
&pinctrl 114 GPIO_114 3
&pinctrl 123 GPIO_123 5
>;
};
/* SD */
&sdhci0 {
pinctrl-names = "default","fast";
pinctrl-0 = <&pinctrl_mmc1>;
pinctrl-1 = <&pinctrl_mmc1_fast>;
bus-width = <4>;
cd-gpios = <&gpio 80 0>;
cd-inverted;
vmmc-supply = <&dcdc_4>;
vqmmc-supply = <&ldo_1>;
no-mmc;
no-sdio;
spacemit,sdh-host-caps-disable = <(
MMC_CAP_UHS_SDR12 |
MMC_CAP_UHS_SDR25
)>;
spacemit,sdh-quirks = <(
SDHCI_QUIRK_BROKEN_CARD_DETECTION |
SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
)>;
spacemit,sdh-quirks2 = <(
SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
SDHCI_QUIRK2_BROKEN_PHY_MODULE |
SDHCI_QUIRK2_SET_AIB_MMC
)>;
spacemit,aib_mmc1_io_reg = <0xD401E81C>;
spacemit,apbc_asfar_reg = <0xD4015050>;
spacemit,apbc_assar_reg = <0xD4015054>;
spacemit,rx_dline_reg = <0x0>;
spacemit,tx_dline_reg = <0x0>;
spacemit,tx_delaycode = <0x7f>;
spacemit,rx_tuning_limit = <50>;
spacemit,sdh-freq = <204800000>;
status = "okay";
};
/* SDIO */
&sdhci1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc2>;
bus-width = <4>;
non-removable;
vqmmc-supply = <&dcdc_3>;
no-mmc;
no-sd;
keep-power-in-suspend;
/* bcmdhd use private oob solution rather than dat1/standard wakeup */
/delete-property/ enable-sdio-wakeup;
spacemit,sdh-host-caps-disable = <(
MMC_CAP_UHS_DDR50 |
MMC_CAP_NEEDS_POLL
)>;
spacemit,sdh-quirks = <(
SDHCI_QUIRK_BROKEN_CARD_DETECTION |
SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
)>;
spacemit,sdh-quirks2 = <(
SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
SDHCI_QUIRK2_BROKEN_PHY_MODULE
)>;
spacemit,rx_dline_reg = <0x0>;
spacemit,rx_tuning_limit = <50>;
spacemit,sdh-freq = <375000000>;
status = "okay";
};
/* eMMC */
&sdhci2 {
bus-width = <8>;
non-removable;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
no-sd;
no-sdio;
spacemit,sdh-quirks = <(
SDHCI_QUIRK_BROKEN_CARD_DETECTION |
SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
)>;
spacemit,sdh-quirks2 = <(
SDHCI_QUIRK2_PRESET_VALUE_BROKEN
)>;
spacemit,sdh-freq = <375000000>;
status = "okay";
};
&usbphy {
status = "okay";
};
&udc {
/*spacemit,udc-mode = <MV_USB_MODE_OTG>;*/
spacemit,udc-mode = <MV_USB_MODE_UDC>;
status = "okay";
};
&ehci {
spacemit,reset-on-resume;
spacemit,udc-mode = <MV_USB_MODE_OTG>;
status = "disabled";
};
&otg {
usb-role-switch;
role-switch-user-control;
spacemit,reset-on-resume;
role-switch-default-mode = "peripheral";
vbus-gpios = <&gpio 123 0>;
status = "disabled";
};
&usbphy1 {
status = "okay";
};
&udc1 {
/*spacemit,udc-mode = <MV_USB_MODE_UDC>;*/
spacemit,udc-mode = <MV_USB_MODE_OTG>;
status = "disabled";
};
&ehci1 {
spacemit,reset-on-resume;
status = "okay";
};
&otg1 {
usb-role-switch;
role-switch-user-control;
spacemit,reset-on-resume;
role-switch-default-mode = "host";
vbus-gpios = <&gpio 123 0>;
status = "disabled";
};
&usb2phy {
status = "okay";
};
&combphy {
status = "okay";
};
&usb3hub {
hub-gpios = <&gpio 123 0>; /* usb3 hub en */
status = "okay";
};
&usbdrd3 {
status = "okay";
reset-on-resume;
dwc3@c0a00000 {
dr_mode = "host";
phy_type = "utmi";
snps,hsphy_interface = "utmi";
snps,dis_enblslpm_quirk;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,parkmode-disable-ss-quirk;
};
};
&pcie1_rc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1_3>;
num-lanes = <1>;
status = "okay";
};
&pcie2_rc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie2_4>;
status = "okay";
};
&imggpu {
status = "okay";
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <26500000>;
m25p,fast-read;
broken-flash-reset;
status = "okay";
};
};
&pwm_bl {
pwms = <&pwm14 2000>;
brightness-levels = <
0 64 64 64 64 65 65 65 65 66 66 66 66 67 67 68
68 69 69 70 70 71 71 72 72 73 73 74 74 75 75 76
76 77 78 79 80 80 81 82 83 84 84 85 86 87 88 88
89 90 91 92 92 93 94 95 96 96 97 98 99 100 100 101
102 103 104 104 105 106 107 108 108 109 110 111 112 112 113 114
115 116 116 117 118 119 120 120 121 122 123 124 124 125 126 127
128 128 129 130 131 132 132 133 134 135 136 136 137 138 139 140
140 141 142 143 144 144 145 146 147 148 148 149 150 151 152 152
153 154 155 156 156 157 158 159 160 160 161 162 163 164 164 165
166 167 168 168 169 170 171 172 172 173 174 175 176 176 177 178
179 180 180 181 182 183 184 184 185 186 187 188 188 189 190 191
192 192 193 194 195 196 196 197 198 199 200 200 201 202 203 204
204 205 206 207 208 208 209 210 211 212 212 213 214 215 216 216
217 218 219 220 220 221 222 223 224 224 225 226 227 228 228 229
230 231 232 232 233 234 235 236 236 237 238 239 240 240 241 242
243 244 244 245 246 247 248 248 249 250 251 252 252 253 254 255
>;
default-brightness-level = <128>;
status = "okay";
};
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};
&i2s0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sspa0_0>;
status = "okay";
};
&hdmiaudio {
status = "okay";
};
&sound_hdmi {
status = "okay";
simple-audio-card,cpu {
sound-dai = <&hdmiaudio>;
};
};
&sound_codec {
status = "okay";
simple-audio-card,name = "snd-es8326";
spacemit,mclk-fs = <64>;
simple-audio-card,codec {
sound-dai = <&es8326>;
};
};

3
arch/riscv/boot/dts/spacemit/k1-x_lpi3a.dts
View File

@@ -1131,9 +1131,6 @@
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

5
arch/riscv/boot/dts/spacemit/k1-x_milkv-jupiter.dts
View File

@@ -728,7 +728,7 @@
SDHCI_QUIRK2_BROKEN_PHY_MODULE
)>;
spacemit,rx_dline_reg = <0x0>;
spacemit,tx_delaycode = <0x30>;
spacemit,tx_delaycode = <0xa8 0x78>;
spacemit,rx_tuning_limit = <50>;
spacemit,sdh-freq = <375000000>;
status = "okay";
@@ -1054,9 +1054,6 @@
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

288
arch/riscv/boot/dts/spacemit/k1-x_mingo.dts → arch/riscv/boot/dts/spacemit/k1-x_som.dts Normal file → Executable file
View File

@@ -10,7 +10,7 @@
#include "k1-x_thermal_cooling.dtsi"
/ {
model = "spacemit k1-x mingo board";
model = "spacemit k1-x som board";
cpus: cpus {
#address-cells = <1>;
@@ -111,7 +111,7 @@
};
chosen {
bootargs = "earlycon=sbi console=ttyS0,115200n8 loglevel=8 rdinit=/init";
bootargs = "earlycon=sbi console=ttyS0,115200n8 loglevel=8 swiotlb=65536 rdinit=/init";
stdout-path = "serial0:115200n8";
};
@@ -134,27 +134,15 @@
vin-supply = <&dc_12v>;
};
rf_pwrseq: rf-pwrseq {
compatible = "spacemit,rf-pwrseq";
//vdd-supply = <&ldo_7>;
//vdd_voltage = <3300000>;
io-supply = <&dcdc_3>;
io_voltage = <1800000>;
pwr-gpios = <&gpio 67 0>;
status = "okay";
leds {
compatible = "gpio-leds";
wlan_pwrseq: wlan-pwrseq {
compatible = "spacemit,wlan-pwrseq";
regon-gpios = <&gpio 116 0>;
interrupt-parent = <&pinctrl>;
interrupts = <268>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wlan_wakeup>;
};
bt_pwrseq: bt-pwrseq {
compatible = "spacemit,bt-pwrseq";
reset-gpios = <&gpio 63 0>;
led1 {
label = "sys-led";
gpios = <&gpio 96 0>;
linux,default-trigger = "heartbeat";
default-state = "on";
status = "okay";
};
};
};
@@ -171,6 +159,13 @@
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
spacemit,i2c-fast-mode;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_0>;
@@ -219,6 +214,7 @@
regulator-name = "dcdc1";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3450000>;
regulator-ramp-delay = <5000>;
regulator-always-on;
regulator-state-mem {
@@ -231,6 +227,7 @@
regulator-name = "dcdc2";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3450000>;
regulator-ramp-delay = <5000>;
regulator-always-on;
};
@@ -238,6 +235,7 @@
regulator-name = "dcdc3";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <5000>;
regulator-always-on;
};
@@ -245,13 +243,19 @@
regulator-name = "dcdc4";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <5000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
dcdc_5: DCDC_REG5 {
regulator-name = "dcdc5";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3450000>;
regulator-ramp-delay = <5000>;
regulator-always-on;
};
@@ -259,6 +263,7 @@
regulator-name = "dcdc6";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3450000>;
regulator-ramp-delay = <5000>;
regulator-always-on;
};
@@ -268,24 +273,40 @@
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <500000>;
};
};
ldo_2: LDO_REG2 {
regulator-name = "ldo2";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <500000>;
};
};
ldo_3: LDO_REG3 {
regulator-name = "ldo3";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <500000>;
};
};
ldo_4: LDO_REG4 {
regulator-name = "ldo4";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <500000>;
};
};
/* dldo */
@@ -294,18 +315,30 @@
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <500000>;
};
};
ldo_6: LDO_REG6 {
regulator-name = "ldo6";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <500000>;
};
};
ldo_7: LDO_REG7 {
regulator-name = "ldo7";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <500000>;
};
};
ldo_8: LDO_REG8 {
@@ -383,27 +416,45 @@
&range GPIO_81 3 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
&range GPIO_90 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_91 2 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
&range DVL0 2 (MUX_MODE1 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range DVL0 1 (MUX_MODE1 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range DVL1 1 (MUX_MODE1 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)
&range GPIO_110 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_111 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_113 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_114 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_115 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_116 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
&range GPIO_118 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
&range GPIO_123 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
&range GPIO_123 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)
&range GPIO_124 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
&range GPIO_125 3 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
>;
pinctrl_rcpu: pinctrl_rcpu_grp {
pinctrl-single,pins = <
K1X_PADCONF(GPIO_47, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* r_uart0_tx */
K1X_PADCONF(GPIO_48, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* r_uart0_rx */
K1X_PADCONF(GPIO_47, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* r_uart0_tx */
K1X_PADCONF(GPIO_48, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* r_uart0_rx */
>;
};
pinctrl_wlan_wakeup: wlan_wakeup_grp {
pinctrl_gmac0: gmac0_grp {
pinctrl-single,pins =<
K1X_PADCONF(GPIO_66, MUX_MODE0, (EDGE_FALL | PULL_DOWN | PAD_3V_DS2)) /* wifi edge detect */
K1X_PADCONF(GPIO_00, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rxdv */
K1X_PADCONF(GPIO_01, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_d0 */
K1X_PADCONF(GPIO_02, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_d1 */
K1X_PADCONF(GPIO_03, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_clk */
K1X_PADCONF(GPIO_04, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_d2 */
K1X_PADCONF(GPIO_05, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_d3 */
K1X_PADCONF(GPIO_06, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_d0 */
K1X_PADCONF(GPIO_07, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_d1 */
K1X_PADCONF(GPIO_08, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx */
K1X_PADCONF(GPIO_09, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_d2 */
K1X_PADCONF(GPIO_10, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_d3 */
K1X_PADCONF(GPIO_11, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_en */
K1X_PADCONF(GPIO_12, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS0)) /* gmac0_mdc */
K1X_PADCONF(GPIO_13, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS0)) /* gmac0_mdio */
K1X_PADCONF(GPIO_14, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_int_n */
K1X_PADCONF(GPIO_45, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_clk_ref */
>;
};
};
@@ -420,79 +471,14 @@
&pinctrl 90 GPIO_90 3
&pinctrl 96 DVL0 2
&pinctrl 110 GPIO_110 1
&pinctrl 111 GPIO_111 1
&pinctrl 113 GPIO_113 1
&pinctrl 114 GPIO_114 3
&pinctrl 118 GPIO_118 1
&pinctrl 123 GPIO_123 5
>;
};
/* SD */
&sdhci0 {
pinctrl-names = "default","fast";
pinctrl-0 = <&pinctrl_mmc1>;
pinctrl-1 = <&pinctrl_mmc1_fast>;
bus-width = <4>;
cd-gpios = <&gpio 80 0>;
cd-inverted;
vmmc-supply = <&dcdc_4>;
vqmmc-supply = <&ldo_1>;
no-mmc;
no-sdio;
spacemit,sdh-host-caps-disable = <(
MMC_CAP_UHS_SDR12 |
MMC_CAP_UHS_SDR25
)>;
spacemit,sdh-quirks = <(
SDHCI_QUIRK_BROKEN_CARD_DETECTION |
SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
)>;
spacemit,sdh-quirks2 = <(
SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
SDHCI_QUIRK2_BROKEN_PHY_MODULE |
SDHCI_QUIRK2_SET_AIB_MMC
)>;
spacemit,aib_mmc1_io_reg = <0xD401E81C>;
spacemit,apbc_asfar_reg = <0xD4015050>;
spacemit,apbc_assar_reg = <0xD4015054>;
spacemit,rx_dline_reg = <0x0>;
spacemit,tx_dline_reg = <0x0>;
spacemit,tx_delaycode = <0x7f>;
spacemit,rx_tuning_limit = <50>;
spacemit,sdh-freq = <204800000>;
status = "okay";
};
/* SDIO */
&sdhci1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc2>;
bus-width = <4>;
non-removable;
vqmmc-supply = <&dcdc_3>;
no-mmc;
no-sd;
keep-power-in-suspend;
/* bcmdhd use private oob solution rather than dat1/standard wakeup */
/delete-property/ enable-sdio-wakeup;
spacemit,sdh-host-caps-disable = <(
MMC_CAP_UHS_DDR50 |
MMC_CAP_NEEDS_POLL
)>;
spacemit,sdh-quirks = <(
SDHCI_QUIRK_BROKEN_CARD_DETECTION |
SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
)>;
spacemit,sdh-quirks2 = <(
SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
SDHCI_QUIRK2_BROKEN_PHY_MODULE
)>;
spacemit,rx_dline_reg = <0x0>;
spacemit,rx_tuning_limit = <50>;
spacemit,sdh-freq = <375000000>;
status = "okay";
};
/* eMMC */
&sdhci2 {
bus-width = <8>;
@@ -548,6 +534,7 @@
};
&ehci1 {
/*spacemit,udc-mode = <MV_USB_MODE_OTG>;*/
spacemit,reset-on-resume;
status = "okay";
};
@@ -570,9 +557,11 @@
};
&usb3hub {
usb-gpios = <&gpio 97 0>; /* gpio_97 for usb3 pwren */
hub-gpios = <&gpio 123 0>; /* usb3 hub en */
reset-gpios = <&gpio 124 0>; /* usb3 hub rst*/
hub-gpios = <
&gpio 123 0 /* usb3 hub en */
&gpio 124 0>; /* usb3 hub rst*/
vbus-gpios = <&gpio 97 0>; /* gpio_97 for usb3 hub output vbus */
vbus_delay_ms = <200>;
status = "okay";
};
@@ -580,7 +569,7 @@
status = "okay";
reset-on-resume;
dwc3@c0a00000 {
dr_mode = "otg";
dr_mode = "host";
phy_type = "utmi";
snps,hsphy_interface = "utmi";
snps,dis_enblslpm_quirk;
@@ -589,21 +578,48 @@
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,parkmode-disable-ss-quirk;
usb-role-switch;
role-switch-default-mode = "host";
};
};
&pcie1_rc {
&eth0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1_3>;
status = "okay";
};
pinctrl-0 = <&pinctrl_gmac0>;
emac,reset-gpio = <&gpio 110 0>;
emac,reset-active-low;
emac,reset-delays-us = <0 10000 100000>;
/* store forward mode */
tx-threshold = <1518>;
rx-threshold = <12>;
tx-ring-num = <1024>;
rx-ring-num = <1024>;
dma-burst-len = <5>;
ref-clock-from-phy;
clk-tuning-enable;
clk-tuning-by-delayline;
tx-phase = <60>;
rx-phase = <73>;
nvmem-cells = <&mac_address0>;
nvmem-cell-names = "mac-address";
phy-handle = <&rgmii0>;
&pcie2_rc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie2_4>;
status = "okay";
mdio-bus {
#address-cells = <0x1>;
#size-cells = <0x0>;
rgmii0: phy@0 {
compatible = "ethernet-phy-id001c.c916";
device_type = "ethernet-phy";
reg = <0x1>;
phy-mode = "rgmii";
};
};
};
&imggpu {
@@ -628,8 +644,58 @@
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};
&thermal {
sensor_range = <0x1 0x4>;
};
&thermal_zones {
top_thermal {
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&thermal 1>;
trips {
top_trip0: top-trip0 {
temperature = <40000>;
hysteresis = <5000>;
type = "passive";
};
top_trip1: top-trip1 {
temperature = <55000>;
hysteresis = <5000>;
type = "passive";
};
top_trip2: top-trip2 {
temperature = <70000>;
hysteresis = <5000>;
type = "passive";
};
top_trip3: top-trip3 {
temperature = <85000>;
hysteresis = <5000>;
type = "passive";
};
};
};
gpu_thermal {
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&thermal 2>;
/* Just a placeholder */
trips {
gpu_trip0: gpu-trip0 {
temperature = <40000>;
hysteresis = <5000>;
type = "passive";
};
};
};
};

5
arch/riscv/boot/dts/spacemit/k1-x_uav.dts
View File

@@ -781,7 +781,7 @@
SDHCI_QUIRK2_BROKEN_PHY_MODULE
)>;
spacemit,rx_dline_reg = <0x0>;
spacemit,tx_delaycode = <0xbf>;
spacemit,tx_delaycode = <0xa8 0x78>;
spacemit,rx_tuning_limit = <50>;
spacemit,sdh-freq = <375000000>;
status = "okay";
@@ -1106,9 +1106,6 @@
&rcpu {
/* pinctrl-names = "default"; */
/* pinctrl-0 = <&pinctrl_rcpu>; */
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

5
arch/riscv/boot/dts/spacemit/m1-x_milkv-jupiter.dts
View File

@@ -724,7 +724,7 @@
SDHCI_QUIRK2_BROKEN_PHY_MODULE
)>;
spacemit,rx_dline_reg = <0x0>;
spacemit,tx_delaycode = <0x30>;
spacemit,tx_delaycode = <0xa8 0x78>;
spacemit,rx_tuning_freq = <1600000>;
spacemit,rx_tuning_limit = <50>;
spacemit,sdh-freq = <375000000>;
@@ -1051,9 +1051,6 @@
&rcpu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rcpu>;
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
memory-region = <&rcpu_mem_0>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};

2
arch/riscv/configs/k1_debug_defconfig
View File

@@ -890,6 +890,7 @@ CONFIG_SPACEMIT_K1X_VIR_CAMERA=y
CONFIG_DRM_RADEON=m
CONFIG_DRM_RADEON_USERPTR=y
CONFIG_DRM_SPACEMIT=y
CONFIG_SPACEMIT_MIPI_PANEL=y
CONFIG_POWERVR_ROGUE=y
CONFIG_FB=y
CONFIG_BACKLIGHT_PWM=y
@@ -902,7 +903,6 @@ CONFIG_SND_SOC_SPACEMIT=y
CONFIG_SPACEMIT_CARD=y
CONFIG_SPACEMIT_PCM=y
CONFIG_SPACEMIT_I2S=y
CONFIG_SPACEMIT_HDMIAUDIO=y
CONFIG_SPACEMIT_DUMMYCODEC=y
CONFIG_SND_SOC_ES7210=y
CONFIG_SND_SOC_ES8156=y

3
arch/riscv/configs/k1_defconfig
View File

@@ -624,6 +624,7 @@ CONFIG_K1X_EMAC=y
# CONFIG_NET_VENDOR_WANGXUN is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
CONFIG_MOTORCOMM_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_CAN_FLEXCAN=y
CONFIG_PPP=y
@@ -915,8 +916,10 @@ CONFIG_SPACEMIT_HDMIAUDIO=y
CONFIG_SPACEMIT_DUMMYCODEC=y
CONFIG_SND_SOC_ES7210=y
CONFIG_SND_SOC_ES8156=y
CONFIG_SND_SOC_ES8316=y
CONFIG_SND_SOC_ES8323=y
CONFIG_SND_SOC_ES8326=y
CONFIG_SND_SOC_ES8375=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_HIDRAW=y
CONFIG_UHID=y

2
arch/riscv/configs/k1_rt_defconfig
View File

@@ -619,6 +619,8 @@ CONFIG_K1X_EMAC=y
# CONFIG_NET_VENDOR_WANGXUN is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
CONFIG_EC_MASTER=y
CONFIG_EC_K1X_EMAC=y
CONFIG_REALTEK_PHY=y
CONFIG_CAN_FLEXCAN=y
CONFIG_PPP=y

70
drivers/dma-buf/dma-heap.c
View File

@@ -43,24 +43,56 @@ struct dma_heap {
struct cdev heap_cdev;
};
struct dma_buf_node {
struct dma_buf *dmabuf;
struct list_head list;
};
static LIST_HEAD(g_fifo_list);
static LIST_HEAD(heap_list);
static DEFINE_MUTEX(heap_list_lock);
static dev_t dma_heap_devt;
static struct class *dma_heap_class;
static DEFINE_XARRAY_ALLOC(dma_heap_minors);
struct dma_buf *gdmabuf[10] = {NULL};
int gfd_dmabuf[10] = { -1 };
static int fifo_list_add(struct dma_buf *dmabuf)
{
struct dma_buf_node *node;
node = kzalloc(sizeof(*node), GFP_KERNEL);
if (!node) {
pr_err("%s %d: error! kzalloc node fail!\n", __func__, __LINE__);
return -ENOMEM;
}
node->dmabuf = dmabuf;
list_add_tail(&node->list, &g_fifo_list);
return 0;
}
static struct dma_buf *fifo_list_sub(void)
{
struct dma_buf *outdata;
struct dma_buf_node *node;
node = list_first_entry_or_null(&g_fifo_list, struct dma_buf_node, list);
if (node == NULL || node->dmabuf == NULL) {
pr_err("%s %d: error! without node or dmabuf in fifo list\n", __func__, __LINE__);
return NULL;
}
outdata = node->dmabuf;
list_del(&node->list);
kfree(node);
return outdata;
}
static int dma_heap_buffer_alloc(struct dma_heap *heap, size_t len,
unsigned int fd_flags,
unsigned int heap_flags)
{
static int push_count = 0;
static int pop_count = 0;
struct dma_buf *dmabuf;
int fd;
int fd_dma;
/*
* Allocations from all heaps have to begin
@@ -70,18 +102,16 @@ static int dma_heap_buffer_alloc(struct dma_heap *heap, size_t len,
if (!len)
return -EINVAL;
//if v4l2-app heap_flags, pop env
/* if v4l2-app heap_flags, sub dmabuf from fifo list */
if (heap_flags == 0xf0) {
dmabuf = gdmabuf[pop_count];
fd_dma = gfd_dmabuf[pop_count];
pop_count ++;
dmabuf = fifo_list_sub();
fd = dma_buf_fd(dmabuf, fd_flags);
if (fd < 0) {
printk("%s %d: error! heap_flags:%x, fd: %d\n",__func__,__LINE__, heap_flags, fd);
pr_err("%s %d: error! heap_flags:%x, fd: %d\n", __func__, __LINE__, heap_flags, fd);
dma_buf_put(dmabuf);
return fd;
}
printk("%s,%d: get fd%d, %p to v4l2-app success, heap_flags:%x\n", __func__, __LINE__, fd, dma_buf_get(fd_dma), heap_flags);
pr_info("%s,%d: get fd%d to v4l2-app success, heap_flags:%x\n", __func__, __LINE__, fd, heap_flags);
return fd;
}
@@ -95,14 +125,15 @@ static int dma_heap_buffer_alloc(struct dma_heap *heap, size_t len,
dma_buf_put(dmabuf);
/* just return, as put will call release and that will free */
}
//if cam-test heap_flags, push env
/* if cam-test heap_flags, add dmabuf to fifo list */
if (heap_flags == 0xff) {
gdmabuf[push_count] = dmabuf;
gfd_dmabuf[push_count] = fd;
dma_buf_get(fd); //for increase refcount
push_count++;
printk("%s,%d: alloc buf%p fd:%d, heap_flags:%x, cnt:%d, %d",
__func__,__LINE__, dmabuf, fd, heap_flags, push_count, pop_count);
if (fifo_list_add(dmabuf)) {
dma_buf_put(dmabuf);
return -ENOMEM;
} else {
dma_buf_get(fd); //for increase refcount
pr_info("%s,%d: alloc buf%p fd:%d, heap_flags:%x", __func__, __LINE__, dmabuf, fd, heap_flags);
}
}
return fd;
@@ -138,9 +169,8 @@ static long dma_heap_ioctl_allocate(struct file *file, void *data)
return -EINVAL;
if (heap_allocation->heap_flags & ~DMA_HEAP_VALID_HEAP_FLAGS) {
//TODO: flags define
if (heap_allocation->heap_flags == 0xff || heap_allocation->heap_flags == 0xf0)
printk("%s,%d: heap_flas: %llx\n", __func__, __LINE__, heap_allocation->heap_flags);
pr_info("%s,%d: heap_flas: %llx\n", __func__, __LINE__, heap_allocation->heap_flags);
else
return -EINVAL;
}

2
drivers/gpu/drm/nulldisp/drm_nulldisp_drv.c
View File

@@ -2733,7 +2733,7 @@ static void __exit nulldisp_exit(void)
platform_driver_unregister(&nulldisp_platform_driver);
}
module_init(nulldisp_init);
late_initcall(nulldisp_init);
module_exit(nulldisp_exit);
#if defined(LMA) && !defined(SUPPORT_EXTERNAL_PHYSHEAP_INTERFACE)

4
drivers/gpu/drm/nulldisp/drm_nulldisp_gem.c
View File

@@ -297,6 +297,10 @@ nulldisp_gem_prime_import_sg_table(struct drm_device *dev,
obj->resv = nulldisp_obj->resv;
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 9, 0))
obj->funcs = &nulldisp_gem_funcs;
#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(5, 9, 0) */
drm_gem_private_object_init(dev, obj, attach->dmabuf->size);
npages = obj->size >> PAGE_SHIFT;

9
drivers/gpu/drm/spacemit/dpu/dpu_saturn.c
View File

@@ -67,13 +67,13 @@ static const struct dpu_format_id primary_fmts[] = {
{ DRM_FORMAT_XRGB1555, 21 }, //RDMA_FMT_XRGB_1555
{ DRM_FORMAT_ARGB16161616F, 24 }, //RDMA_FMT_ARGB_16161616
{ DRM_FORMAT_ABGR16161616F, 25 }, //RDMA_FMT_ABGR_16161616
{ DRM_FORMAT_XYUV8888, 32 }, //RDMA_FMT_XYUV_444_P1_8, uv_swap has no corresponding fourcc format
{ DRM_FORMAT_Y410, 33 }, //RDMA_FMT_XYUV_444_P1_10, uv_swap has no corresponding fourcc format
{ DRM_FORMAT_YUYV, 34 }, //RDMA_FMT_VYUY_422_P1_8
{ DRM_FORMAT_YVYU, 34 }, //RDMA_FMT_VYUY_422_P1_8, uv_swap = 1
{ DRM_FORMAT_UYVY, 35 }, //RDMA_FMT_YVYU_422_P1_8
{ DRM_FORMAT_VYUY, 35 }, //RDMA_FMT_YVYU_422_P1_8, uv_swap = 1
*/
{ DRM_FORMAT_XYUV8888, 32, 32 }, //RDMA_FMT_XYUV_444_P1_8, uv_swap has no corresponding fourcc format
{ DRM_FORMAT_YUV420_8BIT, 37, 12 }, //DRM_FORMAT_YUV420_8BIT for AFBC
{ DRM_FORMAT_NV12, 37, 12 }, //RDMA_FMT_YUV_420_P2_8
/*
@@ -1143,15 +1143,14 @@ void spacemit_plane_update_hw_channel(struct drm_plane *plane)
void spacemit_plane_disable_hw_channel(struct drm_plane *plane, struct drm_plane_state *old_state)
{
struct spacemit_plane *p = to_spacemit_plane(plane);
u8 channel = crtc_to_dpu(old_state->crtc)->dev_id;
u8 channel = p->dev_id;
u32 base = CMP_BASE_ADDR(channel);
u32 rdma_id = to_spacemit_plane_state(old_state)->rdma_id;
struct spacemit_drm_private *priv = plane->dev->dev_private;
struct spacemit_hw_device *hwdev = priv->hwdev;
DRM_DEBUG("%s() layer_id = %u rdma_id:%d\n", __func__, p->hw_pid, rdma_id);
DRM_DEBUG("%s() channel %d layer_id = %u \n", __func__, p->dev_id, p->hw_pid);
trace_spacemit_plane_disable_hw_channel(p->hw_pid, rdma_id);
trace_spacemit_plane_disable_hw_channel(p->hw_pid);
switch (p->hw_pid) {
case 0:

9
drivers/gpu/drm/spacemit/dpu/dpu_trace.h
View File

@@ -182,18 +182,15 @@ DEFINE_EVENT(dpu_uint64_t_data_template, u64_data,
);
TRACE_EVENT(spacemit_plane_disable_hw_channel,
TP_PROTO(uint32_t layer_id, uint32_t rdma_id),
TP_ARGS(layer_id, rdma_id),
TP_PROTO(uint32_t layer_id),
TP_ARGS(layer_id),
TP_STRUCT__entry(
__field(uint32_t, layer_id)
__field(uint32_t, rdma_id)
),
TP_fast_assign(
__entry->layer_id = layer_id;
__entry->rdma_id = rdma_id;
),
TP_printk("layer_id:%d rdma_id:%d",
__entry->layer_id, __entry->rdma_id)
TP_printk("layer_id=%d", __entry->layer_id)
);
TRACE_EVENT(dpu_mclk_scl,

2
drivers/gpu/drm/spacemit/dpu/saturn_fbcmem.c
View File

@@ -82,7 +82,7 @@ int get_raw_data_plane_rdma_mem_size(u32 drm_4cc_fmt, bool rot_90_or_270, u32 pl
DRM_ERROR("FBC_MEM: not support format %d\n", drm_4cc_fmt);
return -1;
}
if (info->num_planes == 1 && info->is_yuv == false) {
if (info->num_planes == 1) {
data_plane_mem_size[0] = plane_crop_width * info->cpp[0];
} else if (info->num_planes >= 2 && info->is_yuv) {
data_plane_mem_size[0] = plane_crop_width * info->cpp[0];

7
drivers/gpu/drm/spacemit/spacemit_dpu.c
View File

@@ -330,10 +330,15 @@ static void spacemit_crtc_atomic_disable(struct drm_crtc *crtc,
{
struct spacemit_dpu *dpu = crtc_to_dpu(crtc);
struct drm_device *drm = dpu->crtc.dev;
struct drm_crtc_state *old_crtc_state;
DRM_INFO("%s(power off)\n", __func__);
trace_spacemit_crtc_atomic_disable(dpu->dev_id);
/* always disable planes on the CRTC that is being turned off */
old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc);
drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false);
if (!IS_ERR_OR_NULL(dpu->enable_gpio)) {
gpiod_direction_output(dpu->enable_gpio, 0);
}
@@ -672,6 +677,8 @@ static int spacemit_dpu_init(struct spacemit_dpu *dpu)
{
trace_spacemit_dpu_init(dpu->dev_id);
DRM_DEBUG("%s() type %d\n", __func__, dpu->type);
if (dpu->core && dpu->core->init)
dpu->core->init(dpu);

1
drivers/gpu/drm/spacemit/spacemit_dpu.h
View File

@@ -208,6 +208,7 @@ struct spacemit_plane {
struct drm_property *solid_color_property;
struct drm_property *hdr_coef_property;
struct drm_property *scale_coef_property;
int dev_id;
u32 hw_pid;
};

19
drivers/gpu/drm/spacemit/spacemit_planes.c
View File

@@ -152,6 +152,8 @@ static int spacemit_plane_atomic_check(struct drm_plane *plane,
dpu = crtc_to_dpu(state->crtc);
trace_spacemit_plane_atomic_check(dpu->dev_id);
DRM_DEBUG("%s() type %d \n", __func__, dpu->type);
src_x = state->src_x >> 16;
src_y = state->src_y >> 16;
src_w = state->src_w >> 16;
@@ -264,7 +266,7 @@ static void spacemit_plane_atomic_update(struct drm_plane *plane,
u32 src_x, src_y, src_w, src_h;
u32 crtc_x, crtc_y, crtc_w, crtc_h;
DRM_DEBUG("%s()\n", __func__);
DRM_DEBUG("%s() type %d \n", __func__, dpu->type);
trace_spacemit_plane_atomic_update(dpu->dev_id);
mode = &dpu_crtc->mode;
@@ -374,9 +376,17 @@ static void spacemit_plane_atomic_update(struct drm_plane *plane,
static void spacemit_plane_atomic_disable(struct drm_plane *plane,
struct drm_atomic_state *state)
{
struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane);
struct drm_plane_state *old_state;
DRM_DEBUG("%s()\n", __func__);
if (state)
old_state = drm_atomic_get_old_plane_state(state, plane);
else
old_state = NULL;
if ((old_state != NULL) && (!old_state->crtc))
return;
spacemit_dmmu_unmap(plane);
spacemit_plane_disable_hw_channel(plane, old_state);
}
@@ -744,6 +754,8 @@ struct drm_plane *spacemit_plane_init(struct drm_device *drm,
u8 n_rdmas = hwdev->rdma_nums;
u32 plane_crtc_mask;
DRM_DEBUG("%s() type %d \n", __func__, dpu->type);
trace_spacemit_plane_init(dpu->dev_id);
if (n_fbcmems * 2 != n_rdmas) {
DRM_ERROR("Unmatched rdma and fbcmem numbers, \
@@ -793,10 +805,13 @@ struct drm_plane *spacemit_plane_init(struct drm_device *drm,
spacemit_plane_create_properties(p, i);
p->dev_id = dpu->dev_id;
p->hwdev = hwdev;
p->hw_pid = n_planes - i - 1;
if (i == 0)
primary = &p->plane;
DRM_DEBUG("%s() type %d i %d hw_pid %d dev_id %d \n", __func__, dpu->type, i, p->hw_pid, dpu->dev_id);
}
kfree(formats);

8
drivers/i2c/busses/i2c-k1x.c
View File

@@ -98,7 +98,7 @@ static void spacemit_i2c_controller_reset(struct spacemit_i2c_dev *spacemit_i2c)
static void spacemit_i2c_bus_reset(struct spacemit_i2c_dev *spacemit_i2c)
{
int clk_cnt = 0;
u32 bus_status;
u32 bus_status, val;
/* if bus is locked, reset unit. 0: locked */
bus_status = spacemit_i2c_read_reg(spacemit_i2c, REG_BMR);
@@ -119,7 +119,8 @@ static void spacemit_i2c_bus_reset(struct spacemit_i2c_dev *spacemit_i2c)
break;
/* if still locked, send one clk to slave to request release */
spacemit_i2c_write_reg(spacemit_i2c, REG_RST_CYC, 0x1);
val = spacemit_i2c_read_reg(spacemit_i2c, REG_RST_CYC);
spacemit_i2c_write_reg(spacemit_i2c, REG_RST_CYC, val | 0x1);
spacemit_i2c_write_reg(spacemit_i2c, REG_CR, CR_RSTREQ);
usleep_range(20, 30);
clk_cnt++;
@@ -1337,6 +1338,9 @@ xfer_retry:
spacemit_i2c_init_xfer_params(spacemit_i2c);
ret = spacemit_i2c_read_reg(spacemit_i2c, REG_RST_CYC);
spacemit_i2c_write_reg(spacemit_i2c, REG_RST_CYC, I2C_SDA_GLITCH_FIX_BYPASS | ret);
spacemit_i2c_mark_rw_flag(spacemit_i2c);
reinit_completion(&spacemit_i2c->complete);

2
drivers/i2c/busses/i2c-k1x.h
View File

@@ -185,6 +185,8 @@ enum spacemit_i2c_xfer_phase {
#define SPACEMIT_I2C_APB_CLOCK_26M (26000000)
#define SPACEMIT_I2C_APB_CLOCK_52M (52000000)
#define I2C_SDA_GLITCH_FIX_BYPASS BIT(7)
/* i2c-spacemit driver's main struct */
struct spacemit_i2c_dev {
struct device *dev;

30
drivers/media/platform/spacemit/camera/vi/subdev.c
View File

@@ -16,7 +16,11 @@
static int spm_subdev_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
{
struct spm_camera_subdev *sc_subdev = v4l2_subdev_to_sc_subdev(sd);
cam_dbg("%s(%s) enter.", __func__, sc_subdev->name);
cam_dbg("%s(%s) enter. cnt:%d", __func__, sc_subdev->name, atomic_read(&sc_subdev->ref_cnt));
if (atomic_inc_return(&sc_subdev->ref_cnt) != 1)
cam_warn("subdev(%s) was already openned.", sc_subdev->name);
return 0;
}
@@ -28,18 +32,22 @@ static int spm_subdev_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
struct spm_camera_subdev *sc_subdev = v4l2_subdev_to_sc_subdev(sd);
struct media_pipeline *pipe = media_entity_pipeline(me);
cam_dbg("%s(%s) enter.", __func__, sc_subdev->name);
mutex_lock(&mdev->graph_mutex);
if (pipe) {
sc_pipeline = media_pipeline_to_sc_pipeline(pipe);
if (sc_pipeline->state >= PIPELINE_ST_STARTED) {
__spm_mlink_stop_pipeline(me);
}
while (sc_pipeline->state >= PIPELINE_ST_GET) {
__spm_mlink_put_pipeline(me, 1);
cam_dbg("%s(%s) enter. cnt:%d", __func__, sc_subdev->name, atomic_read(&sc_subdev->ref_cnt));
if (atomic_dec_and_test(&sc_subdev->ref_cnt)) {
mutex_lock(&mdev->graph_mutex);
if (pipe) {
sc_pipeline = media_pipeline_to_sc_pipeline(pipe);
if (sc_pipeline->state >= PIPELINE_ST_STARTED) {
__spm_mlink_stop_pipeline(me);
}
while (sc_pipeline->state >= PIPELINE_ST_GET) {
__spm_mlink_put_pipeline(me, 1);
}
}
mutex_unlock(&mdev->graph_mutex);
}
mutex_unlock(&mdev->graph_mutex);
return 0;
}

1
drivers/media/platform/spacemit/camera/vi/subdev.h
View File

@@ -36,6 +36,7 @@ struct spm_camera_subdev {
struct notifier_block vnode_nb;
uint32_t pads_stream_enable;
int is_resetting;
atomic_t ref_cnt;
long (*ioctl)(struct v4l2_subdev *sd, unsigned int cmd, void *arg);
void (*release)(struct spm_camera_subdev *sc_subdev);
void (*notify)(struct spm_camera_subdev *sc_subdev, unsigned int notification,

621
drivers/media/platform/spacemit/virtual_camera/svivi.c
View File

File diff suppressed because it is too large Load Diff

41
drivers/media/platform/spacemit/virtual_camera/vcam_dbg.c
View File

@@ -2,20 +2,18 @@
/*
* vcam_dbg.c - vcamera debug utility
*
* Copyright(C) 2023 SPACEMIT Micro Limited
* Copyright(C) 2025 SPACEMIT Micro Limited
*/
#define DEBUG /* for pr_debug() */
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ioctl.h>
#include "vcam_dbg.h"
static uint debug_mdl = 0x0; /* disable all modules at default */
//static uint debug_mdl = 0x1FF; /* enable all modules for debug */
static uint debug_mdl = 0x0;
static uint debug_loop_prink = 0x0;
void vcam_printk(int module_tag, const char *vcam_level, const char *kern_level,
void vcam_printk(const char *vcam_level, const char *kern_level,
const char *func, int line, const char *format, ...)
{
struct va_format vaf;
@@ -32,29 +30,12 @@ void vcam_printk(int module_tag, const char *vcam_level, const char *kern_level,
EXPORT_SYMBOL(vcam_printk);
void vcam_printk_ratelimited(int module_tag, const char *vcam_level,
const char *kern_level, const char *format, ...)
void vcam_debug(const char *vcam_level, const char *func, int line, const char *format, ...)
{
struct va_format vaf;
va_list args;
va_start(args, format);
vaf.fmt = format;
vaf.va = &args;
printk_ratelimited("%s" "%s: %pV\n", kern_level, vcam_level, &vaf);
va_end(args);
}
EXPORT_SYMBOL(vcam_printk_ratelimited);
void vcam_debug(int module_tag, const char *vcam_level, const char *func, int line, const char *format, ...)
{
struct va_format vaf;
va_list args;
if (!debug_mdl)
if (debug_loop_prink == 0)
return;
va_start(args, format);
@@ -68,13 +49,5 @@ void vcam_debug(int module_tag, const char *vcam_level, const char *func, int li
EXPORT_SYMBOL(vcam_debug);
// MODULE_PARM_DESC(debug_mdl, "Enable debug output, where each bit enables a module.\n"
// "\t\tBit 0 (0x01) will enable VI messages\n"
// "\t\tBit 1 (0x02) will enable ISP messages\n"
// "\t\tBit 2 (0x04) will enable CPP messages\n"
// "\t\tBit 3 (0x08) will enable VBE messages\n"
// "\t\tBit 4 (0x10) will enable SENSOR messages\n"
// "\t\tBit 5 (0x20) will enable IRCUT messages\n"
// "\t\tBit 8 (0x100) will enable COMMON messages");
module_param(debug_mdl, uint, 0644);
module_param(debug_loop_prink, uint, 0644);

53
drivers/media/platform/spacemit/virtual_camera/vcam_dbg.h
View File

@@ -2,38 +2,19 @@
/*
* vcam_dbg.h - vcamera debug utility
*
* Copyright(C) 2023 SPACEMIT Micro Limited
* Copyright(C) 2025 SPACEMIT Micro Limited
*/
#ifndef __VCAM_DBG_H__
#define __VCAM_DBG_H__
#include <linux/printk.h>
// enum dbg_module_tag {
// VCAM_MDL_VI = 0,
// VCAM_MDL_ISP = 1,
// VCAM_MDL_CPP = 2,
// VCAM_MDL_VBE = 3,
// VCAM_MDL_SNR = 4,
// VCAM_MDL_IRCUT = 5,
// VCAM_MDL_COMMON = 8,
// };
#ifndef VCAM_MODULE_TAG
// #define VCAM_MODULE_TAG VCAM_MDL_COMMON
#define VCAM_MODULE_TAG 8
#endif
__printf(6, 7)
void vcam_printk(int module_tag, const char *vcam_level, const char *kern_level,
__printf(5, 6)
void vcam_printk(const char *vcam_level, const char *kern_level,
const char *func, int line, const char *format, ...);
__printf(4, 5)
void vcam_printk_ratelimited(int module_tag, const char *vcam_level,
const char *kern_level, const char *format, ...);
__printf(5, 6)
void vcam_debug(int module_tag, const char *vcam_level, const char *func, int line, const char *format, ...);
void vcam_debug(const char *vcam_level, const char *func, int line, const char *format, ...);
/**
* vcamera error output.
@@ -41,25 +22,16 @@ void vcam_debug(int module_tag, const char *vcam_level, const char *func, int li
* @format: printf() like format string.
*/
#define vcam_err(format, ...) \
vcam_printk(VCAM_MODULE_TAG, "vcam_err", KERN_ERR, \
vcam_printk("vcam_err", KERN_ERR, \
__func__, __LINE__, format, ##__VA_ARGS__)
/**
* vcamera error output.
*
* @format: printf() like format string.
*/
#define vcam_err_ratelimited(format, ...) \
vcam_printk_ratelimited(VCAM_MODULE_TAG, "vcam_err", KERN_ERR, \
format, ##__VA_ARGS__)
/**
* vcamera warning output.
*
* @format: printf() like format string.
*/
#define vcam_warn(format, ...) \
vcam_printk(VCAM_MODULE_TAG, "vcam_wrn", KERN_WARNING, \
vcam_printk("vcam_wrn", KERN_WARNING, \
__func__, __LINE__, format, ##__VA_ARGS__)
/**
@@ -68,7 +40,7 @@ void vcam_debug(int module_tag, const char *vcam_level, const char *func, int li
* @format: printf() like format string.
*/
#define vcam_not(format, ...) \
vcam_printk(VCAM_MODULE_TAG, "vcam_not", KERN_NOTICE, \
vcam_printk("vcam_not", KERN_NOTICE, \
__func__, __LINE__, format, ##__VA_ARGS__)
/**
@@ -77,7 +49,7 @@ void vcam_debug(int module_tag, const char *vcam_level, const char *func, int li
* @format: printf() like format string.
*/
#define vcam_info(format, ...) \
vcam_printk(VCAM_MODULE_TAG, "vcam_inf", KERN_INFO, \
vcam_printk("vcam_inf", KERN_INFO, \
__func__, __LINE__, format, ##__VA_ARGS__)
/**
@@ -86,13 +58,6 @@ void vcam_debug(int module_tag, const char *vcam_level, const char *func, int li
* @format: printf() like format string.
*/
#define vcam_dbg(format, ...) \
vcam_debug(VCAM_MODULE_TAG, "vcam_dbg", __func__, __LINE__, format, ##__VA_ARGS__)
vcam_debug("vcam_dbg", __func__, __LINE__, format, ##__VA_ARGS__)
#define VCAM_DBG_TRACE
#ifdef VCAM_DBG_TRACE
#define vcam_trace(f, args...) trace_printk(f, ##args)
#else
#define vcam_trace(f, args...) no_printk(f, ##args)
#endif
#endif /* ifndef __VCAM_DBG_H__ */

162
drivers/mmc/host/sdhci-of-k1x.c
View File

@@ -637,6 +637,20 @@ static void spacemit_enable_sdio_irq(struct mmc_host *mmc, int enable)
spin_unlock_irqrestore(&host->lock, flags);
}
static void spacemit_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
struct k1x_sdhci_platdata *pdata = mmc->parent->platform_data;
if (!(mmc->caps2 & MMC_CAP2_NO_SDIO)) {
while (atomic_inc_return(&pdata->ref_count) > 1) {
atomic_dec(&pdata->ref_count);
wait_event(pdata->wait_queue, atomic_read(&pdata->ref_count) == 0);
}
}
sdhci_request(mmc, mrq);
}
static void spacemit_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -1402,6 +1416,18 @@ static void spacemit_sdhci_dump_vendor_regs(struct sdhci_host *host)
#endif
}
static void spacemit_sdhci_request_done(struct sdhci_host *host,
struct mmc_request *mrq)
{
struct mmc_host *mmc = host->mmc;
struct k1x_sdhci_platdata *pdata = mmc->parent->platform_data;
mmc_request_done(host->mmc, mrq);
if (!(host->mmc->caps2 & MMC_CAP2_NO_SDIO))
atomic_dec(&pdata->ref_count);
}
static const struct sdhci_ops spacemit_sdhci_ops = {
.set_clock = spacemit_sdhci_set_clock,
.platform_send_init_74_clocks = spacemit_sdhci_gen_init_74_clocks,
@@ -1415,11 +1441,115 @@ static const struct sdhci_ops spacemit_sdhci_ops = {
.irq = spacemit_handle_interrupt,
.set_power = sdhci_set_power_and_bus_voltage,
.dump_vendor_regs = spacemit_sdhci_dump_vendor_regs,
.request_done = spacemit_sdhci_request_done,
#ifdef CONFIG_SOC_SPACEMIT_K1X
.set_encrypt_feature = spacemit_sdhci_set_encrypt,
#endif
};
#ifdef CONFIG_CPU_FREQ
static unsigned long get_voltage_from_freq(unsigned long freq)
{
struct device *dev = get_cpu_device(0);
unsigned long freq_hz = freq * 1000;
unsigned long voltage;
struct dev_pm_opp *opp;
opp = dev_pm_opp_find_freq_ceil(dev, &freq_hz);
if (IS_ERR(opp)) {
dev_err_ratelimited(dev, "Failed to find OPP for frequency %lu kHZ: %ld\n",
freq, PTR_ERR(opp));
return 0;
}
voltage = dev_pm_opp_get_voltage(opp) / 1000; /* mV */
dev_pm_opp_put(opp);
return voltage;
}
#define SPLIT_VOLTAGE 950 /* mV */
static int spacemit_cpufreq_transition(struct notifier_block *nb,
unsigned long val, void *data)
{
struct sdhci_host *host = container_of(nb, struct sdhci_host, freq_transition);
struct mmc_host *mmc = host->mmc;
struct k1x_sdhci_platdata *pdata = mmc->parent->platform_data;
struct cpufreq_freqs *freq = data;
unsigned long voltage_old, voltage_new;
if ((pdata->tx_delaycode_array[0] == pdata->tx_delaycode_array[1])
|| (pdata->tx_delaycode_cnt == 1))
return 0;
if (val == CPUFREQ_PRECHANGE) {
pr_debug("%s: cpu freq pre changed %u to %u kHZ\n",
mmc_hostname(mmc), freq->old, freq->new);
voltage_old = get_voltage_from_freq(freq->old);
voltage_new = get_voltage_from_freq(freq->new);
if ((voltage_old == 0) || (voltage_new == 0))
return 0;
if ((voltage_old > SPLIT_VOLTAGE) && (voltage_new <= SPLIT_VOLTAGE)) {
pdata->tx_need_update = true;
pdata->tx_delaycode = pdata->tx_delaycode_array[1];
} else if ((voltage_old <= SPLIT_VOLTAGE) && (voltage_new > SPLIT_VOLTAGE)) {
pdata->tx_need_update = true;
pdata->tx_delaycode = pdata->tx_delaycode_array[0];
}
if (pdata->tx_need_update) {
while (atomic_inc_return(&pdata->ref_count) > 1) {
atomic_dec(&pdata->ref_count);
usleep_range(5, 10);
}
}
}
if (val == CPUFREQ_POSTCHANGE) {
pr_debug("%s: cpu freq is changed to %u kHZ\n",
mmc_hostname(mmc), freq->new);
if (pdata->tx_need_update) {
spacemit_sw_tx_set_delaycode(host, pdata->tx_delaycode);
pr_info("%s: update tx delaycode: %d\n",
mmc_hostname(mmc), pdata->tx_delaycode);
atomic_dec(&pdata->ref_count);
wake_up(&pdata->wait_queue);
pdata->tx_need_update = false;
}
}
return 0;
}
static inline int spacemit_cpufreq_register(struct sdhci_host *host)
{
if (host->mmc->caps2 & MMC_CAP2_NO_SDIO)
return 0;
host->freq_transition.notifier_call = spacemit_cpufreq_transition;
return cpufreq_register_notifier(&host->freq_transition,
CPUFREQ_TRANSITION_NOTIFIER);
}
static inline void spacemit_cpufreq_unregister(struct sdhci_host *host)
{
cpufreq_unregister_notifier(&host->freq_transition,
CPUFREQ_TRANSITION_NOTIFIER);
}
#else
static inline int spacemit_cpufreq_register(struct sdhci_host *host)
{
return 0;
}
static inline void spacemit_cpufreq_unregister(struct sdhci_host *host)
{
}
#endif
static struct sdhci_pltfm_data sdhci_k1x_pdata = {
.ops = &spacemit_sdhci_ops,
.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
@@ -1452,6 +1582,7 @@ static void spacemit_get_of_property(struct sdhci_host *host,
{
struct device_node *np = dev->of_node;
u32 property;
int ret;
/* sdh io clk */
if (!of_property_read_u32(np, "spacemit,sdh-freq", &property))
@@ -1508,10 +1639,16 @@ static void spacemit_get_of_property(struct sdhci_host *host,
pdata->tx_dline_reg = (u8)property;
else
pdata->tx_dline_reg = TX_TUNING_DLINE_REG;
if (!of_property_read_u32(np, "spacemit,tx_delaycode", &property))
pdata->tx_delaycode = (u8)property;
else
pdata->tx_delaycode = TX_TUNING_DELAYCODE;
ret = of_property_read_variable_u32_array(np, "spacemit,tx_delaycode",
pdata->tx_delaycode_array, 1, 2);
if (ret > 0) {
pdata->tx_delaycode_cnt = (u8)ret;
} else {
pdata->tx_delaycode_array[0] = TX_TUNING_DELAYCODE;
pdata->tx_delaycode_cnt = 1;
}
pdata->tx_delaycode = pdata->tx_delaycode_array[0];
/* phy driver select */
if (!of_property_read_u32(np, "spacemit,phy_driver_sel", &property))
@@ -1692,6 +1829,7 @@ static int spacemit_sdhci_probe(struct platform_device *pdev)
host->mmc_host_ops.card_busy = spacemit_sdhci_card_busy;
host->mmc_host_ops.init_card = spacemit_init_card_quriks;
host->mmc_host_ops.enable_sdio_irq = spacemit_enable_sdio_irq;
host->mmc_host_ops.request = spacemit_sdhci_request;
if (!(host->mmc->caps2 & MMC_CAP2_NO_SDIO)) {
/* skip auto rescan */
@@ -1716,13 +1854,22 @@ static int spacemit_sdhci_probe(struct platform_device *pdev)
ret = clk_set_rate(spacemit->clk_io, pdata->host_freq);
if (ret) {
dev_err(dev, "failed to set io clock freq\n");
goto err_add_host;
goto err_host_freq;
}
} else {
dev_err(dev, "failed to get io clock freq\n");
goto err_add_host;
goto err_host_freq;
}
ret = spacemit_cpufreq_register(host);
if (ret) {
dev_err(&pdev->dev, "failed to register cpufreq\n");
goto err_host_freq;
}
init_waitqueue_head(&pdata->wait_queue);
atomic_set(&pdata->ref_count, 0);
ret = sdhci_add_host(host);
if (ret) {
dev_err(&pdev->dev, "failed to add spacemit sdhc.\n");
@@ -1754,6 +1901,8 @@ static int spacemit_sdhci_probe(struct platform_device *pdev)
return 0;
err_add_host:
spacemit_cpufreq_unregister(host);
err_host_freq:
pm_runtime_disable(&pdev->dev);
pm_runtime_put_noidle(&pdev->dev);
err_of_parse:
@@ -1778,6 +1927,7 @@ static void spacemit_sdhci_remove(struct platform_device *pdev)
pm_runtime_get_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
pm_runtime_put_noidle(&pdev->dev);
spacemit_cpufreq_unregister(host);
sdhci_remove_host(host, 1);
reset_control_assert(spacemit->reset);

4
drivers/mmc/host/sdhci.h
View File

@@ -635,6 +635,10 @@ struct sdhci_host {
u64 data_timeout;
#ifdef CONFIG_CPU_FREQ
struct notifier_block freq_transition;
#endif
unsigned long private[] ____cacheline_aligned;
};

54
drivers/net/can/flexcan/flexcan-core.c
View File

@@ -381,7 +381,15 @@ static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
};
#ifdef CONFIG_SOC_SPACEMIT_K1X
static const struct flexcan_devtype_data spacemit_k1x_devtype_data = {
static const struct flexcan_devtype_data spacemit_k1x_devtype_data_can20 = {
.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
FLEXCAN_QUIRK_SUPPORT_RX_FIFO |
FLEXCAN_QUIRK_SUPPORT_ECC,
};
static const struct flexcan_devtype_data spacemit_k1x_devtype_data_fd = {
.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_FD |
@@ -1794,7 +1802,7 @@ static int flexcan_open(struct net_device *dev)
can_rx_offload_enable(&priv->offload);
if (dev->irq > 0) {
err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED | IRQF_NO_THREAD, dev->name, dev);
err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
if (err)
goto out_can_rx_offload_disable;
@@ -2087,8 +2095,9 @@ static const struct of_device_id flexcan_of_match[] = {
{ .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
{ .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
#ifdef CONFIG_SOC_SPACEMIT_K1X
{ .compatible = "spacemit,k1x-flexcan", .data = &spacemit_k1x_devtype_data, },
{ .compatible = "spacemit,k1x-r-flexcan", .data = &spacemit_k1x_devtype_data, },
{ .compatible = "spacemit,k1x-flexcan", .data = &spacemit_k1x_devtype_data_fd, },
{ .compatible = "spacemit,k1x-r-flexcan", .data = &spacemit_k1x_devtype_data_fd, },
{ .compatible = "spacemit,k1x-flexcan-can2.0", .data = &spacemit_k1x_devtype_data_can20, },
#endif
{ /* sentinel */ },
};
@@ -2106,6 +2115,7 @@ MODULE_DEVICE_TABLE(platform, flexcan_id_table);
static void flexcan_box_callback(struct mbox_client *cl, void *data)
{
char c = 'c';
struct net_device *dev;
struct flexcan_mox *mb = container_of(cl, struct flexcan_mox, client);
@@ -2113,35 +2123,7 @@ static void flexcan_box_callback(struct mbox_client *cl, void *data)
flexcan_irq(0, dev);
complete(&mb->mb_comp);
}
static int __process_theread(void *arg)
{
int ret;
char c = 'c';
struct mbox_client *cl = arg;
struct flexcan_mox *mb = container_of(cl, struct flexcan_mox, client);
struct sched_param param = {.sched_priority = 0 };
mb->kthread_running = true;
ret = sched_setscheduler(current, SCHED_FIFO, &param);
set_freezable();
do {
try_to_freeze();
ret = wait_for_completion_timeout(&mb->mb_comp, 10);
/* send message to the other hand */
if (ret)
mbox_send_message(mb->chan, &c);
} while (!kthread_should_stop());
mb->kthread_running = false;
return 0;
mbox_send_message(mb->chan, &c);
}
#define CAN_MBOX0_ID 0
@@ -2151,7 +2133,7 @@ static struct flexcan_mox flexcan_mbox[] = {
.box_id = CAN_MBOX0_ID,
.client = {
.rx_callback = flexcan_box_callback,
.tx_block = true,
.tx_block = false,
},
},
};
@@ -2290,10 +2272,6 @@ static int flexcan_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "Failed to request mbox channel\n");
return -EINVAL;
}
init_completion(&priv->fmx->mb_comp);
priv->fmx->mb_thread = kthread_run(__process_theread, (void *)&flexcan_mbox->client,
priv->fmx->name);
}
if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||

13
drivers/net/ethercat/master/module.c
View File

@@ -745,3 +745,16 @@ module_platform_driver(ec_master_driver);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Ethercat master driver");
/****************************************************************************/
/** \cond */
EXPORT_SYMBOL(ecdev_offer);
EXPORT_SYMBOL(ecrt_request_master);
EXPORT_SYMBOL(ecrt_release_master);
EXPORT_SYMBOL(ecrt_version_magic);
/** \endcond */
/****************************************************************************/

43
drivers/net/ethernet/spacemit/k1x-emac.c
View File

@@ -37,6 +37,7 @@
#include <linux/udp.h>
#include <linux/workqueue.h>
#include <linux/reset.h>
#include <linux/pm_wakeirq.h>
#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
@@ -2386,6 +2387,37 @@ static void emac_get_strings(struct net_device *dev, u32 stringset, u8 *data)
}
}
/* Currently only support WOL through Magic packet. */
static void emac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
wol->supported = 0;
wol->wolopts = 0;
if (dev->phydev)
phy_ethtool_get_wol(dev->phydev, wol);
return ;
}
static int emac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
struct emac_priv *priv = netdev_priv(dev);
struct device *kdev = &priv->pdev->dev;
int ret;
if (!device_can_wakeup(kdev))
return -EOPNOTSUPP;
/* Try Wake-on-LAN from the PHY first */
if (dev->phydev) {
ret = phy_ethtool_set_wol(dev->phydev, wol);
if (!ret)
device_set_wakeup_enable(kdev, !!wol->wolopts);
}
return ret;
}
static int emac_get_sset_count(struct net_device *dev, int sset)
{
switch (sset) {
@@ -2543,6 +2575,8 @@ static const struct ethtool_ops emac_ethtool_ops = {
.nway_reset = phy_ethtool_nway_reset,
.get_link = ethtool_op_get_link,
.get_strings = emac_get_strings,
.get_wol = emac_get_wol,
.set_wol = emac_set_wol,
.get_sset_count = emac_get_sset_count,
.get_ethtool_stats = emac_get_ethtool_stats,
.get_regs = emac_ethtool_get_regs,
@@ -2593,6 +2627,10 @@ static int emac_config_dt(struct platform_device *pdev, struct emac_priv *priv)
return -ENXIO;
}
priv->irq_wakeup = irq_of_parse_and_map(np, 1);
if (!priv->irq_wakeup)
dev_dbg(&pdev->dev, "has no wake_up irq\n");
if (of_property_read_u32(np, "ctrl-reg", &ctrl_reg)) {
dev_err(&pdev->dev, "cannot find ctrl register in device tree\n");
return -EINVAL;
@@ -2839,6 +2877,11 @@ static int emac_probe(struct platform_device *pdev)
netif_napi_add(ndev, &priv->napi, emac_rx_poll);
if (priv->irq_wakeup) {
dev_pm_set_dedicated_wake_irq_spacemit(&pdev->dev, priv->irq_wakeup, IRQ_TYPE_EDGE_FALLING);
device_init_wakeup(&pdev->dev, true);
}
return 0;
err_mdio_deinit:
emac_mdio_deinit(priv);

1
drivers/net/ethernet/spacemit/k1x-emac.h
View File

@@ -673,6 +673,7 @@ struct emac_priv {
void __iomem *iobase;
u32 apmu_base;
int irq;
int irq_wakeup;
int link;
int duplex;
int speed;

74
drivers/net/phy/realtek.c
View File

@@ -10,6 +10,7 @@
#include <linux/bitops.h>
#include <linux/of.h>
#include <linux/phy.h>
#include <linux/netdevice.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/clk.h>
@@ -44,6 +45,24 @@
#define RTL8211F_TX_DELAY BIT(8)
#define RTL8211F_RX_DELAY BIT(3)
/* RTL8211F WOL interrupt configuration */
#define RTL8211F_INTBCR_PAGE 0xd40
#define RTL8211F_INTBCR 0x16
#define RTL8211F_INTBCR_INTB_PMEB BIT(5)
/* RTL8211F WOL settings */
#define RTL8211F_WOL_SETTINGS_PAGE 0xd8a
#define RTL8211F_WOL_SETTINGS_EVENTS 16
#define RTL8211F_WOL_EVENT_MAGIC BIT(12)
#define RTL8211F_WOL_SETTINGS_STATUS 17
#define RTL8211F_WOL_STATUS_RESET (BIT(15) | 0x1fff)
/* RTL8211F Unique phyiscal and multicast address (WOL) */
#define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c
#define RTL8211F_PHYSICAL_ADDR_WORD0 16
#define RTL8211F_PHYSICAL_ADDR_WORD1 17
#define RTL8211F_PHYSICAL_ADDR_WORD2 18
#define RTL8211F_ALDPS_PLL_OFF BIT(1)
#define RTL8211F_ALDPS_ENABLE BIT(2)
#define RTL8211F_ALDPS_XTAL_OFF BIT(12)
@@ -324,6 +343,53 @@ static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
return IRQ_HANDLED;
}
static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol)
{
wol->supported = WAKE_MAGIC;
if (phy_read_paged(dev, RTL8211F_WOL_SETTINGS_PAGE, RTL8211F_WOL_SETTINGS_EVENTS)
& RTL8211F_WOL_EVENT_MAGIC)
wol->wolopts = WAKE_MAGIC;
}
static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol)
{
const u8 *mac_addr = dev->attached_dev->dev_addr;
int oldpage;
oldpage = phy_save_page(dev);
if (oldpage < 0)
goto err;
if (wol->wolopts & WAKE_MAGIC) {
/* Store the device address for the magic packet */
rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE);
__phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0]));
__phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2]));
__phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4]));
/* Enable magic packet matching and reset WOL status */
rtl821x_write_page(dev, RTL8211F_WOL_SETTINGS_PAGE);
__phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC);
__phy_write(dev, RTL8211F_WOL_SETTINGS_STATUS, RTL8211F_WOL_STATUS_RESET);
/* Enable the WOL interrupt */
rtl821x_write_page(dev, RTL8211F_INTBCR_PAGE);
__phy_set_bits(dev, RTL8211F_INTBCR, RTL8211F_INTBCR_INTB_PMEB);
} else {
/* Disable the WOL interrupt */
rtl821x_write_page(dev, RTL8211F_INTBCR_PAGE);
__phy_clear_bits(dev, RTL8211F_INTBCR, RTL8211F_INTBCR_INTB_PMEB);
/* Disable magic packet matching and reset WOL status */
rtl821x_write_page(dev, RTL8211F_WOL_SETTINGS_PAGE);
__phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0);
__phy_write(dev, RTL8211F_WOL_SETTINGS_STATUS, RTL8211F_WOL_STATUS_RESET);
}
err:
return phy_restore_page(dev, oldpage, 0);
}
static int rtl8211_config_aneg(struct phy_device *phydev)
{
int ret;
@@ -513,6 +579,9 @@ static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index,
{
int val;
if (phydev->state == PHY_HALTED)
return 0;
val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR);
if (val < 0)
return val;
@@ -544,6 +613,9 @@ static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index,
u16 reg = 0;
int ret;
if (phydev->state == PHY_HALTED)
return 0;
if (index >= RTL8211F_LED_COUNT)
return -EINVAL;
@@ -1072,6 +1144,8 @@ static struct phy_driver realtek_drvs[] = {
.read_status = rtlgen_read_status,
.config_intr = &rtl8211f_config_intr,
.handle_interrupt = rtl8211f_handle_interrupt,
.set_wol = rtl8211f_set_wol,
.get_wol = rtl8211f_get_wol,
.suspend = rtl821x_suspend,
.resume = rtl821x_resume,
.read_page = rtl821x_read_page,

2
drivers/net/wireless/aic8800/aic8800_bsp/aic_bsp_8800d80.c
View File

@@ -557,7 +557,7 @@ int aicbsp_8800d80_fw_init(struct priv_dev *aicdev)
const u32 mem_addr = 0x40500000;
struct dbg_mem_read_cfm rd_mem_addr_cfm;
#ifdef AICWF_SDIO_SUPPORT
#if 0
int ret = 0;
if (rwnx_send_dbg_mem_write_req(aicdev, 0x40500058, 0x40))
return -1;

5
drivers/net/wireless/aic8800/aic8800_bsp/aicsdio.c
View File

@@ -1518,12 +1518,13 @@ static int aicwf_sdio_func_init(struct priv_dev *aicdev)
sdio_release_host(aicdev->func[0]);
return ret;
}
#if 0
if (feature.sdio_clock > 0) {
host->ios.clock = feature.sdio_clock;
host->ops->set_ios(host, &host->ios);
bsp_dbg("Set SDIO Clock %d MHz\n", host->ios.clock/1000000);
}
#endif
sdio_release_host(aicdev->func[0]);
if (aicbsp_info.chipinfo->chipid == PRODUCT_ID_AIC8800DC) {
@@ -1621,7 +1622,7 @@ static int aicwf_sdiov3_func_init(struct priv_dev *aicdev)
}
#endif
msleep(1);
#if 1 // SDIO CLOCK SETTING
#if 0 // SDIO CLOCK SETTING
if ((feature.sdio_clock > 0) && (host->ios.timing != MMC_TIMING_UHS_DDR50)) {
host->ios.clock = feature.sdio_clock;
host->ops->set_ios(host, &host->ios);

7
drivers/net/wireless/aic8800/aic8800_fdrv/aicwf_sdio.c
View File

@@ -1654,12 +1654,13 @@ int aicwf_sdio_func_init(struct aic_sdio_dev *sdiodev)
sdio_err("enable func fail %d.\n", ret);
return ret;
}
#if 0
if (feature.sdio_clock > 0) {
host->ios.clock = feature.sdio_clock;
host->ops->set_ios(host, &host->ios);
sdio_dbg("Set SDIO Clock %d MHz\n", host->ios.clock/1000000);
}
#endif
sdio_release_host(sdiodev->func);
if (aicwf_chipid == PRODUCT_ID_AIC8800D || aicwf_chipid == PRODUCT_ID_AIC8800DC ||
@@ -1766,13 +1767,13 @@ int aicwf_sdiov3_func_init(struct aic_sdio_dev *sdiodev)
sdio_err("enable func fail %d.\n", ret);
return ret;
}
#if 0
if ((feature.sdio_clock > 0) && (host->ios.timing != MMC_TIMING_UHS_DDR50)) {
host->ios.clock = feature.sdio_clock;
host->ops->set_ios(host, &host->ios);
sdio_info("Set SDIO Clock %d MHz\n", host->ios.clock/1000000);
}
#endif
sdio_release_host(sdiodev->func);
//1: no byte mode

2
drivers/net/wireless/realtek/rtl8852bs/core/rtw_wnm.c
View File

@@ -846,7 +846,7 @@ void rtw_wnm_update_reassoc_req_ie(_adapter *padapter)
_rtw_memcpy(pdup, pmlmepriv->assoc_req, offset);
_rtw_memcpy(pdup + offset,
pmlmepriv->assoc_req + offset + ETH_ALEN,
pmlmepriv->assoc_req_len - offset);
dup_len - offset);
rtw_buf_update(&pmlmepriv->assoc_req,
&pmlmepriv->assoc_req_len, pdup, dup_len);
rtw_mfree(pdup, dup_len);

2
drivers/net/wireless/realtek/rtl8852bs/include/autoconf.h
View File

@@ -198,7 +198,7 @@
/*#define RTW_RECV_THREAD_HIGH_PRIORITY*/
#ifdef CONFIG_RTW_NAPI
#define CONFIG_RTW_NAPI_DYNAMIC
/*#define CONFIG_RTW_NAPI_DYNAMIC*/
#define CONFIG_RTW_NAPI_V2
#ifdef CONFIG_RTW_NAPI_V2
#define CONFIG_RX_BATCH_IND

2
drivers/net/wireless/realtek/rtl8852bs/include/drv_conf.h
View File

@@ -730,7 +730,7 @@ power down etc.) in last time, we can unmark this flag to avoid some unpredictab
#endif
/* for phl illegal mac io access check*/
#define CONFIG_MAC_REG_RW_CHK
//#define CONFIG_MAC_REG_RW_CHK
/* To enable the CONFIG_PHL_P2PPS definition in phl_config.h */
#ifdef CONFIG_P2P_PS

2
drivers/net/wireless/realtek/rtl8852bs/include/osdep_service.h
View File

@@ -99,7 +99,7 @@
#endif
extern int RTW_STATUS_CODE(int error_code);
extern u16 rtw_warn_on_cnt;
extern s32 rtw_warn_on_cnt;
#ifndef RTK_DMP_PLATFORM
#define CONFIG_USE_VMALLOC

2
drivers/net/wireless/realtek/rtl8852bs/os_dep/osdep_service_linux.c
View File

@@ -1075,5 +1075,5 @@ void rtw_wiphy_rfkill_set_hw_state(struct wiphy *wiphy, bool blocked)
wiphy_rfkill_set_hw_state(wiphy, blocked);
}
u16 rtw_warn_on_cnt;
s32 rtw_warn_on_cnt = 0;

1
drivers/pci/controller/dwc/pcie-k1x.c
View File

@@ -439,6 +439,7 @@ void rterm_force(struct k1x_pcie *k1x, u32 pcie_rcal)
#else
//REG32(PCIE_PUPHY_REG_BASE + (0x8 << 2)) |= 0x3 << 29;
val = k1x_pcie_phy_reg_readl(k1x, (0x8 << 2));
val &= ~(0x7 << 29);
val |= 0x3 << 29;
k1x_pcie_phy_reg_writel(k1x, (0x8 << 2), val);
#endif

4
drivers/soc/spacemit/v2d/v2d_iommu.c
View File

@@ -99,8 +99,8 @@ static void __write_tbu_table(struct v2d_iommu_res *res, struct tbu_instance *tb
mask = (res->page_size == 4096) ? 0xFFFFFFFFFFFFF000 : 0xFFFFFFFFFFFF0000;
ttb_entry = tbu->ttb_va + (iova - tbu->va_base) / res->page_size;
while (size != 0) {
paddr = paddr & 0xFFFFFFFF;
val = ((paddr & mask) >> TTB_ENTRY_SHIFT) & 0x1FFFFF;
paddr = paddr & 0x3FFFFFFFF;
val = ((paddr & mask) >> TTB_ENTRY_SHIFT) & 0x3FFFFF;
*ttb_entry = val;
size -= res->page_size;
ttb_entry++;

16
drivers/spi/spi-k1x.c
View File

@@ -721,9 +721,9 @@ static int k1x_spi_transfer_one_message(struct spi_master *master,
*/
drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
if (master->max_speed_hz != drv_data->cur_transfer->speed_hz) {
master->max_speed_hz = drv_data->cur_transfer->speed_hz;
clk_set_rate(drv_data->clk, master->max_speed_hz);
if ((drv_data->cur_transfer->speed_hz) \
&& (drv_data->cur_transfer->speed_hz != clk_get_rate(drv_data->clk))) {
clk_set_rate(drv_data->clk, drv_data->cur_transfer->speed_hz);
}
reinit_completion(&drv_data->cur_msg_completion);
@@ -823,9 +823,8 @@ static int setup(struct spi_device *spi)
chip->write = u32_writer;
}
if (spi->master->max_speed_hz != spi->max_speed_hz) {
spi->master->max_speed_hz = spi->max_speed_hz;
clk_set_rate(drv_data->clk, spi->master->max_speed_hz);
if (clk_get_rate(drv_data->clk) != spi->max_speed_hz) {
clk_set_rate(drv_data->clk, spi->max_speed_hz);
}
spi_set_ctldata(spi, chip);
@@ -1005,6 +1004,11 @@ static int k1x_spi_probe(struct platform_device *pdev)
clk_prepare_enable(drv_data->clk);
reset_control_deassert(drv_data->reset);
if ((master->bus_num == 2 || master->bus_num == 3) && \
of_get_property(np, "k1x,ssp-enable-clk-phase-adj", NULL)) {
k1x_spi_write(drv_data, CLK_PHASE_ADJ, 0x1);
}
/* Load default SSP configuration */
k1x_spi_write(drv_data, TOP_CTRL, 0);
k1x_spi_write(drv_data, FIFO_CTRL, 0);

1
drivers/spi/spi-k1x.h
View File

@@ -37,6 +37,7 @@
#define RWOT_CTRL 0x24 /* SSP RWOT Control Register */
#define RWOT_CCM 0x28 /* SSP RWOT Counter Cycles Match Register */
#define RWOT_CVWRn 0x2C /* SSP RWOT Counter Value Write for Read Request Register */
#define CLK_PHASE_ADJ 0x30 /* SSP clock phase adjustment for debug */
/* 0x00 TOP_CTRL */
#define TOP_TTELP (1 << 18)

34
drivers/tty/serial/pxa_k1x.c
View File

@@ -516,7 +516,7 @@ static void serial_pxa_start_tx(struct uart_port *port)
/* should hold up->port.lock */
static inline void check_modem_status(struct uart_pxa_port *up)
{
int status;
int status, dcts = 0;
status = serial_in(up, UART_MSR);
@@ -530,8 +530,24 @@ static inline void check_modem_status(struct uart_pxa_port *up)
up->port.icount.dsr++;
if (status & UART_MSR_DDCD)
uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
#if CONFIG_SOC_SPACEMIT_K1X
do {
if (status & UART_MSR_DCTS)
dcts = 1;
status = serial_in(up, UART_MSR);
if (status & UART_MSR_TERI)
up->port.icount.rng++;
if (status & UART_MSR_DDSR)
up->port.icount.dsr++;
if (status & UART_MSR_DDCD)
uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
} while ((status & UART_MSR_DCTS) != 0);
if (dcts)
uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
#else
if (status & UART_MSR_DCTS)
uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
#endif
spin_unlock(&up->port.lock);
wake_up_interruptible(&up->port.state->port.delta_msr_wait);
@@ -1462,13 +1478,6 @@ serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios,
// #endif
serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
/*
* the right DLL/DLH setting sequence is:
* write DLH --> read DLH --> write DLL
*/
serial_out(up, UART_DLM, (quot >> 8) & 0xff); /* MS of divisor */
(void) serial_in(up, UART_DLM);
serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
/*
@@ -1476,15 +1485,10 @@ serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios,
* Specification Update (Nov 2005)
*/
/*
* read DLL twice in case the uart semi-stable state to trigger this warning.
*/
(void) serial_in(up, UART_DLL);
dll = serial_in(up, UART_DLL);
WARN(dll != (quot & 0xff),
"uart %d baud %d target 0x%x real 0x%x\n",
up->port.line, baud, quot & 0xff, dll);
WARN_ON(dll != (quot & 0xff));
serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
serial_out(up, UART_LCR, cval); /* reset DLAB */
up->lcr = cval; /* Save LCR */
serial_pxa_set_mctrl(&up->port, up->port.mctrl);

5
include/linux/platform_data/k1x_sdhci.h
View File

@@ -83,6 +83,11 @@ struct k1x_sdhci_platdata {
u8 tx_dline_reg;
u8 tx_delaycode;
u8 tx_delaycode_cnt;
u32 tx_delaycode_array[2];
bool tx_need_update;
wait_queue_head_t wait_queue;
atomic_t ref_count;
u8 phy_driver_sel;
struct rx_tuning rxtuning;
u8 need_reset_dllcfg1;

72
rt-linux/rt-linux-support.patch
View File

@@ -465,7 +465,7 @@ index b1e6d275cda9..9a8d3970da3c 100644
}
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 247c53645ec7..1df5d327df54 100644
index 736791da9739..f7930f5a1a0d 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -52,6 +52,7 @@ config RISCV
@@ -6281,7 +6281,7 @@ index e308d5022b3f..3a95bf5d55d3 100644
/* serial core request to claim uart iomem */
diff --git a/drivers/tty/serial/pmac_zilog.c b/drivers/tty/serial/pmac_zilog.c
index 29bc80d39e8b..77691fbbf779 100644
index 29bc80d39e8b..5d0fbc7132f7 100644
--- a/drivers/tty/serial/pmac_zilog.c
+++ b/drivers/tty/serial/pmac_zilog.c
@@ -245,9 +245,9 @@ static bool pmz_receive_chars(struct uart_pmac_port *uap)
@@ -6445,7 +6445,7 @@ index 29bc80d39e8b..77691fbbf779 100644
unsigned long flags;
- spin_lock_irqsave(&port->lock, flags);
+ uart_port_lock_irqsave(port, &flags);
+ uart_port_lock_irqsave(port, &flags);
/* Disable IRQs on the port */
pmz_interrupt_control(uap, 0);
@@ -6591,10 +6591,10 @@ index 73c60f5ea027..46e70e155aab 100644
clk_disable(up->clk);
diff --git a/drivers/tty/serial/pxa_k1x.c b/drivers/tty/serial/pxa_k1x.c
index 6db39ca8a77b..571b6935218e 100644
index 0513d5af2696..b418f42b4a8d 100644
--- a/drivers/tty/serial/pxa_k1x.c
+++ b/drivers/tty/serial/pxa_k1x.c
@@ -175,13 +175,13 @@ static inline void stop_dma(struct uart_pxa_port *up, int read)
@@ -176,13 +176,13 @@ static inline void stop_dma(struct uart_pxa_port *up, int read)
channel = read ? pxa_dma->rxdma_chan : pxa_dma->txdma_chan;
dmaengine_terminate_all(channel);
@@ -6610,7 +6610,7 @@ index 6db39ca8a77b..571b6935218e 100644
}
static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
@@ -247,9 +247,9 @@ static void serial_pxa_stop_rx(struct uart_port *port)
@@ -256,9 +256,9 @@ static void serial_pxa_stop_rx(struct uart_port *port)
if (up->dma_enable) {
if (up->ier & UART_IER_DMAE) {
@@ -6622,7 +6622,7 @@ index 6db39ca8a77b..571b6935218e 100644
}
up->uart_dma.rx_stop = 1;
} else {
@@ -272,10 +272,10 @@ static inline void receive_chars(struct uart_pxa_port *up, int *status)
@@ -281,10 +281,10 @@ static inline void receive_chars(struct uart_pxa_port *up, int *status)
* Step 2
* Disable the Reciever Time Out Interrupt via IER[RTOEI]
*/
@@ -6635,7 +6635,7 @@ index 6db39ca8a77b..571b6935218e 100644
ch = serial_in(up, UART_RX);
flag = TTY_NORMAL;
@@ -342,10 +342,10 @@ static inline void receive_chars(struct uart_pxa_port *up, int *status)
@@ -351,10 +351,10 @@ static inline void receive_chars(struct uart_pxa_port *up, int *status)
* Step 6:
* No more data in FIFO: Re-enable RTO interrupt via IER[RTOIE]
*/
@@ -6648,7 +6648,7 @@ index 6db39ca8a77b..571b6935218e 100644
}
static void transmit_chars(struct uart_pxa_port *up)
@@ -360,9 +360,9 @@ static void transmit_chars(struct uart_pxa_port *up)
@@ -369,9 +369,9 @@ static void transmit_chars(struct uart_pxa_port *up)
return;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
@@ -6660,7 +6660,7 @@ index 6db39ca8a77b..571b6935218e 100644
return;
}
@@ -381,9 +381,9 @@ static void transmit_chars(struct uart_pxa_port *up)
@@ -390,9 +390,9 @@ static void transmit_chars(struct uart_pxa_port *up)
if (uart_circ_empty(xmit))
{
@@ -6672,16 +6672,7 @@ index 6db39ca8a77b..571b6935218e 100644
}
}
@@ -504,7 +504,7 @@ static void serial_pxa_start_tx(struct uart_port *port)
}
}
-/* should hold up->port.lock */
+/* should hold up->port */
static inline void check_modem_status(struct uart_pxa_port *up)
{
int status;
@@ -592,17 +592,17 @@ static unsigned int serial_pxa_tx_empty(struct uart_port *port)
@@ -605,17 +605,17 @@ static unsigned int serial_pxa_tx_empty(struct uart_port *port)
unsigned long flags;
unsigned int ret;
@@ -6702,7 +6693,7 @@ index 6db39ca8a77b..571b6935218e 100644
return ret;
}
@@ -676,13 +676,13 @@ static void serial_pxa_break_ctl(struct uart_port *port, int break_state)
@@ -689,13 +689,13 @@ static void serial_pxa_break_ctl(struct uart_port *port, int break_state)
struct uart_pxa_port *up = (struct uart_pxa_port *)port;
unsigned long flags;
@@ -6718,7 +6709,7 @@ index 6db39ca8a77b..571b6935218e 100644
}
static void pxa_uart_transmit_dma_start(struct uart_pxa_port *up, int count)
@@ -741,13 +741,13 @@ static void pxa_uart_receive_dma_start(struct uart_pxa_port *up)
@@ -754,13 +754,13 @@ static void pxa_uart_receive_dma_start(struct uart_pxa_port *up)
return;
}
@@ -6735,7 +6726,7 @@ index 6db39ca8a77b..571b6935218e 100644
slave_config.direction = DMA_DEV_TO_MEM;
slave_config.src_addr = up->port.mapbase;
@@ -913,13 +913,13 @@ static void pxa_uart_receive_dma_cb(void *data)
@@ -926,13 +926,13 @@ static void pxa_uart_receive_dma_cb(void *data)
}
tty_flip_buffer_push(port);
@@ -6751,7 +6742,7 @@ index 6db39ca8a77b..571b6935218e 100644
/* Mark the DMA buf[0] as 0xff for next checking and polling. */
#if (DMA_BUF_POLLING_SWITCH == 1)
@@ -974,13 +974,13 @@ static void pxa_uart_transmit_dma_cb(void *data)
@@ -987,13 +987,13 @@ static void pxa_uart_transmit_dma_cb(void *data)
schedule_work(&up->uart_tx_lpm_work);
}
@@ -6767,7 +6758,7 @@ index 6db39ca8a77b..571b6935218e 100644
/* if tx stop, stop transmit DMA and return */
if (pxa_dma->tx_stop || !serial_pxa_is_open(up)) {
@@ -1116,9 +1116,9 @@ static void uart_task_action(unsigned long data)
@@ -1129,9 +1129,9 @@ static void uart_task_action(unsigned long data)
return;
}
@@ -6779,7 +6770,7 @@ index 6db39ca8a77b..571b6935218e 100644
return;
}
@@ -1135,7 +1135,7 @@ static void uart_task_action(unsigned long data)
@@ -1148,7 +1148,7 @@ static void uart_task_action(unsigned long data)
count += c;
up->port.icount.tx += c;
}
@@ -6788,7 +6779,7 @@ index 6db39ca8a77b..571b6935218e 100644
pr_debug("count =%d", count);
pxa_uart_transmit_dma_start(up, count);
@@ -1190,12 +1190,12 @@ static int serial_pxa_startup(struct uart_port *port)
@@ -1203,12 +1203,12 @@ static int serial_pxa_startup(struct uart_port *port)
*/
serial_out(up, UART_LCR, UART_LCR_WLEN8);
@@ -6803,7 +6794,7 @@ index 6db39ca8a77b..571b6935218e 100644
/*
* Finally, enable interrupts. Note: Modem status interrupts
@@ -1209,14 +1209,14 @@ static int serial_pxa_startup(struct uart_port *port)
@@ -1222,14 +1222,14 @@ static int serial_pxa_startup(struct uart_port *port)
tasklet_init(&up->uart_dma.tklet, uart_task_action, (unsigned long)up);
}
@@ -6820,7 +6811,7 @@ index 6db39ca8a77b..571b6935218e 100644
/*
* And clear the interrupt registers again for luck.
@@ -1248,7 +1248,7 @@ static void serial_pxa_shutdown(struct uart_port *port)
@@ -1261,7 +1261,7 @@ static void serial_pxa_shutdown(struct uart_port *port)
/*
* Disable interrupts from this port
*/
@@ -6829,7 +6820,7 @@ index 6db39ca8a77b..571b6935218e 100644
up->ier = 0;
serial_out(up, UART_IER, 0);
@@ -1256,7 +1256,7 @@ static void serial_pxa_shutdown(struct uart_port *port)
@@ -1269,7 +1269,7 @@ static void serial_pxa_shutdown(struct uart_port *port)
tmp = serial_in(up, UART_MCR);
tmp &= ~TIOCM_OUT2;
serial_out(up, UART_MCR, tmp);
@@ -6838,7 +6829,7 @@ index 6db39ca8a77b..571b6935218e 100644
/*
* Disable break condition and FIFOs
@@ -1384,7 +1384,7 @@ serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios,
@@ -1397,7 +1397,7 @@ serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios,
* Ok, we're now changing the port state. Do it with
* interrupts disabled.
*/
@@ -6847,7 +6838,7 @@ index 6db39ca8a77b..571b6935218e 100644
/*
* Ensure the port will be enabled.
@@ -1480,7 +1480,7 @@ serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios,
@@ -1481,7 +1481,7 @@ serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios,
up->lcr = cval; /* Save LCR */
serial_pxa_set_mctrl(&up->port, up->port.mctrl);
serial_out(up, UART_FCR, fcr);
@@ -6856,7 +6847,7 @@ index 6db39ca8a77b..571b6935218e 100644
/*
* when console polling the xfer status, we use one-eighth of xfer
@@ -1578,16 +1578,16 @@ void serial_pxa_assert_rts(int port)
@@ -1579,16 +1579,16 @@ void serial_pxa_assert_rts(int port)
up = serial_pxa_ports[port];
@@ -6876,7 +6867,7 @@ index 6db39ca8a77b..571b6935218e 100644
return;
}
@@ -1606,14 +1606,14 @@ void serial_pxa_deassert_rts(int port)
@@ -1607,14 +1607,14 @@ void serial_pxa_deassert_rts(int port)
up = serial_pxa_ports[port];
@@ -6894,7 +6885,7 @@ index 6db39ca8a77b..571b6935218e 100644
return;
}
@@ -1702,13 +1702,10 @@ serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
@@ -1703,13 +1703,10 @@ serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
clk_enable(up->gclk);
clk_enable(up->fclk);
@@ -6911,7 +6902,7 @@ index 6db39ca8a77b..571b6935218e 100644
/*
* First save the IER then disable the interrupts
@@ -1726,8 +1723,7 @@ serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
@@ -1727,8 +1724,7 @@ serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
serial_out(up, UART_IER, ier);
if (locked)
@@ -6921,7 +6912,7 @@ index 6db39ca8a77b..571b6935218e 100644
clk_disable(up->fclk);
clk_disable(up->gclk);
}
@@ -1943,9 +1939,9 @@ static int serial_pxa_suspend(struct device *dev)
@@ -1944,9 +1940,9 @@ static int serial_pxa_suspend(struct device *dev)
if (dma_async_is_tx_complete(pxa_dma->rxdma_chan,
pxa_dma->rx_cookie, NULL, NULL) != DMA_COMPLETE) {
/* before stop receive, de-assert RTS */
@@ -11018,10 +11009,10 @@ index cba8b1a6a4cc..4c73e0b81acc 100644
/*
* Fixup the pi_state owner and possibly acquire the lock if we
diff --git a/kernel/irq/handle.c b/kernel/irq/handle.c
index 9489f93b3db3..faea1b4c020e 100644
index 9489f93b3db3..6ead078c64ad 100644
--- a/kernel/irq/handle.c
+++ b/kernel/irq/handle.c
@@ -158,9 +158,11 @@ irqreturn_t __handle_irq_event_percpu(struct irq_desc *desc)
@@ -158,9 +158,10 @@ irqreturn_t __handle_irq_event_percpu(struct irq_desc *desc)
res = action->handler(irq, action->dev_id);
trace_irq_handler_exit(irq, action, res);
@@ -11029,8 +11020,7 @@ index 9489f93b3db3..faea1b4c020e 100644
- irq, action->handler))
- local_irq_disable();
+ if (!IS_ENABLED(CONFIG_PREEMPT_RT)) {
+ if (WARN_ONCE(!irqs_disabled(),"irq %u handler %pS enabled interrupts\n",
+ irq, action->handler))
+ if (WARN_ONCE(!irqs_disabled(),"irq %u handler %pS enabled interrupts\n", irq, action->handler))
+ local_irq_disable();
+ }

4
scripts/package/mkdebian
View File

@@ -227,7 +227,7 @@ Architecture: $debarch
Description: Linux kernel, version $version
This package contains the Linux kernel, modules and corresponding other
files, version: $version.
Depends: spacemit-flash-dtbs
Depends: spacemit-flash-dtbs, bianbu-esos (= 0.0.9)
Provides: linux-image-$baseversion
EOF
@@ -246,7 +246,7 @@ Multi-Arch: same
Package: linux-tools-$version
Architecture: $debarch
Section: devel
Depends: linux-tools-common
Depends: linux-tools-common, libnuma-dev, libbabeltrace1, libpfm4, libtraceevent1
Description: Linux kernel version specific tools for version $version
This package provides the architecture dependant parts for kernel
version locked tools (such as perf) for

5
sound/soc/codecs/Kconfig
View File

@@ -115,6 +115,7 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_ES7134
imply SND_SOC_ES7210
imply SND_SOC_ES7241
imply SND_SOC_ES8375
imply SND_SOC_GTM601
imply SND_SOC_HDAC_HDMI
imply SND_SOC_HDAC_HDA
@@ -1086,6 +1087,10 @@ config SND_SOC_ES8328_SPI
depends on SPI_MASTER
select SND_SOC_ES8328
config SND_SOC_ES8375
tristate "Everest Semi ES8375 CODEC"
depends on I2C
config SND_SOC_GTM601
tristate 'GTM601 UMTS modem audio codec'

2
sound/soc/codecs/Makefile
View File

@@ -122,6 +122,7 @@ snd-soc-es8326-objs := es8326.o
snd-soc-es8328-objs := es8328.o
snd-soc-es8328-i2c-objs := es8328-i2c.o
snd-soc-es8328-spi-objs := es8328-spi.o
snd-soc-es8375-objs := es8375.o
snd-soc-gtm601-objs := gtm601.o
snd-soc-hdac-hdmi-objs := hdac_hdmi.o
snd-soc-hdac-hda-objs := hdac_hda.o
@@ -511,6 +512,7 @@ obj-$(CONFIG_SND_SOC_ES8326) += snd-soc-es8326.o
obj-$(CONFIG_SND_SOC_ES8328) += snd-soc-es8328.o
obj-$(CONFIG_SND_SOC_ES8328_I2C)+= snd-soc-es8328-i2c.o
obj-$(CONFIG_SND_SOC_ES8328_SPI)+= snd-soc-es8328-spi.o
obj-$(CONFIG_SND_SOC_ES8375) += snd-soc-es8375.o
obj-$(CONFIG_SND_SOC_GTM601) += snd-soc-gtm601.o
obj-$(CONFIG_SND_SOC_HDAC_HDMI) += snd-soc-hdac-hdmi.o
obj-$(CONFIG_SND_SOC_HDAC_HDA) += snd-soc-hdac-hda.o

954
sound/soc/codecs/es8375.c Executable file
View File

@@ -0,0 +1,954 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Based on code by Du lianghan
* Copyright (C) 2025 Everest Semiconductor Co., Ltd
*/
#include <linux/gpio/consumer.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include <sound/soc.h>
#include <linux/acpi.h>
#include "es8375.h"
#if IS_ENABLED(CONFIG_SND_SOC_SPACEMIT)
#define SPACEMIT_CONFIG_CODEC_ES8375
#endif
/* codec private data */
struct es8375_priv {
struct snd_soc_component *codec;
struct regmap *regmap;
struct clk *mclk;
unsigned long mclk_freq;
int mastermode;
bool sclkinv;
bool mclkinv;
bool dmic_enable;
u8 dmic_pol;
u8 mclk_src;
u8 vdda;
u8 vddd;
enum snd_soc_bias_level bias_level;
struct gpio_desc *pa_ctl_gpio;
u8 stream_status;
};
struct snd_soc_component *es8375_RegMap_codec;
/*
static int es8375_set_gpio(struct es8375_priv *es8375, bool level)
{
printk("enter into %s, level = %d\n", __func__, level);
gpiod_set_value(es8375->pa_ctl_gpio, level);
return 0;
}
*/
static const DECLARE_TLV_DB_SCALE(es8375_adc_osr_gain_tlv, -3100, 100, 0);
static const DECLARE_TLV_DB_SCALE(es8375_adc_volume_tlv, -9550, 50, 0);
static const DECLARE_TLV_DB_SCALE(es8375_adc_automute_attn_tlv, 0, 100, 0);
static const DECLARE_TLV_DB_SCALE(es8375_dac_volume_tlv, -9550, 50, 0);
static const DECLARE_TLV_DB_SCALE(es8375_dac_vppscale_tlv, -388, 12, 0);
static const DECLARE_TLV_DB_SCALE(es8375_dac_automute_attn_tlv, 0, 400, 0);
static const char *const es8375_dmic_gain_txt[] = {
"x1",
"x2",
"x4",
"x8",
};
static SOC_ENUM_SINGLE_DECL(es8375_dmic_gain, ES8375_ADC1_0x17,
DMIC_GAIN_SHIFT_2, es8375_dmic_gain_txt);
static const char *const es8375_ramprate_txt[] = {
"0.125dB/LRCK",
"0.125dB/2LRCK",
"0.125dB/4LRCK",
"0.125dB/8LRCK",
"0.125dB/16LRCK",
"0.125dB/32LRCK",
"0.125dB/64LRCK",
"0.125dB/128LRCK",
"disable softramp",
"disable softramp",
"disable softramp",
"disable softramp",
"disable softramp",
"disable softramp",
"disable softramp",
"disable softramp",
};
static SOC_ENUM_SINGLE_DECL(es8375_adc_ramprate, ES8375_ADC2_0x18,
ADC_RAMPRATE_SHIFT_0, es8375_ramprate_txt);
static SOC_ENUM_SINGLE_DECL(es8375_dac_ramprate, ES8375_DAC2_0x20,
DAC_RAMPRATE_SHIFT_0, es8375_ramprate_txt);
static const char *const es8375_automute_ws_txt[] = {
"256 samples",
"512 samples",
"1024 samples",
"2048 samples",
"4096 samples",
"8192 samples",
"16384 samples",
"32768 samples",
};
static SOC_ENUM_SINGLE_DECL(es8375_adc_automute_ws, ES8375_ADC_AUTOMUTE_0x1B,
ADC_AUTOMUTE_WS_SHIFT_3, es8375_automute_ws_txt);
static SOC_ENUM_SINGLE_DECL(es8375_dac_automute_ws, ES8375_DAC_AUTOMUTE_0x24,
DAC_AUTOMUTE_WS_SHIFT_5, es8375_automute_ws_txt);
static const char *const es8375_adc_automute_ng_txt[] = {
"-96dB (default)",
"-90dB",
"-84dB",
"-78dB",
"-72dB",
"-66dB",
"-60dB",
"-54dB",
};
static SOC_ENUM_SINGLE_DECL(es8375_adc_automute_ng, ES8375_ADC_AUTOMUTE_0x1B,
ADC_AUTOMUTE_NG_SHIFT_0, es8375_adc_automute_ng_txt);
static const char *const es8375_dac_automute_ng_txt[] = {
"-144dB (default)",
"-90dB",
"-84dB",
"-78dB",
"-72dB",
"-66dB",
"-60dB",
"-54dB",
};
static SOC_ENUM_SINGLE_DECL(es8375_dac_automute_ng, ES8375_DAC_AUTOMUTE1_0x23,
DAC_AUTOMUTE_NG_SHIFT_0, es8375_dac_automute_ng_txt);
static const char *const es8375_adc_src_txt[] = {
"ADC data source select as AMIC",
"ADC data source select as DMICL",
};
static SOC_ENUM_SINGLE_DECL(es8375_adc_src, ES8375_ADC1_0x17,
ADC_SRC_SHIFT_7, es8375_adc_src_txt);
static const char *const es8375_dmic_pol_txt[] = {
"Low = Left Channel ; High = Right Channel. (default)",
"Low = Right Channel ; High = Left Channel.",
};
static SOC_ENUM_SINGLE_DECL(es8375_dmic_pol, ES8375_ADC1_0x17,
DMIC_POL_SHIFT_4, es8375_dmic_pol_txt);
static const char *const es8375_adc_hpf_txt[] = {
"Freeze Offset",
"Dynamic HPF (default)",
};
static SOC_ENUM_SINGLE_DECL(es8375_adc_hpf, ES8375_HPF1_0x1D,
ADC_HPF_SHIFT_5, es8375_adc_hpf_txt);
static const struct snd_kcontrol_new es8375_snd_controls[] = {
/* Capture Path */
SOC_SINGLE_TLV("ADC OSR GAIN", ES8375_ADC_OSR_GAIN_0x19,
ADC_OSR_GAIN_SHIFT_0, ES8375_ADC_OSR_GAIN_MAX, 0,
es8375_adc_osr_gain_tlv),
SOC_ENUM("ADC Source Select", es8375_adc_src),
SOC_SINGLE("ADC Invert", ES8375_ADC1_0x17, ADC_INV_SHIFT_6, 1, 0),
SOC_SINGLE("ADC RAM Clear", ES8375_ADC1_0x17, ADC_RAMCLR_SHIFT_5, 1, 0),
SOC_ENUM("DMIC Polarity", es8375_dmic_pol),
SOC_ENUM("DMIC Gain Select", es8375_dmic_gain),
SOC_ENUM("ADC Ramp Rate", es8375_adc_ramprate),
SOC_SINGLE_TLV("ADC Volume", ES8375_ADC_VOLUME_0x1A,
ADC_VOLUME_SHIFT_0, ES8375_ADC_VOLUME_MAX,
0, es8375_adc_volume_tlv),
SOC_SINGLE("ADC Automute Enable", ES8375_ADC_AUTOMUTE_0x1B,
ADC_AUTOMUTE_SHIFT_7, 1, 0),
SOC_ENUM("ADC Automute Winsize", es8375_adc_automute_ws),
SOC_ENUM("ADC Automute Noise Gate", es8375_adc_automute_ng),
SOC_SINGLE_TLV("ADC Automute Attenuation", ES8375_ADC_AUTOMUTE_ATTN_0x1C,
ADC_AUTOMUTE_ATTN_SHIFT_0, ES8375_ADC_AUTOMUTE_ATTN_MAX,
0, es8375_adc_automute_attn_tlv),
SOC_ENUM("ADC HPF", es8375_adc_hpf),
/* Playback Path */
SOC_SINGLE("DAC DSM Mute", ES8375_DAC1_0x1F, DAC_DSMMUTE_SHIFT_7, 1, 0),
SOC_SINGLE("DAC DEM Mute", ES8375_DAC1_0x1F, DAC_DEMMUTE_SHIFT_6, 1, 0),
SOC_SINGLE("DAC Invert", ES8375_DAC1_0x1F, DAC_INV_SHIFT_5, 1, 0),
SOC_SINGLE("DAC RAM Clear", ES8375_DAC1_0x1F, DAC_RAMCLR_SHIFT_4, 1, 0),
SOC_ENUM("DAC Ramp Rate", es8375_dac_ramprate),
SOC_SINGLE_TLV("DAC Volume", ES8375_DAC_VOLUME_0x21,
DAC_VOLUME_SHIFT_0, ES8375_DAC_VOLUME_MAX,
0, es8375_dac_volume_tlv),
SOC_SINGLE_TLV("DAC VPP Scale", ES8375_DAC_VPPSCALE_0x22,
DAC_VPPSCALE_SHIFT_0, ES8375_DAC_VPPSCALE_MAX,
0, es8375_dac_vppscale_tlv),
SOC_SINGLE("DAC Automute Enable", ES8375_DAC_AUTOMUTE1_0x23,
DAC_AUTOMUTE_EN_SHIFT_7, 1, 0),
SOC_ENUM("DAC Automute Noise Gate", es8375_dac_automute_ng),
SOC_ENUM("DAC Automute Winsize", es8375_dac_automute_ws),
SOC_SINGLE_TLV("DAC Automute Attenuation", ES8375_DAC_AUTOMUTE_0x24,
DAC_AUTOMUTE_ATTN_SHIFT_0, ES8375_DAC_AUTOMUTE_ATTN_MAX,
0, es8375_dac_automute_attn_tlv),
};
static const struct snd_soc_dapm_widget es8375_dapm_widgets[] = {
/* Capture Path */
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_PGA("PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_ADC("Mono ADC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, ES8375_SDP2_0x16,
ES8375_ADC_P2S_MUTE_SHIFT_5, 1),
/* Playback Path */
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, ES8375_SDP_0x15,
ES8375_DAC_S2P_MUTE_SHIFT_6, 1),
SND_SOC_DAPM_DAC("Mono DAC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("OUT"),
};
static const struct snd_soc_dapm_route es8375_dapm_routes[] = {
/* Capture Path */
{ "PGA", NULL, "MIC1" },
{ "Mono ADC", NULL, "PGA" },
{ "AIF1TX", NULL, "Mono ADC" },
/* Playback Path */
{ "Mono DAC", NULL, "AIF1RX" },
{ "OUT", NULL, "Mono DAC" },
};
struct _coeff_div {
u16 mclk_lrck_ratio;
u32 mclk;
u32 rate;
u8 Reg0x04;
u8 Reg0x05;
u8 Reg0x06;
u8 Reg0x07;
u8 Reg0x08;
u8 Reg0x09;
u8 Reg0x0A;
u8 Reg0x0B;
u8 Reg0x19;
u8 dvdd_vol;
u8 dmic_sel;
};
static const struct _coeff_div coeff_div[] = {
{32, 256000, 8000, 0x05, 0x34, 0xDD, 0x55, 0x1F, 0x00, 0x95, 0x00, 0x1F, 2, 2},
{32, 512000, 16000, 0x05, 0x34, 0xDD, 0x55, 0x1F, 0x00, 0x94, 0x00, 0x1F, 2, 2},
{32, 1536000, 48000, 0x05, 0x33, 0xD5, 0x55, 0x1F, 0x00, 0x93, 0x00, 0x1F, 2, 2},
{36, 288000, 8000, 0x05, 0x34, 0xDD, 0x55, 0x23, 0x08, 0x95, 0x00, 0x1F, 2, 2},
{36, 576000, 16000, 0x05, 0x34, 0xDD, 0x55, 0x23, 0x08, 0x94, 0x00, 0x1F, 2, 2},
{36, 1728000, 48000, 0x05, 0x33, 0xD5, 0x55, 0x23, 0x08, 0x93, 0x00, 0x1F, 2, 2},
{48, 384000, 8000, 0x05, 0x14, 0x5D, 0x55, 0x17, 0x20, 0x94, 0x00, 0x28, 2, 2},
{48, 768000, 16000, 0x05, 0x14, 0x5D, 0x55, 0x17, 0x20, 0x94, 0x00, 0x28, 2, 2},
{48, 2304000, 48000, 0x05, 0x11, 0x53, 0x55, 0x17, 0x20, 0x92, 0x00, 0x28, 2, 2},
{50, 400000, 8000, 0x05, 0x14, 0x5D, 0x55, 0x18, 0x24, 0x94, 0x00, 0x27, 2, 2},
{50, 800000, 16000, 0x05, 0x14, 0x5D, 0x55, 0x18, 0x24, 0x94, 0x00, 0x27, 2, 2},
{50, 2400000, 48000, 0x05, 0x11, 0x53, 0x55, 0x18, 0x24, 0x92, 0x00, 0x27, 2, 2},
{64, 512000, 8000, 0x05, 0x14, 0x5D, 0x33, 0x1F, 0x00, 0x94, 0x00, 0x1F, 2, 2},
{64, 1024000, 16000, 0x05, 0x13, 0x55, 0x33, 0x1F, 0x00, 0x93, 0x00, 0x1F, 2, 2},
{64, 3072000, 48000, 0x05, 0x11, 0x53, 0x33, 0x1F, 0x00, 0x92, 0x00, 0x1F, 2, 2},
{72, 576000, 8000, 0x05, 0x14, 0x5D, 0x33, 0x23, 0x08, 0x94, 0x00, 0x1F, 2, 2},
{72, 1152000, 16000, 0x05, 0x13, 0x55, 0x33, 0x23, 0x08, 0x93, 0x00, 0x1F, 2, 2},
{72, 3456000, 48000, 0x05, 0x11, 0x53, 0x33, 0x23, 0x08, 0x92, 0x00, 0x1F, 2, 2},
{96, 768000, 8000, 0x15, 0x34, 0xDD, 0x55, 0x1F, 0x00, 0x94, 0x00, 0x1F, 2, 2},
{96, 1536000, 16000, 0x15, 0x34, 0xDD, 0x55, 0x1F, 0x00, 0x93, 0x00, 0x1F, 2, 2},
{96, 4608000, 48000, 0x15, 0x33, 0xD5, 0x55, 0x1F, 0x00, 0x92, 0x00, 0x1F, 2, 2},
{100, 800000, 8000, 0x05, 0x03, 0x35, 0x33, 0x18, 0x24, 0x94, 0x00, 0x27, 2, 2},
{100, 1600000, 16000, 0x05, 0x03, 0x35, 0x33, 0x18, 0x24, 0x93, 0x00, 0x27, 2, 2},
{100, 4800000, 48000, 0x03, 0x00, 0x31, 0x33, 0x18, 0x24, 0x92, 0x00, 0x27, 2, 2},
{128, 1024000, 8000, 0x05, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x93, 0x01, 0x1F, 2, 2},
{128, 2048000, 16000, 0x03, 0x01, 0x33, 0x11, 0x1F, 0x00, 0x92, 0x01, 0x1F, 2, 2},
{128, 6144000, 48000, 0x03, 0x00, 0x31, 0x11, 0x1F, 0x00, 0x92, 0x01, 0x1F, 2, 2},
{144, 1152000, 8000, 0x05, 0x03, 0x35, 0x11, 0x23, 0x08, 0x93, 0x01, 0x1F, 2, 2},
{144, 2304000, 16000, 0x03, 0x01, 0x33, 0x11, 0x23, 0x08, 0x92, 0x01, 0x1F, 2, 2},
{144, 6912000, 48000, 0x03, 0x00, 0x31, 0x11, 0x23, 0x08, 0x92, 0x01, 0x1F, 2, 2},
{192, 1536000, 8000, 0x15, 0x14, 0x5D, 0x33, 0x1F, 0x00, 0x93, 0x02, 0x1F, 2, 2},
{192, 3072000, 16000, 0x15, 0x13, 0x55, 0x33, 0x1F, 0x00, 0x92, 0x02, 0x1F, 2, 2},
{192, 9216000, 48000, 0x15, 0x11, 0x53, 0x33, 0x1F, 0x00, 0x92, 0x02, 0x1F, 2, 2},
{250, 12000000, 48000, 0x25, 0x11, 0x53, 0x55, 0x18, 0x24, 0x92, 0x04, 0x27, 2, 2},
{256, 2048000, 8000, 0x0D, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x03, 0x1F, 2, 2},
{256, 4096000, 16000, 0x0B, 0x01, 0x33, 0x11, 0x1F, 0x00, 0x92, 0x03, 0x1F, 2, 2},
{256, 12288000, 48000, 0x0B, 0x00, 0x31, 0x11, 0x1F, 0x00, 0x92, 0x03, 0x1F, 2, 2},
{384, 3072000, 8000, 0x15, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x05, 0x1F, 2, 2},
{384, 6144000, 16000, 0x13, 0x01, 0x33, 0x11, 0x1F, 0x00, 0x92, 0x05, 0x1F, 2, 2},
{384, 18432000, 48000, 0x13, 0x00, 0x31, 0x11, 0x1F, 0x00, 0x92, 0x05, 0x1F, 2, 2},
{400, 19200000, 48000, 0x1B, 0x00, 0x31, 0x33, 0x18, 0x24, 0x92, 0x04, 0x27, 2, 2},
{500, 24000000, 48000, 0x23, 0x00, 0x31, 0x33, 0x18, 0x24, 0x92, 0x04, 0x27, 2, 2},
{512, 4096000, 8000, 0x1D, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x07, 0x1F, 2, 2},
{512, 8192000, 16000, 0x1B, 0x01, 0x33, 0x11, 0x1F, 0x00, 0x92, 0x07, 0x1F, 2, 2},
{512, 24576000, 48000, 0x1B, 0x00, 0x31, 0x11, 0x1F, 0x00, 0x92, 0x07, 0x1F, 2, 2},
{768, 6144000, 8000, 0x2D, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x0B, 0x1F, 2, 2},
{768, 12288000, 16000, 0x2B, 0x01, 0x33, 0x11, 0x1F, 0x00, 0x92, 0x0B, 0x1F, 2, 2},
{1024, 8192000, 8000, 0x3D, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x0F, 0x1F, 2, 2},
{1024, 16384000, 16000, 0x3B, 0x01, 0x33, 0x11, 0x1F, 0x00, 0x92, 0x0F, 0x1F, 2, 2},
{1152, 9216000, 8000, 0x45, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x0F, 0x1F, 2, 2},
{1152, 18432000, 16000, 0x43, 0x01, 0x33, 0x11, 0x1F, 0x00, 0x92, 0x0F, 0x1F, 2, 2},
{1200, 9600000, 8000, 0x5D, 0x03, 0x35, 0x33, 0x18, 0x24, 0x92, 0x11, 0x27, 2, 2},
{1200, 19200000, 16000, 0x5D, 0x03, 0x35, 0x33, 0x18, 0x24, 0x92, 0x11, 0x27, 2, 2},
{1536, 12288000, 8000, 0x5D, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x17, 0x1F, 2, 2},
{1536, 24576000, 16000, 0x5B, 0x01, 0x33, 0x11, 0x1F, 0x00, 0x92, 0x17, 0x1F, 2, 2},
{2048, 16384000, 8000, 0x7D, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x1F, 0x1F, 2, 2},
{2304, 18432000, 8000, 0x8D, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x23, 0x1F, 2, 2},
{2400, 19200000, 8000, 0xBD, 0x03, 0x35, 0x33, 0x18, 0x24, 0x92, 0x25, 0x27, 2, 2},
{3072, 24576000, 8000, 0xBD, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x2F, 0x1F, 2, 2},
{32, 3072000, 96000, 0x05, 0x11, 0x53, 0x55, 0x0F, 0x00, 0x92, 0x00, 0x37, 2, 2},
{64, 6144000, 96000, 0x03, 0x00, 0x31, 0x33, 0x0F, 0x00, 0x92, 0x00, 0x37, 2, 2},
{96, 9216000, 96000, 0x15, 0x11, 0x53, 0x55, 0x0F, 0x00, 0x92, 0x00, 0x37, 2, 2},
{128, 12288000, 96000, 0x0B, 0x00, 0x31, 0x33, 0x0F, 0x00, 0x92, 0x01, 0x37, 2, 2},
};
static inline int get_coeff(u8 vddd, u8 dmic, int mclk, int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk) {
if ((vddd == ES8375_1V8) && (dmic == 1) &&
(coeff_div[i].dvdd_vol != 1) &&
(coeff_div[i].dmic_sel != 0)) {
return i;
} else if ((vddd == ES8375_1V8) && (dmic == 0) &&
(coeff_div[i].dvdd_vol != 1) &&
(coeff_div[i].dmic_sel != 1)) {
return i;
} else if ((vddd == ES8375_3V3) && (dmic == 1) &&
(coeff_div[i].dvdd_vol != 0) &&
(coeff_div[i].dmic_sel != 0)) {
return i;
} else if ((vddd == ES8375_3V3) && (dmic == 0) &&
(coeff_div[i].dvdd_vol != 0) &&
(coeff_div[i].dmic_sel != 1)) {
return i;
}
}
}
return -EINVAL;
}
static int es8375_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *codec = dai->component;
struct es8375_priv *es8375 = snd_soc_component_get_drvdata(codec);
int par_width = params_width(params);
u16 iface = 0;
int coeff;
printk("Enter into %s()\n", __func__);
if (es8375->mclk_src == ES8375_BCLK_PIN) {
if (es8375->mastermode) {
dev_err(codec->dev, "no mclk, cannot as master\n");
return -EINVAL;
}
snd_soc_component_update_bits(codec,
ES8375_MCLK_SEL_0x01, 0x80, 0x80);
es8375->mclk_freq = 2 * (unsigned int)par_width * params_rate(params);
}
printk("%s, mclk = %lu, lrck = %u\n", __func__, es8375->mclk_freq,
params_rate(params));
coeff = get_coeff(es8375->vddd, es8375->dmic_enable,
es8375->mclk_freq, params_rate(params));
if (coeff < 0) {
printk("Unable to configure sample rate %uHz with %luHz MCLK\n",
params_rate(params), es8375->mclk_freq);
return -EINVAL;
}
/*
* set clock parammeters
*/
snd_soc_component_write(codec, ES8375_CLK_MGR_0x04,
coeff_div[coeff].Reg0x04);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x05,
coeff_div[coeff].Reg0x05);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x06,
coeff_div[coeff].Reg0x06);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x07,
coeff_div[coeff].Reg0x07);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x08,
coeff_div[coeff].Reg0x08);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x09,
coeff_div[coeff].Reg0x09);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x0A,
coeff_div[coeff].Reg0x0A);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x0B,
coeff_div[coeff].Reg0x0B);
snd_soc_component_write(codec, ES8375_ADC_OSR_GAIN_0x19,
coeff_div[coeff].Reg0x19);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
iface |= 0x0c;
break;
case SNDRV_PCM_FORMAT_S20_3LE:
iface |= 0x04;
break;
case SNDRV_PCM_FORMAT_S24_LE:
break;
case SNDRV_PCM_FORMAT_S32_LE:
iface |= 0x10;
break;
}
/* set iface */
snd_soc_component_update_bits(codec, ES8375_SDP_0x15, 0x1c, iface);
return 0;
}
static int es8375_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *codec = dai->component;
struct es8375_priv *es8375 = snd_soc_component_get_drvdata(codec);
es8375->mclk_freq = freq;
return 0;
}
static int es8375_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *codec = codec_dai->component;
struct es8375_priv *es8375 = snd_soc_component_get_drvdata(codec);
u8 iface = 0;
u8 codeciface = 0;
dev_dbg(codec->dev, "Enter into %s()\n", __func__);
codeciface = snd_soc_component_read(codec, ES8375_SDP_0x15);
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM: /* MASTER MODE */
es8375->mastermode = 1;
dev_dbg(codec->dev, "ES8375 in Master mode\n");
snd_soc_component_update_bits(codec, ES8375_RESET1_0x00,
0x80, 0x80);
break;
case SND_SOC_DAIFMT_CBS_CFS: /* SLAVE MODE */
es8375->mastermode = 0;
dev_dbg(codec->dev, "ES8375 in Slave mode\n");
snd_soc_component_update_bits(codec, ES8375_RESET1_0x00,
0x80, 0x00);
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
dev_dbg(codec->dev, "ES8375 in I2S Format\n");
codeciface &= 0xFC;
break;
case SND_SOC_DAIFMT_RIGHT_J:
return -EINVAL;
case SND_SOC_DAIFMT_LEFT_J:
dev_dbg(codec->dev, "ES8375 in LJ Format\n");
codeciface &= 0xFC;
codeciface |= 0x01;
break;
case SND_SOC_DAIFMT_DSP_A:
dev_dbg(codec->dev, "ES8375 in DSP-A Format\n");
codeciface &= 0xDC;
codeciface |= 0x03;
break;
case SND_SOC_DAIFMT_DSP_B:
dev_dbg(codec->dev, "ES8375 in DSP-B Format\n");
codeciface &= 0xDC;
codeciface |= 0x23;
break;
default:
return -EINVAL;
}
iface = snd_soc_component_read(codec, ES8375_CLK_MGR_0x03);
#ifdef SPACEMIT_CONFIG_CODEC_ES8375
snd_soc_component_write(codec, ES8375_SDP_0x15, codeciface);
#endif
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
iface &= 0xFE;
codeciface &= 0xDF;
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x01;
codeciface |= 0x20;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x01;
codeciface &= 0xDF;
break;
case SND_SOC_DAIFMT_NB_IF:
iface &= 0xFE;
codeciface |= 0x20;
break;
default:
return -EINVAL;
}
snd_soc_component_write(codec, ES8375_CLK_MGR_0x03, iface);
#ifndef SPACEMIT_CONFIG_CODEC_ES8375
snd_soc_component_write(codec, ES8375_SDP_0x15, codeciface);
#else
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
break;
default:
snd_soc_component_write(codec, ES8375_SDP_0x15, codeciface);
break;
}
#endif
return 0;
}
static int es8375_set_bias_level(struct snd_soc_component *codec,
enum snd_soc_bias_level level)
{
struct es8375_priv *es8375 = snd_soc_component_get_drvdata(codec);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
printk("%s on\n", __func__);
ret = clk_prepare_enable(es8375->mclk);
if (ret) {
dev_err(codec->dev, "unable to prepare mclk\n");
return ret;
}
snd_soc_component_write(codec, ES8375_CSM1_0x0F, 0xA6);
break;
case SND_SOC_BIAS_PREPARE:
printk("%s prepare\n", __func__);
break;
case SND_SOC_BIAS_STANDBY:
printk("%s standby\n", __func__);
snd_soc_component_write(codec, ES8375_CSM1_0x0F, 0x96);
clk_disable_unprepare(es8375->mclk);
break;
case SND_SOC_BIAS_OFF:
printk("%s off\n", __func__);
/* power down analog to get minimum power consumption */
snd_soc_component_write(codec, ES8375_CSM1_0x0F, 0x3C);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x03, 0x48);
snd_soc_component_write(codec, ES8375_CSM2_0x10, 0x80);
snd_soc_component_write(codec, ES8375_CSM1_0x0F, 0x3E);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x0A, 0x15);
snd_soc_component_write(codec, ES8375_SYS_CTRL2_0xF9, 0x0C);
snd_soc_component_write(codec, ES8375_RESET1_0x00, 0x00);
break;
}
return 0;
}
static int es8375_mute(struct snd_soc_dai *dai, int mute, int stream)
{
struct snd_soc_component *codec = dai->component;
struct es8375_priv *es8375 = snd_soc_component_get_drvdata(codec);
printk("Enter into %s(), mute = %d, stream_status = %d\n",
__func__, mute, es8375->stream_status);
return 0;
}
#define es8375_RATES SNDRV_PCM_RATE_8000_96000
#define es8375_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops es8375_ops = {
.hw_params = es8375_hw_params,
.mute_stream = es8375_mute,
.set_sysclk = es8375_set_sysclk,
.set_fmt = es8375_set_dai_fmt,
};
static struct snd_soc_dai_driver es8375_dai = {
.name = "ES8375 HiFi",
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = es8375_RATES,
.formats = es8375_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = es8375_RATES,
.formats = es8375_FORMATS,
},
.ops = &es8375_ops,
.symmetric_rate = 1,
};
static void es8375_init(struct snd_soc_component *codec)
{
struct es8375_priv *es8375 = snd_soc_component_get_drvdata(codec);
printk("Enter into %s()\n", __func__);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x0A, 0x95);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x03, 0x48);
snd_soc_component_write(codec, ES8375_DIV_SPKCLK_0x0E, 0x18);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x04, 0x02);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x05, 0x05);
snd_soc_component_write(codec, ES8375_CSM1_0x0F, 0x82);
snd_soc_component_write(codec, ES8375_VMID_CHARGE2_T_0x11, 0x20);
snd_soc_component_write(codec, ES8375_VMID_CHARGE3_T_0x12, 0x20);
snd_soc_component_write(codec, ES8375_DAC_CAL_0x25, 0x28);
snd_soc_component_write(codec, ES8375_ANALOG_SPK1_0x28, 0xFC);
snd_soc_component_write(codec, ES8375_ANALOG_SPK2_0x29, 0xE0);
snd_soc_component_write(codec, ES8375_VMID_SEL_0x2D, 0xFE);
snd_soc_component_write(codec, ES8375_ANALOG_0x2E, 0xB8);
snd_soc_component_write(codec, ES8375_SYS_CTRL2_0xF9, 0x03);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x02, 0x16);
snd_soc_component_write(codec, ES8375_RESET1_0x00, 0x00);
msleep(80);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x03, 0x00);
snd_soc_component_write(codec, ES8375_CSM1_0x0F, 0x86);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x04, 0x0B);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x05, 0x00);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x06, 0x31);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x07, 0x11);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x08, 0x1F);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x09, 0x00);
snd_soc_component_write(codec, ES8375_ADC_OSR_GAIN_0x19, 0x1F);
snd_soc_component_write(codec, ES8375_ADC2_0x18, 0x00);
snd_soc_component_write(codec, ES8375_DAC2_0x20, 0x00);
snd_soc_component_write(codec, ES8375_ADC_VOLUME_0x1A, 0xBF);
snd_soc_component_write(codec, ES8375_DAC_VOLUME_0x21, 0xBF);
snd_soc_component_write(codec, ES8375_DAC_OTP_0x27, 0x88);
snd_soc_component_write(codec, ES8375_ANALOG_SPK2_0x29, 0xE7);
snd_soc_component_write(codec, ES8375_ANALOG_0x32, 0xF0);
snd_soc_component_write(codec, ES8375_ANALOG_0x37, 0x40);
snd_soc_component_write(codec, ES8375_CLK_MGR_0x02, 0xFE);
es8375->stream_status = 0;
}
static int es8375_suspend(struct snd_soc_component *codec)
{
return 0;
}
static int es8375_resume(struct snd_soc_component *codec)
{
return 0;
}
static int es8375_codec_probe(struct snd_soc_component *codec)
{
struct es8375_priv *es8375 = snd_soc_component_get_drvdata(codec);
printk("Enter into %s()\n", __func__);
es8375->codec = codec;
es8375->mastermode = 0;
es8375_RegMap_codec = codec;
es8375_init(codec);
return 0;
}
static bool es8375_writeable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case ES8375_CHIP_VERSION_0xFF:
case ES8375_CHIP_ID0_0xFE:
case ES8375_CHIP_ID1_0xFD:
case ES8375_SPK_OFFSET_0xFC:
case ES8375_FLAGS2_0xFB:
return false;
default:
return true;
}
}
static struct regmap_config es8375_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = ES8375_REG_MAX,
.cache_type = REGCACHE_RBTREE,
.use_single_read = true,
.use_single_write = true,
.writeable_reg = es8375_writeable_register,
};
static struct snd_soc_component_driver es8375_codec_driver = {
.probe = es8375_codec_probe,
.suspend = es8375_suspend,
.resume = es8375_resume,
.set_bias_level = es8375_set_bias_level,
.controls = es8375_snd_controls,
.num_controls = ARRAY_SIZE(es8375_snd_controls),
.dapm_widgets = es8375_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(es8375_dapm_widgets),
.dapm_routes = es8375_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(es8375_dapm_routes),
.idle_bias_on = 1,
.suspend_bias_off = 1,
};
static int es8375_read_device_properities(struct device *dev, struct es8375_priv *es8375)
{
int ret;
ret = device_property_read_u8(dev, "everest,mclk-src", &es8375->mclk_src);
if (ret != 0) {
dev_dbg(dev, "mclk-src return %d", ret);
es8375->mclk_src = ES8375_MCLK_SOURCE;
}
dev_dbg(dev, "mclk-src %x", es8375->mclk_src);
ret = device_property_read_u8(dev, "everest,vddd-voltage", &es8375->vddd);
if (ret != 0) {
dev_dbg(dev, "vddd-voltage return %d", ret);
es8375->vddd = ES8375_DVDD;
}
dev_dbg(dev, "vddd-voltage %x", es8375->vddd);
es8375->dmic_enable = device_property_read_bool(dev, "everest,dmic-enabled");
dev_dbg(dev, "dmic_enable %x", es8375->dmic_enable);
ret = device_property_read_u8(dev, "everest,dmic-pol", &es8375->dmic_pol);
if (ret != 0) {
dev_dbg(dev, "dmic-pol return %d", ret);
es8375->dmic_pol = DMIC_POL;
}
dev_dbg(dev, "dmic-pol %x", es8375->dmic_pol);
es8375->mclkinv = device_property_read_bool(dev, "everest,mclk-inverted");
dev_dbg(dev, "mclk-inverted %x", es8375->mclkinv);
es8375->sclkinv = device_property_read_bool(dev, "everest,sclk-inverted");
dev_dbg(dev, "sclk-inverted %x", es8375->sclkinv);
#ifndef SPACEMIT_CONFIG_CODEC_ES8375
es8375->mclk = devm_clk_get(dev, "mclk");
if (IS_ERR(es8375->mclk)) {
dev_err(dev, "unable to get mclk\n");
return PTR_ERR(es8375->mclk);
}
if (!es8375->mclk)
dev_warn(dev, "assuming static mclk\n");
ret = clk_prepare_enable(es8375->mclk);
if (ret) {
dev_err(dev, "unable to enable mclk\n");
return ret;
}
#endif
return 0;
}
static u32 cur_reg = 0;
static ssize_t es8375_show(struct device *dev, struct device_attribute *attr, char *_buf)
{
int ret;
ret = sprintf(_buf, "%s(): get 0x%04x=0x%04x\n", __func__, cur_reg,
snd_soc_component_read(es8375_RegMap_codec, cur_reg));
return ret;
}
static ssize_t es8375_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int val = 0, flag = 0;
u8 i = 0, reg, num, value_w, value_r;
val = simple_strtol(buf, NULL, 16);
flag = (val >> 16) & 0xFF;
if (flag) {
reg = (val >> 8) & 0xFF;
value_w = val & 0xFF;
printk("\nWrite: start REG:0x%02x,val:0x%02x,count:0x%02x\n",
reg, value_w, flag);
while (flag--) {
snd_soc_component_write(es8375_RegMap_codec, reg, value_w);
printk("Write 0x%02x to REG:0x%02x\n", value_w, reg);
reg++;
}
} else {
reg = (val >> 8) & 0xFF;
num = val & 0xff;
printk("\nRead: start REG:0x%02x,count:0x%02x\n", reg, num);
do {
value_r = 0;
value_r = snd_soc_component_read(es8375_RegMap_codec, reg);
printk("REG[0x%02x]: 0x%02x; \n", reg, value_r);
reg++;
i++;
} while (i < num);
}
return count;
}
static DEVICE_ATTR(es8375, 0664, es8375_show, es8375_store);
static struct attribute *es8375_debug_attrs[] = {
&dev_attr_es8375.attr,
NULL,
};
static struct attribute_group es8375_debug_attr_group = {
.name = "es8375_debug",
.attrs = es8375_debug_attrs,
};
static int es8375_i2c_probe(struct i2c_client *i2c_client)
{
struct es8375_priv *es8375;
struct device *dev = &i2c_client->dev;
int ret = -1;
#ifndef SPACEMIT_CONFIG_CODEC_ES8375
unsigned int val;
#endif
printk("Enter into %s\n", __func__);
es8375 = devm_kzalloc(&i2c_client->dev, sizeof(*es8375), GFP_KERNEL);
if (!es8375)
return -ENOMEM;
es8375->regmap = devm_regmap_init_i2c(i2c_client,
&es8375_regmap_config);
if (IS_ERR(es8375->regmap)) {
dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
return PTR_ERR(es8375->regmap);
}
i2c_set_clientdata(i2c_client, es8375);
#ifndef SPACEMIT_CONFIG_CODEC_ES8375
/* verify that we have an es8375 */
ret = regmap_read(es8375->regmap, ES8375_CHIP_ID1_0xFD, &val);
if (ret < 0) {
dev_err(&i2c_client->dev, "failed to read i2c at addr %X\n",
i2c_client->addr);
return ret;
}
/* The ES8375_CHIP_ID1 should be 0x83 */
if (val != 0x83) {
dev_err(&i2c_client->dev, "device at addr %X is not an es8375\n",
i2c_client->addr);
return -ENODEV;
}
ret = regmap_read(es8375->regmap, ES8375_CHIP_ID0_0xFE, &val);
/* The ES8375_CHIP_ID0 should be 0x75 */
if (val != 0x75) {
dev_err(&i2c_client->dev, "device at addr %X is not an es8375\n",
i2c_client->addr);
return -ENODEV;
}
#endif
ret = es8375_read_device_properities(dev, es8375);
if (ret != 0) {
dev_err(&i2c_client->dev, "get an error from dts info %X\n", ret);
return ret;
}
//es8375_set_gpio(es8375, PA_SHUTDOWN);
ret = sysfs_create_group(&i2c_client->dev.kobj, &es8375_debug_attr_group);
if (ret) {
pr_err("failed to create attr group\n");
}
return devm_snd_soc_register_component(&i2c_client->dev, &es8375_codec_driver,
&es8375_dai, 1);
}
static void es8375_i2c_shutdown(struct i2c_client *i2c)
{
struct es8375_priv *es8375;
es8375 = i2c_get_clientdata(i2c);
//es8375_set_gpio(es8375, PA_SHUTDOWN);
}
static const struct i2c_device_id es8375_id[] = {
{ "es8375" },
{ }
};
MODULE_DEVICE_TABLE(i2c, es8375_id);
#ifdef CONFIG_ACPI
static const struct acpi_device_id es8375_acpi_match[] = {
{"ESSX8375", 0},
{},
};
MODULE_DEVICE_TABLE(acpi, es8375_acpi_match);
#endif
#ifdef CONFIG_OF
static const struct of_device_id es8375_of_match[] = {
{.compatible = "everest,es8375",},
{}
};
MODULE_DEVICE_TABLE(of, es8375_of_match);
#endif
static struct i2c_driver es8375_i2c_driver = {
.driver = {
.name = "es8375",
.owner = THIS_MODULE,
.of_match_table = of_match_ptr(es8375_of_match),
.acpi_match_table = ACPI_PTR(es8375_acpi_match),
},
.shutdown = es8375_i2c_shutdown,
.probe = es8375_i2c_probe,
.id_table = es8375_id,
};
module_i2c_driver(es8375_i2c_driver);
MODULE_DESCRIPTION("ASoC ES8375 driver");
MODULE_AUTHOR("Dulianghan <Dulianghan@everest-semi.com>");
MODULE_LICENSE("GPL");

116
sound/soc/codecs/es8375.h Executable file
View File

@@ -0,0 +1,116 @@
#ifndef _ES8375_H
#define _ES8375_H
#include <linux/bitops.h>
// Registors
#define ES8375_RESET1_0x00 0x00
#define ES8375_MCLK_SEL_0x01 0x01
#define ES8375_CLK_MGR_0x02 0x02
#define ES8375_CLK_MGR_0x03 0x03
#define ES8375_CLK_MGR_0x04 0x04
#define ES8375_CLK_MGR_0x05 0x05
#define ES8375_CLK_MGR_0x06 0x06
#define ES8375_CLK_MGR_0x07 0x07
#define ES8375_CLK_MGR_0x08 0x08
#define ES8375_CLK_MGR_0x09 0x09
#define ES8375_CLK_MGR_0x0A 0x0A
#define ES8375_CLK_MGR_0x0B 0x0B
#define ES8375_CLK_MGR_0x0C 0x0C
#define ES8375_DIV_SPKCLK_0x0E 0x0E
#define ES8375_CSM1_0x0F 0x0F
#define ES8375_CSM2_0x10 0x10
#define ES8375_VMID_CHARGE2_T_0x11 0x11
#define ES8375_VMID_CHARGE3_T_0x12 0x12
#define ES8375_SDP_0x15 0x15
#define ES8375_SDP2_0x16 0x16
#define ES8375_ADC1_0x17 0x17
#define ES8375_ADC2_0x18 0x18
#define ES8375_ADC_OSR_GAIN_0x19 0x19
#define ES8375_ADC_VOLUME_0x1A 0x1A
#define ES8375_ADC_AUTOMUTE_0x1B 0x1B
#define ES8375_ADC_AUTOMUTE_ATTN_0x1C 0x1C
#define ES8375_HPF1_0x1D 0x1D
#define ES8375_DAC1_0x1F 0x1F
#define ES8375_DAC2_0x20 0x20
#define ES8375_DAC_VOLUME_0x21 0x21
#define ES8375_DAC_VPPSCALE_0x22 0x22
#define ES8375_DAC_AUTOMUTE1_0x23 0x23
#define ES8375_DAC_AUTOMUTE_0x24 0x24
#define ES8375_DAC_CAL_0x25 0x25
#define ES8375_DAC_OTP_0x27 0x27
#define ES8375_ANALOG_SPK1_0x28 0x28
#define ES8375_ANALOG_SPK2_0x29 0x29
#define ES8375_VMID_SEL_0x2D 0x2D
#define ES8375_ANALOG_0x2E 0x2E
#define ES8375_ANALOG_0x32 0x32
#define ES8375_ANALOG_0x37 0x37
#define ES8375_ADC2DAC_CLKTRI 0xF8
#define ES8375_SYS_CTRL2_0xF9 0xF9
#define ES8375_FLAGS2_0xFB 0xFB
#define ES8375_SPK_OFFSET_0xFC 0xFC
#define ES8375_CHIP_ID1_0xFD 0xFD
#define ES8375_CHIP_ID0_0xFE 0xFE
#define ES8375_CHIP_VERSION_0xFF 0xFF
// Bit Shifts
#define ADC_OSR_GAIN_SHIFT_0 0
#define ADC_RAMPRATE_SHIFT_0 0
#define ADC_VOLUME_SHIFT_0 0
#define ADC_AUTOMUTE_NG_SHIFT_0 0
#define ADC_AUTOMUTE_ATTN_SHIFT_0 0
#define DAC_RAMPRATE_SHIFT_0 0
#define DAC_VOLUME_SHIFT_0 0
#define DAC_VPPSCALE_SHIFT_0 0
#define DAC_AUTOMUTE_NG_SHIFT_0 0
#define DAC_AUTOMUTE_ATTN_SHIFT_0 0
#define DMIC_GAIN_SHIFT_2 2
#define ADC_AUTOMUTE_WS_SHIFT_3 3
#define DMIC_POL_SHIFT_4 4
#define DAC_RAMCLR_SHIFT_4 4
#define ES8375_EN_MODL_SHIFT_4 4
#define ADC_RAMCLR_SHIFT_5 5
#define ADC_HPF_SHIFT_5 5
#define DAC_INV_SHIFT_5 5
#define DAC_AUTOMUTE_WS_SHIFT_5 5
#define ES8375_EN_PGAL_SHIFT_5 5
#define ES8375_ADC_P2S_MUTE_SHIFT_5 5
#define ADC_INV_SHIFT_6 6
#define DAC_DEMMUTE_SHIFT_6 6
#define ES8375_DAC_S2P_MUTE_SHIFT_6 6
#define ADC_SRC_SHIFT_7 7
#define ADC_AUTOMUTE_SHIFT_7 7
#define DAC_DSMMUTE_SHIFT_7 7
#define DAC_AUTOMUTE_EN_SHIFT_7 7
// Function values
#define ES8375_ADC_OSR_GAIN_MAX 0x3F
#define ES8375_ADC_AUTOMUTE_ATTN_MAX 0x1F
#define ES8375_ADC_VOLUME_MAX 0xFF
#define ES8375_DAC_VOLUME_MAX 0xFF
#define ES8375_DAC_VPPSCALE_MAX 0x3F
#define ES8375_DAC_AUTOMUTE_ATTN_MAX 0x17 // 0 ~ 23 每级之间的增益为4dB，24~31 是 reversed，所以有增益的部分就到 0x17（23）
#define ES8375_REG_MAX 0xFF
// Properties
#define ES8375_3V3 1
#define ES8375_1V8 0
#define ES8375_AVDD ES8375_3V3
#define ES8375_DVDD ES8375_3V3
#define ES8375_MCLK_PIN 0
#define ES8375_BCLK_PIN 1
#define ES8375_MCLK_SOURCE ES8375_MCLK_PIN
#define DMIC_POSITIVE_EDGE 0 // Low = Left channel ; High = Right channel
#define DMIC_NEGATIVE_EDGE 1 // Low = Right channel ; High = Left channel
#define DMIC_POL DMIC_POSITIVE_EDGE
#define PA_SHUTDOWN 0
#define PA_ENABLE 1
#endif

329
sound/soc/spacemit/spacemit-snd-i2s.c
View File

@@ -22,8 +22,6 @@
#include <sound/dmaengine_pcm.h>
#include "spacemit-snd-i2s.h"
static int i2s_sspa_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt);
//APB Clock/Reset Control Register
#define APB_CLK_BASE 0xD4015000
#define APB_SSP0_CLK_RST 0x80
@@ -102,10 +100,73 @@ static u32 i2s_sspa_read_reg(struct ssp_device *sspa, u32 reg)
static int i2s_sspa_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct sspa_priv *priv = snd_soc_dai_get_drvdata(dai);
pm_runtime_get_sync(&priv->i2splatdev->dev);
i2s_sspa_set_dai_fmt(dai, SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_I2S);
struct sspa_priv *sspa_priv = snd_soc_dai_get_drvdata(dai);
struct ssp_device *sspa = sspa_priv->sspa;
unsigned int ssp_top_cfg = 0, ssp_fifo_cfg = 0, ssp_int_en_cfg = 0;
unsigned int ssp_to_cfg = 0, ssp_psp_cfg = 0, ssp_net_work_ctrl = 0;
int dai_id = dai->id;
pm_runtime_get_sync(&sspa_priv->i2splatdev->dev);
if ((sspa_priv->dai_id_pre == dai_id) & (i2s_sspa_read_reg(sspa, PSP_CTRL)))
return 0;
ssp_top_cfg = TOP_TRAIL_DMA | DW_32BYTE | TOP_SFRMDIR_M | TOP_SCLKDIR_M | TOP_FRF_PSP;
ssp_fifo_cfg = FIFO_RSRE | FIFO_TSRE | FIFO_RX_THRES_15 | FIFO_TX_THRES_15;
if ((i2s_sspa_read_reg(sspa, TOP_CTRL) & TOP_SSE)) {
pr_debug("no need to change hardware dai format: stream is in use\n");
return 0;
}
switch (sspa_priv->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
ssp_top_cfg |= TOP_SFRMDIR_M;
ssp_top_cfg |= TOP_SCLKDIR_M;
pr_debug("%s,%d------------SND_SOC_DAIFMT_CBP_CFP\n", __func__, __LINE__);
break;
case SND_SOC_DAIFMT_CBC_CFC:
pr_debug("%s,%d------------SND_SOC_DAIFMT_CBC_CFC\n", __func__, __LINE__);
break;
default:
return -EINVAL;
}
switch (sspa_priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
pr_debug("%s,%d------------mode i2s\n", __func__, __LINE__);
ssp_top_cfg |= TOP_FRF_PSP;
ssp_psp_cfg = (0x10<<12) | (0x1<<3) | PSP_SFRMP;
break;
case SND_SOC_DAIFMT_DSP_B:
pr_debug("%s,%d------------mode B\n", __func__, __LINE__);
ssp_top_cfg |= TOP_FRF_PSP;
ssp_psp_cfg = (0x1<<12) | PSP_SFRMP;
break;
case SND_SOC_DAIFMT_DSP_A:
pr_debug("%s,%d------------mode A\n", __func__, __LINE__);
ssp_top_cfg |= TOP_FRF_PSP;
ssp_psp_cfg = (0x1<<12) | (0x1<<3) | PSP_SFRMP;
break;
default:
pr_debug("%s, unexpected format type\n", __func__);
return -EINVAL;
}
i2s_sspa_write_reg(sspa, TOP_CTRL, ssp_top_cfg);
i2s_sspa_write_reg(sspa, PSP_CTRL, ssp_psp_cfg);
i2s_sspa_write_reg(sspa, INT_EN, ssp_int_en_cfg);
i2s_sspa_write_reg(sspa, TO, ssp_to_cfg);
i2s_sspa_write_reg(sspa, FIFO_CTRL, ssp_fifo_cfg);
i2s_sspa_write_reg(sspa, NET_WORK_CTRL, ssp_net_work_ctrl);
pr_debug("TOP_CTRL=0x%x,\n PSP_CTRL=0x%x,\n INT_EN=0x%x,\n TO=0x%x,\n FIFO_CTRL=0x%x,\n,NET_WORK_CTRL=0x%x",
i2s_sspa_read_reg(sspa, TOP_CTRL),
i2s_sspa_read_reg(sspa, PSP_CTRL),
i2s_sspa_read_reg(sspa, INT_EN),
i2s_sspa_read_reg(sspa, TO),
i2s_sspa_read_reg(sspa, FIFO_CTRL),
i2s_sspa_read_reg(sspa, NET_WORK_CTRL));
return 0;
}
@@ -147,61 +208,33 @@ static int i2s_sspa_set_dai_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
{
struct sspa_priv *sspa_priv = snd_soc_dai_get_drvdata(cpu_dai);
struct ssp_device *sspa = sspa_priv->sspa;
unsigned int ssp_top_cfg=0, ssp_fifo_cfg=0, ssp_int_en_cfg=0,ssp_to_cfg=0, ssp_psp_cfg=0, ssp_net_work_ctrl=0;
int dai_id = cpu_dai->id;
pr_debug("%s, fmt=0x%x, dai_id=0x%x\n", __FUNCTION__, fmt, dai_id);
if ((sspa_priv->dai_fmt == fmt) & (sspa_priv->dai_id_pre == dai_id) & (i2s_sspa_read_reg(sspa, PSP_CTRL)))
return 0;
ssp_top_cfg = TOP_TRAIL_DMA | DW_32BYTE | TOP_SFRMDIR_M | TOP_SCLKDIR_M | TOP_FRF_PSP;
ssp_fifo_cfg = FIFO_RSRE | FIFO_TSRE | FIFO_RX_THRES_15 | FIFO_TX_THRES_15;
if ((i2s_sspa_read_reg(sspa, TOP_CTRL) & TOP_SSE)) {
pr_debug("no need to change hardware dai format: stream is in use\n");
return 0;
}
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
ssp_top_cfg |= TOP_SFRMDIR_M;
ssp_top_cfg |= TOP_SCLKDIR_M;
break;
case SND_SOC_DAIFMT_CBM_CFM:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
ssp_top_cfg |= TOP_FRF_PSP;
ssp_psp_cfg = (0x10<<12) | (0x1<<3) | PSP_SFRMP;
break;
default:
return -EINVAL;
}
i2s_sspa_write_reg(sspa, TOP_CTRL, ssp_top_cfg);
i2s_sspa_write_reg(sspa, PSP_CTRL, ssp_psp_cfg);
i2s_sspa_write_reg(sspa, INT_EN, ssp_int_en_cfg);
i2s_sspa_write_reg(sspa, TO, ssp_to_cfg);
i2s_sspa_write_reg(sspa, FIFO_CTRL, ssp_fifo_cfg);
i2s_sspa_write_reg(sspa, NET_WORK_CTRL, ssp_net_work_ctrl);
pr_debug("TOP_CTRL=0x%x,\n PSP_CTRL=0x%x,\n INT_EN=0x%x,\n TO=0x%x,\n FIFO_CTRL=0x%x,\n,NET_WORK_CTRL=0x%x",
i2s_sspa_read_reg(sspa, TOP_CTRL),
i2s_sspa_read_reg(sspa, PSP_CTRL),
i2s_sspa_read_reg(sspa, INT_EN),
i2s_sspa_read_reg(sspa, TO),
i2s_sspa_read_reg(sspa, FIFO_CTRL),
i2s_sspa_read_reg(sspa, NET_WORK_CTRL));
sspa_priv->dai_fmt = fmt;
sspa_priv->dai_id_pre = dai_id;
switch (sspa_priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
pr_debug("%s,%d------------mode i2s\n", __func__, __LINE__);
cpu_dai->driver->playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
cpu_dai->driver->capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
break;
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
pr_debug("%s,%d------------mode A/B\n", __func__, __LINE__);
cpu_dai->driver->playback.channels_min = 1;
cpu_dai->driver->playback.channels_max = 1;
cpu_dai->driver->capture.channels_min = 1;
cpu_dai->driver->capture.channels_max = 1;
cpu_dai->driver->playback.formats = SNDRV_PCM_FMTBIT_S32_LE;
cpu_dai->driver->capture.formats = SNDRV_PCM_FMTBIT_S32_LE;
break;
default:
pr_debug("%s, unexpected format type\n", __func__);
return -EINVAL;
}
return 0;
}
@@ -214,36 +247,89 @@ static int i2s_sspa_hw_params(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, dai->id);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct sspa_priv *sspa_priv = snd_soc_dai_get_drvdata(dai);
struct ssp_device *sspa = sspa_priv->sspa;
struct snd_dmaengine_dai_dma_data *dma_params;
unsigned int val, target;
dma_params = &sspa_priv->dma_params[substream->stream];
dma_params->addr = (sspa->phys_base + DATAR);
dma_params->maxburst = 32;
dma_params->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
snd_soc_dai_set_dma_data(cpu_dai, substream, dma_params);
unsigned int ssp_top_cfg = 0, data_width = 0, data_bits = 0;
if (sspa_priv->running_cnt)
return 0;
dma_params = &sspa_priv->dma_params[substream->stream];
dma_params->addr = (sspa->phys_base + DATAR);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S8:
data_bits = 8;
data_width = DW_8BYTE;
dma_params->maxburst = 8;
dma_params->addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
break;
case SNDRV_PCM_FORMAT_S16_LE:
data_bits = 16;
data_width = DW_16BYTE;
dma_params->maxburst = 16;
dma_params->addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
if ((sspa_priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S) {
data_width = DW_32BYTE;
dma_params->maxburst = 32;
dma_params->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
}
break;
case SNDRV_PCM_FORMAT_S32_LE:
data_bits = 32;
data_width = DW_32BYTE;
dma_params->maxburst = 32;
dma_params->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
break;
default:
pr_debug("%s, unexpected data width type\n", __func__);
return -EINVAL;
}
ssp_top_cfg = i2s_sspa_read_reg(sspa, TOP_CTRL);
ssp_top_cfg &= ~DW_32BYTE;
ssp_top_cfg |= data_width;
i2s_sspa_write_reg(sspa, TOP_CTRL, ssp_top_cfg);
snd_soc_dai_set_dma_data(cpu_dai, substream, dma_params);
sspa_priv->mclk_fs = sspa_priv->sysclk / (params_rate(params));
switch (sspa_priv->mclk_fs) {
case 64:
target = SYSCLK_BASE_156M | 0 << 27| 4 << 15 | 200; //64fs
target = SYSCLK_BASE_156M | 4 << 15 | 200; //64fs
break;
case 128:
target = SYSCLK_BASE_156M | 1 << 27| 8 << 15 | 200; //128fs
target = SYSCLK_BASE_156M | 8 << 15 | 200; //128fs
break;
case 256:
target = SYSCLK_BASE_156M | 3 << 27| 16 << 15 | 200; //256fs
target = SYSCLK_BASE_156M | 16 << 15 | 200; //256fs
break;
default:
target = SYSCLK_BASE_156M | 3 << 27| 16 << 15 | 200; //256fs
target = SYSCLK_BASE_156M | 16 << 15 | 200; //256fs
break;
}
switch (sspa_priv->sysclk / (params_channels(params) * params_rate(params) * data_bits)) {
case 2:
target |= 0 << 27;
break;
case 4:
target |= 1 << 27;
break;
case 6:
target |= 2 << 27;
break;
case 8:
target |= 3 << 27;
break;
default:
target |= 3 << 27;
break;
}
val = __raw_readl(sspa->pmumain + ISCCR1);
val = val & ~0x5FFFFFFF;
__raw_writel(val | target, sspa->pmumain + ISCCR1);
@@ -263,29 +349,32 @@ static int i2s_sspa_trigger(struct snd_pcm_substream *substream, int cmd,
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ssp_top_cfg = i2s_sspa_read_reg(sspa, TOP_CTRL);
pr_debug("TOP_CTRL:0x%x", ssp_top_cfg);
ssp_top_cfg |= TOP_SSE;
i2s_sspa_write_reg(sspa, TOP_CTRL, ssp_top_cfg); //SSP_enable
if (sspa_priv->running_cnt == 0) {
ssp_top_cfg = i2s_sspa_read_reg(sspa, TOP_CTRL);
pr_debug("TOP_CTRL:0x%x", ssp_top_cfg);
ssp_top_cfg |= TOP_SSE;
i2s_sspa_write_reg(sspa, TOP_CTRL, ssp_top_cfg); //SSP_enable
}
sspa_priv->running_cnt++;
pr_debug("triger::TOP_CTRL=0x%x,\n PSP_CTRL=0x%x,\n INT_EN=0x%x,\n TO=0x%x,\n FIFO_CTRL=0x%x,\n",
i2s_sspa_read_reg(sspa, TOP_CTRL), i2s_sspa_read_reg(sspa, PSP_CTRL),
i2s_sspa_read_reg(sspa, INT_EN),
i2s_sspa_read_reg(sspa, TO),
i2s_sspa_read_reg(sspa, FIFO_CTRL));
i2s_sspa_read_reg(sspa, TOP_CTRL), i2s_sspa_read_reg(sspa, PSP_CTRL),
i2s_sspa_read_reg(sspa, INT_EN),
i2s_sspa_read_reg(sspa, TO),
i2s_sspa_read_reg(sspa, FIFO_CTRL));
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (sspa_priv->running_cnt > 0)
sspa_priv->running_cnt--;
if (sspa_priv->running_cnt == 0 ) {
ssp_top_cfg = i2s_sspa_read_reg(sspa, TOP_CTRL);
ssp_top_cfg &= (~TOP_SSE);
i2s_sspa_write_reg(sspa, TOP_CTRL, ssp_top_cfg);
pr_debug("TOP_CTRL=0x%x, dai->id=%d \n", i2s_sspa_read_reg(sspa, TOP_CTRL), dai->id);
}
if (sspa_priv->running_cnt > 0)
sspa_priv->running_cnt--;
if (sspa_priv->running_cnt == 0) {
ssp_top_cfg = i2s_sspa_read_reg(sspa, TOP_CTRL);
ssp_top_cfg &= (~TOP_SSE);
i2s_sspa_write_reg(sspa, TOP_CTRL, ssp_top_cfg);
pr_debug("TOP_CTRL=0x%x, dai->id=%d \n", i2s_sspa_read_reg(sspa, TOP_CTRL), dai->id);
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
pr_debug("%s ignore playback tx\n", __FUNCTION__);
}
@@ -342,41 +431,40 @@ static const struct snd_soc_dai_ops i2s_sspa_dai_ops = {
.set_fmt = i2s_sspa_set_dai_fmt,
};
static struct snd_soc_dai_driver i2s_sspa_dai[] = {
{
.name = "i2s-dai0",
.id = 0,
.playback = {
.channels_min = 1,
.channels_max = 128,
.rates = I2S_SSPA_RATES,
.formats = I2S_SSPA_FORMATS,
},
.capture = {
.channels_min = 1,
.channels_max = 2,
.rates = I2S_SSPA_RATES,
.formats = I2S_SSPA_FORMATS,
},
.ops = &i2s_sspa_dai_ops,
static struct snd_soc_dai_driver i2s0_sspa_dai = {
.name = "i2s0-dai",
.id = 0,
.playback = {
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_48000,
.formats = I2S_SSPA_FORMATS,
},
{
.name = "i2s-dai1",
.id = 1,
.playback = {
.channels_min = 1,
.channels_max = 128,
.rates = I2S_SSPA_RATES,
.formats = I2S_SSPA_FORMATS,
},
.capture = {
.channels_min = 1,
.channels_max = 2,
.rates = I2S_SSPA_RATES,
.formats = I2S_SSPA_FORMATS,
},
.ops = &i2s_sspa_dai_ops,
}
.capture = {
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_48000,
.formats = I2S_SSPA_FORMATS,
},
.ops = &i2s_sspa_dai_ops,
};
static struct snd_soc_dai_driver i2s1_sspa_dai = {
.name = "i2s1-dai",
.id = 1,
.playback = {
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_48000,
.formats = I2S_SSPA_FORMATS,
},
.capture = {
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_48000,
.formats = I2S_SSPA_FORMATS,
},
.ops = &i2s_sspa_dai_ops,
};
static void i2s_sspa_init(struct sspa_priv *priv)
@@ -452,9 +540,9 @@ static int asoc_i2s_sspa_probe(struct platform_device *pdev)
{
struct sspa_priv *priv;
struct resource *res;
u8 dai_id = 0;
struct snd_soc_dai_driver *dai;
pr_debug("enter %s\n", __FUNCTION__);
pr_debug("%s enter: dev name %s\n", __func__, dev_name(&pdev->dev));
priv = devm_kzalloc(&pdev->dev,
sizeof(struct sspa_priv), GFP_KERNEL);
if (!priv) {
@@ -485,6 +573,8 @@ static int asoc_i2s_sspa_probe(struct platform_device *pdev)
return PTR_ERR(priv->sspa->mmio_base);
}
priv->sspa->phys_base = res->start;
if ((priv->sspa->apb_clk_base = ioremap(APB_CLK_BASE, 0x100)) == NULL) {
pr_err("sspa ioremap err\n");
return -1;
@@ -505,12 +595,11 @@ static int asoc_i2s_sspa_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, priv);
pr_debug("exit %s\n", __FUNCTION__);
if (of_device_is_compatible(pdev->dev.of_node, "spacemit,spacemit-i2s0")) {
dai_id = 0;
dai = &i2s0_sspa_dai;
} else {
dai_id = 1;
dai = &i2s1_sspa_dai;
}
return devm_snd_soc_register_component(&pdev->dev, &i2s_sspa_component,
&i2s_sspa_dai[dai_id], 1);
return devm_snd_soc_register_component(&pdev->dev, &i2s_sspa_component, dai, 1);
}
static int asoc_i2s_sspa_remove(struct platform_device *pdev)

4
sound/soc/spacemit/spacemit-snd-pcm-dma.c
View File

@@ -399,11 +399,11 @@ static int spacemit_snd_dma_init(struct device *paraent, struct spacemit_snd_soc
static const struct snd_pcm_hardware spacemit_snd_pcm_hardware = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BATCH,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = SNDRV_PCM_RATE_48000,
.rate_max = SNDRV_PCM_RATE_48000,
.channels_min = 2,
.channels_min = 1,
.channels_max = 2,
.buffer_bytes_max = I2S_PERIOD_SIZE * I2S_PERIOD_COUNT * 4,
.period_bytes_min = I2S_PERIOD_SIZE * 4,

30
tools/perf/pmu-events/arch/riscv/spacemit/x60/cache.json
View File

@@ -89,25 +89,25 @@
"EventCode": "175",
"BriefDescription": "L1 D-cache prefetch hits"
},
{
"EventName": "l2_access",
"EventCode": "184",
"BriefDescription": "L2 cache accesses"
},
{
"EventName": "l2_miss",
"EventCode": "185",
"BriefDescription": "L2 cache misses"
},
{
"EventName": "l2_load_access",
"EventCode": "186",
"EventCode": "184",
"BriefDescription": "L2 cache load accesses"
},
{
"EventName": "l2_load_stall",
"EventName": "l2_load_miss",
"EventCode": "185",
"BriefDescription": "L2 cache load misses"
},
{
"EventName": "l2_ar_channel_request",
"EventCode": "186",
"BriefDescription": "Total number of L2 cache AR channel requests, including read accesses, non-coherent read accesses and DVM accesses"
},
{
"EventName": "l2_ar_channel_stall_cycle",
"EventCode": "187",
"BriefDescription": "L2 cache load stalls"
"BriefDescription": "L2 cache AR channel stall cycles"
},
{
"EventName": "l2_store_access",
@@ -115,8 +115,8 @@
"BriefDescription": "L2 cache store accesses"
},
{
"EventName": "l2_store_stall",
"EventName": "l2_aw_channel_stall_cycle",
"EventCode": "189",
"BriefDescription": "L2 cache store stalls"
"BriefDescription": "L2 cache AW channel stall cycles"
}
]