Merge remote-tracking branch 'origin/k1-dev' into k1-release

Change-Id: I9cb47755d031341ba9d219190baa15e25bf80fd9
This commit is contained in:
zhangmeng
2025-07-03 20:28:36 +08:00
14 changed files with 1340 additions and 120 deletions

View File

@@ -8,5 +8,5 @@ dtb-$(CONFIG_SOC_SPACEMIT_K1X) += k1-x_fpga.dtb k1-x_fpga_1x4.dtb k1-x_fpga_2x2.
k1-x_baton-camera.dtb k1-x_FusionOne.dtb k1-x_InnoBoard-Pi.dtb \
k1-x_ZT001H.dtb k1-x_uav.dtb k1-x_MUSE-Paper2.dtb \
k1-x_bit-brick.dtb k1-x_LX-V10.dtb k1-x_NetBridge-C1.dtb \
k1-x_MUSE-Pi-Pro.dtb k1-x_som.dtb
k1-x_MUSE-Pi-Pro.dtb k1-x_som.dtb k1-x_ZT_RVOH007.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

View File

@@ -426,39 +426,45 @@
ranges;
/* rcpu's heap */
rcpu_mem_heap: rcpu_mem_heap@30000000 {
reg = <0x0 0x30000000 0x0 0x200000>;
rcpu_mem_heap: rcpu_mem_heap@100000 {
reg = <0x0 0x100000 0x0 0x200000>;
da_base = <0x30000000>;
no-map;
};
/* vring0 */
vdev0vring0: vdev0vring0@30200000 {
reg = <0x0 0x30200000 0x0 0x3000>;
vdev0vring0: vdev0vring0@300000 {
reg = <0x0 0x300000 0x0 0x3000>;
da_base = <0x30200000>;
no-map;
};
/* vring1 */
vdev0vring1: vdev0vring1@30203000 {
reg = <0x0 0x30203000 0x0 0x3000>;
vdev0vring1: vdev0vring1@303000 {
reg = <0x0 0x303000 0x0 0x3000>;
da_base = <0x30203000>;
no-map;
};
/* share memory buffer */
vdev0buffer: vdev0buffer@30206000 {
vdev0buffer: vdev0buffer@306000 {
compatible = "shared-dma-pool";
reg = <0x0 0x30206000 0x0 0xf6000>;
reg = <0x0 0x306000 0x0 0xf6000>;
da_base = <0x30206000>;
no-map;
};
/* the resource table */
rsc_table: rsc_table@302fc000 {
reg = <0x0 0x302fc000 0x0 0x4000>;
rsc_table: rsc_table@3fc000 {
reg = <0x0 0x3fc000 0x0 0x4000>;
da_base = <0x302fc000>;
no-map;
};
/* used for rcpu code & data & bss space */
rcpu_mem_0: rcpu_mem_0@30300000 {
reg = <0x0 0x30300000 0x0 0x200000>;
rcpu_mem_0: rcpu_mem_0@400000 {
reg = <0x0 0x400000 0x0 0x200000>;
da_base = <0x30300000>;
no-map;
};
};
@@ -559,6 +565,16 @@
status = "okay";
};
/* for rcpu vqueue buffer . */
dram_range8: dram_range@8 {
compatible = "spacemit-dram-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges = <0x0 0x30200000 0x0 0x300000 0x0 0xfc000>;
#interconnect-cells = <0>;
status = "okay";
};
clint0: clint@e4000000 {
compatible = "riscv,clint0";
interrupts-extended = <
@@ -1022,7 +1038,7 @@
compatible = "spacemit,k1-x-rproc";
reg = <0 0xc088c000 0 0x1000>,
<0 0xc0880000 0 0x200>;
ddr-remap-base = <0x30000000>;
ddr-remap-base = <0x100000>;
esos-entry-point = <0x30300114>;
clocks = <&ccu CLK_AUDIO>, <&ccu CLK_AUDIO_APB>;
clock-names = "core", "apb";
@@ -1033,6 +1049,8 @@
mbox-names = "vq0", "vq1";
firmware-name = "esos.elf";
power-domains = <&power K1X_PMU_AUD_PWR_DOMAIN>;
interconnects = <&dram_range8>;
interconnect-names = "dma-mem";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};
@@ -2116,7 +2134,7 @@
reg = <0x0 0xc0b10000 0x0 0x800>,
<0x0 0xd4282910 0x0 0x400>;
reg-names = "puphy", "phy_sel";
resets = <&reset RESET_PCIE0>;
resets = <&reset RESET_COMBO_PHY>;
reset-names = "phy_rst";
#phy-cells = <1>;
status = "disabled";

View File

@@ -169,7 +169,7 @@
led1 {
label = "sys-led";
gpios = <&gpio 96 0>;
linux,default-trigger = "none";
linux,default-trigger = "heartbeat";
default-state = "on";
status = "okay";
};

File diff suppressed because it is too large Load Diff

View File

@@ -0,0 +1,155 @@
// SPDX-License-Identifier: GPL-2.0
/ { lcds: lcds {
lcd_hxdm101_mipi: lcd_hxdm101_mipi {
dsi-work-mode = <1>; /* video burst mode*/
dsi-lane-number = <4>;
dsi-color-format = "rgb888";
width-mm = <135>;
height-mm = <216>;
use-dcs-write;
/*mipi info*/
height = <1920>;
width = <1200>;
hfp = <80>;
hbp = <50>;
hsync = <10>;
vfp = <60>;
vbp = <25>;
vsync = <4>;
fps = <60>;
work-mode = <0>;
rgb-mode = <3>;
lane-number = <4>;
phy-bit-clock = <1000000000>;
phy-esc-clock = <76800000>;
split-enable = <0>;
eotp-enable = <0>;
burst-mode = <2>;
esd-check-enable = <0>;
/* DSI_CMD, DSI_MODE, timeout, len, cmd */
initial-command = [
39 01 00 02 B0 00
39 01 00 02 B2 50
39 01 00 02 B0 01
39 01 00 02 C0 00
39 01 00 02 C1 17
39 01 00 02 C2 01
39 01 00 02 C3 26
39 01 00 02 C4 00
39 01 00 02 C5 23
39 01 00 02 C6 11
39 01 00 02 C7 05
39 01 00 02 C8 07
39 01 00 02 C9 09
39 01 00 02 CA 0B
39 01 00 02 CB 1B
39 01 00 02 CC 1D
39 01 00 02 CD 1F
39 01 00 02 CE 21
39 01 00 02 CF 0F
39 01 00 02 D0 0D
39 01 00 02 D1 00
39 01 00 02 D2 00
39 01 00 02 D3 00
39 01 00 02 D4 00
39 01 00 02 D5 18
39 01 00 02 D6 02
39 01 00 02 D7 26
39 01 00 02 D8 00
39 01 00 02 D9 23
39 01 00 02 DA 11
39 01 00 02 DB 06
39 01 00 02 DC 08
39 01 00 02 DD 0A
39 01 00 02 DE 0C
39 01 00 02 DF 1C
39 01 00 02 E0 1E
39 01 00 02 E1 20
39 01 00 02 E2 22
39 01 00 02 E3 10
39 01 00 02 E4 0E
39 01 00 02 E5 00
39 01 00 02 E6 00
39 01 00 02 E7 00
39 01 00 02 B0 03
39 01 00 02 BE 04
39 01 00 02 B9 40
39 01 00 02 CC 88
39 01 00 02 C8 0C
39 01 00 02 C9 07
39 01 00 02 CD 01
39 01 00 02 CA 40
39 01 00 02 CE 1A
39 01 00 02 CF 60
39 01 00 02 D2 08
39 01 00 02 D3 08
39 01 00 02 DB 01
39 01 00 02 D9 06
39 01 00 02 D4 00
39 01 00 02 D5 01
39 01 00 02 D6 04
39 01 00 02 D7 03
39 01 00 02 C2 00
39 01 00 02 C3 0E
39 01 00 02 C4 00
39 01 00 02 C5 0E
39 01 00 02 DD 00
39 01 00 02 DE 0E
39 01 00 02 E6 00
39 01 00 02 E7 0E
39 01 00 02 C2 00
39 01 00 02 C3 0E
39 01 00 02 C4 00
39 01 00 02 C5 0E
39 01 00 02 DD 00
39 01 00 02 DE 0E
39 01 00 02 E6 00
39 01 00 02 E7 0E
39 01 00 02 B0 06
39 01 00 02 C0 A5
39 01 00 02 D5 1C
39 01 00 02 C0 00
39 01 00 02 B0 00
39 01 00 02 BD 17
39 01 00 02 BA 8F
39 01 00 02 F9 5C
39 01 00 02 C2 14
39 01 00 02 C4 14
39 01 00 02 BF 1A
39 01 00 02 C0 11
39 01 96 01 11
39 01 32 01 29
];
sleep-in-command = [
39 01 78 01 28
39 01 78 01 10
];
sleep-out-command = [
39 01 96 01 11
39 01 32 01 29
];
read-id-command = [
37 01 00 01 05
14 01 00 05 fb fc fd fe ff
];
display-timings {
timing0 {
clock-frequency = <153600000>;
hactive = <1200>;
hfront-porch = <80>;
hback-porch = <50>;
hsync-len = <10>;
vactive = <1920>;
vfront-porch = <60>;
vback-porch = <25>;
vsync-len = <4>;
vsync-active = <1>;
hsync-active = <1>;
};
};
};
};};

View File

@@ -50,6 +50,7 @@ CONFIG_SMP=y
CONFIG_NR_CPUS=8
CONFIG_RISCV_SBI_V01=y
# CONFIG_RISCV_BOOT_SPINWAIT is not set
CONFIG_IMAGE_LOAD_OFFSET=0x600000
CONFIG_SUSPEND_SKIP_SYNC=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_FREQ=y
@@ -1156,7 +1157,7 @@ CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_RUBIN=y
CONFIG_JFFS2_CMODE_NONE=y
CONFIG_UBIFS_FS=m
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_AUTHENTICATION=y
CONFIG_CRAMFS=m
CONFIG_CRAMFS_MTD=y
@@ -1309,8 +1310,6 @@ CONFIG_CRYPTO_SM3_GENERIC=m
CONFIG_CRYPTO_VMAC=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=m
CONFIG_CRYPTO_LZ4=m
CONFIG_CRYPTO_LZ4HC=m

View File

@@ -44,8 +44,8 @@ SYM_CODE_START(_start)
.dword 0
#else
#if __riscv_xlen == 64
/* Image load offset(2MB) from start of RAM */
.dword 0x200000
/* Image load offset(2MB ?) from start of RAM */
.dword CONFIG_IMAGE_LOAD_OFFSET
#else
/* Image load offset(4MB) from start of RAM */
.dword 0x400000

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@@ -71,6 +71,8 @@ struct spacemit_hdmi {
unsigned int tmds_rate;
struct mutex lock;
bool suspended;
bool edid_done;
bool use_no_edid;
struct hdmi_data_info *hdmi_data;
@@ -752,6 +754,14 @@ spacemit_hdmi_connector_detect(struct drm_connector *connector, bool force)
DRM_DEBUG("%s() \n", __func__);
mutex_lock(&hdmi->lock);
if (hdmi->suspended) {
DRM_DEBUG("%s() hdmi is suspended\n", __func__);
mutex_unlock(&hdmi->lock);
return connector_status_disconnected;
}
mutex_unlock(&hdmi->lock);
ret = pm_runtime_get_sync(hdmi->dev);
if (ret < 0) {
DRM_INFO("%s() pm_runtime_get_sync failed\n", __func__);
@@ -976,6 +986,8 @@ static int spacemit_hdmi_bind(struct device *dev, struct device *master,
spacemit_hdmi_reset(hdmi);
hdmi->edid_done = false;
hdmi->suspended = false;
mutex_init(&hdmi->lock);
ret = spacemit_hdmi_register(drm, hdmi);
@@ -1006,6 +1018,8 @@ static void spacemit_hdmi_unbind(struct device *dev, struct device *master,
hdmi->connector.funcs->destroy(&hdmi->connector);
hdmi->encoder.funcs->destroy(&hdmi->encoder);
mutex_destroy(&hdmi->lock);
pm_runtime_put_sync(&pdev->dev);
if (!IS_ERR_OR_NULL(hdmi->hdmi_reset)) {
ret = reset_control_assert(hdmi->hdmi_reset);
@@ -1077,6 +1091,9 @@ static int hdmi_drv_pm_suspend(struct device *dev)
DRM_DEBUG("%s()\n", __func__);
mutex_lock(&hdmi->lock);
hdmi->suspended = true;
value = hdmi_readb(hdmi, SPACEMIT_HDMI_PHY_STATUS);
value &= (~SPACEMIT_HDMI_HPD_IQR_MASK);
value |= SPACEMIT_HDMI_HPD_IQR;
@@ -1084,6 +1101,7 @@ static int hdmi_drv_pm_suspend(struct device *dev)
udelay(5);
clk_disable_unprepare(hdmi->hdmi_mclk);
mutex_unlock(&hdmi->lock);
return 0;
}
@@ -1095,6 +1113,7 @@ static int hdmi_drv_pm_resume(struct device *dev)
DRM_DEBUG("%s()\n", __func__);
mutex_lock(&hdmi->lock);
clk_prepare_enable(hdmi->hdmi_mclk);
udelay(5);
@@ -1102,6 +1121,13 @@ static int hdmi_drv_pm_resume(struct device *dev)
value |= SPACEMIT_HDMI_HPD_IQR_MASK;
hdmi_writeb(hdmi, SPACEMIT_HDMI_PHY_STATUS, value);
hdmi->suspended = false;
mutex_unlock(&hdmi->lock);
if (hdmi_get_plug_in_status(hdmi)) {
drm_helper_hpd_irq_event(hdmi->connector.dev);
}
return 0;
}

View File

@@ -86,7 +86,7 @@ static void emac_configure_rx(struct emac_priv *priv);
static int emac_tx_mem_map(struct emac_priv *priv, struct sk_buff *skb, u32 max_tx_len, u32 frag_num);
static int emac_tx_clean_desc(struct emac_priv *priv);
static int emac_rx_clean_desc(struct emac_priv *priv, int budget);
static void emac_alloc_rx_desc_buffers(struct emac_priv *priv);
static int emac_alloc_rx_desc_buffers(struct emac_priv *priv);
static int emac_phy_connect(struct net_device *dev);
static int emac_sw_init(struct emac_priv *priv);
@@ -433,7 +433,11 @@ static int emac_up(struct emac_priv *priv)
emac_configure_rx(priv);
/* allocate buffers for receive descriptors */
emac_alloc_rx_desc_buffers(priv);
ret = emac_alloc_rx_desc_buffers(priv);
if (ret) {
pr_err("%s alloc rx desc buffers failed\n", __func__);
goto err;
}
if (ndev->phydev)
phy_start(ndev->phydev);
@@ -786,48 +790,54 @@ static int emac_rx_clean_desc(struct emac_priv *priv, int budget)
rx_buf->dma_len, DMA_FROM_DEVICE);
status = emac_rx_frame_status(priv, rx_desc);
if (unlikely(status == frame_discard)) {
dev_kfree_skb_irq(rx_buf->skb);
rx_buf->skb = NULL;
} else {
if (likely(status != frame_discard)) {
skb = rx_buf->skb;
skb_len = rx_desc->FramePacketLength - ETHERNET_FCS_SIZE;
ecdev_receive(priv->ecdev,skb->data,skb_len);
dev_kfree_skb_irq(rx_buf->skb);
rx_buf->skb = NULL;
ecdev_receive(priv->ecdev, skb->data, skb_len);
}
if (++i == rx_ring->total_cnt)
rx_buf->dma_addr = dma_map_single(&priv->pdev->dev,
skb->data,
priv->dma_buf_sz,
DMA_FROM_DEVICE);
memset(rx_desc, 0, sizeof(struct emac_rx_desc));
rx_desc->BufferAddr1 = rx_buf->dma_addr;
rx_desc->BufferSize1 = rx_buf->dma_len;
if (++i == rx_ring->total_cnt) {
rx_desc->EndRing = 1;
i = 0;
}
dma_wmb();
rx_desc->OWN = 1;
}
rx_ring->tail = i;
emac_alloc_rx_desc_buffers(priv);
return receive_packet;
}
/* Name emac_alloc_rx_desc_buffers
* Arguments priv : pointer to driver private data structure
* Return 1: Cleaned; 0:Failed
* Return -1: fail; 0:success
* Description
*/
static void emac_alloc_rx_desc_buffers(struct emac_priv *priv)
static int emac_alloc_rx_desc_buffers(struct emac_priv *priv)
{
struct net_device *ndev = priv->ndev;
struct emac_desc_ring *rx_ring = &priv->rx_ring;
struct emac_desc_buffer *rx_buf;
struct sk_buff *skb;
struct sk_buff *skb = NULL;
struct emac_rx_desc *rx_desc;
u32 i;
i = rx_ring->head;
rx_buf = &rx_ring->desc_buf[i];
for (int i = 0; i < rx_ring->total_cnt; ++i) {
rx_buf = &rx_ring->desc_buf[i];
while (!rx_buf->skb) {
skb = netdev_alloc_skb_ip_align(ndev, priv->dma_buf_sz);
if (!skb) {
pr_err("sk_buff allocation failed\n");
break;
goto err_out;
}
skb->dev = ndev;
@@ -840,7 +850,9 @@ static void emac_alloc_rx_desc_buffers(struct emac_priv *priv)
DMA_FROM_DEVICE);
if (dma_mapping_error(&priv->pdev->dev, rx_buf->dma_addr)) {
netdev_err(ndev, "dma mapping_error\n");
goto dma_map_err;
dev_kfree_skb_any(skb);
rx_buf->skb = NULL;
goto err_out;
}
rx_desc = &((struct emac_rx_desc *)rx_ring->desc_addr)[i];
@@ -852,25 +864,19 @@ static void emac_alloc_rx_desc_buffers(struct emac_priv *priv)
rx_desc->FirstDescriptor = 0;
rx_desc->LastDescriptor = 0;
if (++i == rx_ring->total_cnt) {
if (i == rx_ring->total_cnt - 1)
rx_desc->EndRing = 1;
i = 0;
}
dma_wmb();
rx_desc->OWN = 1;
rx_buf = &rx_ring->desc_buf[i];
}
rx_ring->head = i;
return;
dma_map_err:
dev_kfree_skb_any(skb);
rx_buf->skb = NULL;
return;
return 0;
err_out:
emac_clean_rx_desc_ring(priv);
return -1;
}
/* Name emac_tx_mem_map
* Arguments priv : pointer to driver private data structure
* pstSkb : pointer to sk_buff structure passed by upper layer
@@ -1590,7 +1596,7 @@ static int emac_probe(struct platform_device *pdev)
priv->reset = devm_reset_control_get_optional(&pdev->dev, NULL);
if (IS_ERR(priv->reset)) {
dev_err(&pdev->dev, "Failed to get emac's resets\n");
goto mac_clk_disable;
goto phy_clk_disable;
}
reset_control_deassert(priv->reset);
@@ -1626,6 +1632,9 @@ err_mdio_deinit:
emac_mdio_deinit(priv);
reset_assert:
reset_control_assert(priv->reset);
phy_clk_disable:
if (priv->ref_clk_frm_soc)
clk_disable_unprepare(priv->phy_clk);
mac_clk_disable:
clk_disable_unprepare(priv->mac_clk);
err_netdev:

View File

@@ -1990,6 +1990,11 @@ static struct rtw_phl_scan_param *_alloc_phl_param(_adapter *adapter, u8 scan_ch
struct rtw_phl_scan_param *phl_param = NULL;
struct scan_priv *scan_priv = NULL;
if (adapter->phl_role == NULL) {
RTW_ERR(FUNC_ADPT_FMT" phl_role == NULL\n", FUNC_ADPT_ARG(adapter));
goto _err_exit;
}
if (scan_ch_num == 0) {
RTW_ERR("%s scan_ch_num = 0\n", __func__);
goto _err_exit;

View File

@@ -250,7 +250,11 @@ static u64 rproc_virtio_get_features(struct virtio_device *vdev)
rsc = (void *)rvdev->rproc->table_ptr + rvdev->rsc_offset;
#ifdef CONFIG_SOC_SPACEMIT_K1X
return (u64)rsc->dfeatures | ((u64)rsc->gfeatures << 32);
#else
return rsc->dfeatures;
#endif
}
static void rproc_transport_features(struct virtio_device *vdev)
@@ -277,8 +281,9 @@ static int rproc_virtio_finalize_features(struct virtio_device *vdev)
rproc_transport_features(vdev);
/* Make sure we don't have any features > 32 bits! */
#ifndef CONFIG_SOC_SPACEMIT_K1X
BUG_ON((u32)vdev->features != vdev->features);
#endif
/*
* Remember the finalized features of our vdev, and provide it
* to the remote processor once it is powered on.

View File

@@ -87,6 +87,7 @@ struct spacemit_rproc {
void __iomem *base[MAX_MEM_BASE];
struct spacemit_mbox *mb;
char *verid;
unsigned int size;
#ifdef CONFIG_PM_SLEEP
struct rpmsg_device *rpdev;
#ifdef CONFIG_HIBERNATION
@@ -177,21 +178,12 @@ static int spacemit_rproc_prepare(struct rproc *rproc)
da = rmem->base;
}
if (strcmp(it.node->name, "vdev0buffer")) {
mem = rproc_mem_entry_init(dev, NULL,
rmem->base,
rmem->size, da,
spacemit_rproc_mem_alloc,
spacemit_rproc_mem_release,
it.node->name);
} else {
/* Register reserved memory for vdev buffer alloc */
mem = rproc_of_resm_mem_entry_init(dev, index,
rmem->size,
rmem->base,
it.node->name);
}
mem = rproc_mem_entry_init(dev, NULL,
rmem->base,
rmem->size, da,
spacemit_rproc_mem_alloc,
spacemit_rproc_mem_release,
it.node->name);
if (!mem)
return -ENOMEM;
@@ -264,7 +256,7 @@ static int spacemit_rproc_start(struct rproc *rproc)
struct spacemit_rproc *priv = rproc->priv;
if (priv->verid != NULL)
pr_notice("the firmare version id is:%s\n", priv->verid);
pr_notice("the firmare version id is:%s\n", rproc_da_to_va(rproc, (u64)priv->verid, priv->size, NULL));
/* enable ipc2ap clk & reset--> rcpu side */
writel(0xff, priv->base[BOOTC_MEM_BASE_OFFSET] + ESOS_AON_PER_CLK_RST_CTL_REG);
@@ -300,7 +292,7 @@ static int spacemit_rproc_parse_fw(struct rproc *rproc, const struct firmware *f
int ret;
u64 sh_size;
struct spacemit_rproc *ddata = rproc->priv;
char *version_id_table, *version_id_va;
char *version_id_table;
ddata->verid = NULL;
/* find the firmare id */
@@ -308,10 +300,8 @@ static int spacemit_rproc_parse_fw(struct rproc *rproc, const struct firmware *f
if (!version_id_table) {
dev_info(&rproc->dev, "Can not find version id table\n");
} else {
version_id_va = ioremap((phys_addr_t)version_id_table, sh_size);
ddata->verid = version_id_va;
ddata->verid = version_id_table;
ddata->size = sh_size;
}
ret = rproc_elf_load_rsc_table(rproc, fw);

View File

@@ -277,6 +277,7 @@ static const struct spacemit_reset_signal
[RESET_SDH1] = { APMU_SDH1_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
[RESET_USB_AXI] = { APMU_USB_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
[RESET_USBP1_AXI] = { APMU_USB_CLK_RES_CTRL, BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU },
[RESET_COMBO_PHY] = { APMU_PCIE_CLK_RES_CTRL_0, BIT(8), 0, BIT(8), RST_BASE_TYPE_APMU },
[RESET_USB3_0] = { APMU_USB_CLK_RES_CTRL, BIT(9)|BIT(10)|BIT(11), BIT(9)|BIT(10)|BIT(11), 0, RST_BASE_TYPE_APMU },
[RESET_QSPI] = { APMU_QSPI_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
[RESET_QSPI_BUS] = { APMU_QSPI_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
@@ -570,4 +571,3 @@ out:
}
CLK_OF_DECLARE(k1x_reset, "spacemit,k1x-reset", spacemit_reset_init);

View File

@@ -84,54 +84,55 @@
#define RESET_SDH1 73
#define RESET_USB_AXI 74
#define RESET_USBP1_AXI 75
#define RESET_USB3_0 76
#define RESET_QSPI 77
#define RESET_QSPI_BUS 78
#define RESET_DMA 79
#define RESET_AES 80
#define RESET_VPU 81
#define RESET_GPU 82
#define RESET_SDH2 83
#define RESET_MC 84
#define RESET_EM_AXI 85
#define RESET_EM 86
#define RESET_AUDIO_SYS 87
#define RESET_HDMI 88
#define RESET_PCIE0 89
#define RESET_PCIE1 90
#define RESET_PCIE2 91
#define RESET_EMAC0 92
#define RESET_EMAC1 93
#define RESET_COMBO_PHY 76
#define RESET_USB3_0 77
#define RESET_QSPI 78
#define RESET_QSPI_BUS 79
#define RESET_DMA 80
#define RESET_AES 81
#define RESET_VPU 82
#define RESET_GPU 83
#define RESET_SDH2 84
#define RESET_MC 85
#define RESET_EM_AXI 86
#define RESET_EM 87
#define RESET_AUDIO_SYS 88
#define RESET_HDMI 89
#define RESET_PCIE0 90
#define RESET_PCIE1 91
#define RESET_PCIE2 92
#define RESET_EMAC0 93
#define RESET_EMAC1 94
//APBC2
#define RESET_SEC_UART1 94
#define RESET_SEC_SSP2 95
#define RESET_SEC_TWSI3 96
#define RESET_SEC_RTC 97
#define RESET_SEC_TIMERS0 98
#define RESET_SEC_KPC 99
#define RESET_SEC_GPIO 100
#define RESET_SEC_UART1 95
#define RESET_SEC_SSP2 96
#define RESET_SEC_TWSI3 97
#define RESET_SEC_RTC 98
#define RESET_SEC_TIMERS0 99
#define RESET_SEC_KPC 100
#define RESET_SEC_GPIO 101
#define RESET_RCPU_HDMIAUDIO 101
#define RESET_RCPU_CAN 102
#define RESET_RCPU_HDMIAUDIO 102
#define RESET_RCPU_CAN 103
#define RESET_RCPU_I2C0 103
#define RESET_RCPU_SSP0 104
#define RESET_RCPU_IR 105
#define RESET_RCPU_UART0 106
#define RESET_RCPU_UART1 107
#define RESET_RCPU_I2C0 104
#define RESET_RCPU_SSP0 105
#define RESET_RCPU_IR 106
#define RESET_RCPU_UART0 107
#define RESET_RCPU_UART1 108
#define RESET_RCPU2_PWM0 108
#define RESET_RCPU2_PWM1 109
#define RESET_RCPU2_PWM2 110
#define RESET_RCPU2_PWM3 111
#define RESET_RCPU2_PWM4 112
#define RESET_RCPU2_PWM5 113
#define RESET_RCPU2_PWM6 114
#define RESET_RCPU2_PWM7 115
#define RESET_RCPU2_PWM8 116
#define RESET_RCPU2_PWM9 117
#define RESET_RCPU2_PWM0 109
#define RESET_RCPU2_PWM1 110
#define RESET_RCPU2_PWM2 111
#define RESET_RCPU2_PWM3 112
#define RESET_RCPU2_PWM4 113
#define RESET_RCPU2_PWM5 114
#define RESET_RCPU2_PWM6 115
#define RESET_RCPU2_PWM7 116
#define RESET_RCPU2_PWM8 117
#define RESET_RCPU2_PWM9 118
#define RESET_NUMBER 118
#define RESET_NUMBER 119
#endif /* __DT_BINDINGS_RESET_SAPCEMIT_K1X_H__ */