amdgpu,radeon: Add workarounds for the Spacemit K1-X RISC-V platform

1. In various GMC versions (v6-v11), the DMA address mask is
  reduced to 34 bits. This is necessary because PCIe devices on the
  Spacemit K1-X platform support a maximum of 34-bit physical addressing.
2. In amdgpu_ttm.c, force the use of the `ttm_write_combined` cache mode.
 This is required because the K1-X platform lacks PCIe cache coherency.
3. In radeon_ttm.c and amdgpu_vram_mgr.c, switch the caching for
IO memory to `ttm_uncached`.This is done to guarantee data correctness
 during VRAM access on this platform.

Signed-off-by: liyeshan <yeshan.li@spacemit.com>
Change-Id: I294b741d1cc7923bfe535299c304f9f443673d92

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

@@ -1103,6 +1103,9 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
 	else
 		caching = ttm_cached;
 
+#ifdef CONFIG_SOC_SPACEMIT_K1X
+	caching = ttm_write_combined;
+#endif
 	/* allocate space for the uninitialized page entries */
 	if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
 		kfree(gtt);