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k1: cpufreq: using on v-f table to support k1 & m1 chip

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m1 can overclock to 1.8G through the turbo mode, but k1 cannot

Change-Id: Icede3f45019c1b5dbd1d088830c21f73d1798feb
This commit is contained in:
Nell
2024-08-30 21:57:56 +08:00
committed by zhangmeng
parent 782e581581
commit 2f79a53e2b
10 changed files with 230 additions and 273 deletions
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2
arch/riscv/boot/dts/spacemit/k1-x_MINI-PC.dts
View File

@@ -10,7 +10,7 @@
#include "k1-x-lcd.dtsi"
#include "k1-x-hdmi.dtsi"
#include "k1-x_opp_table.dtsi"
#include "k1-x_thermal_cooling.dtsi"
#include "m1-x_thermal_cooling.dtsi"
/ {
model = "spacemit k1-x MINI-PC board";

2
arch/riscv/boot/dts/spacemit/k1-x_MUSE-Book.dts
View File

@@ -10,7 +10,7 @@
#include "k1-x-lcd.dtsi"
#include "k1-x-hdmi.dtsi"
#include "k1-x_opp_table.dtsi"
#include "k1-x_thermal_cooling.dtsi"
#include "m1-x_thermal_cooling.dtsi"
/ {
model = "M1-MUSE-BOOK";

2
arch/riscv/boot/dts/spacemit/k1-x_MUSE-Card.dts
View File

@@ -11,7 +11,7 @@
#include "k1-x-lcd.dtsi"
#include "k1-x-camera-sdk.dtsi"
#include "k1-x_opp_table.dtsi"
#include "k1-x_thermal_cooling.dtsi"
#include "m1-x_thermal_cooling.dtsi"
/ {
model = "spacemit k1-x MUSE-Card board";

2
arch/riscv/boot/dts/spacemit/k1-x_MUSE-Pi.dts
View File

@@ -11,7 +11,7 @@
#include "k1-x-lcd.dtsi"
#include "k1-x-camera-sdk.dtsi"
#include "k1-x_opp_table.dtsi"
#include "k1-x_thermal_cooling.dtsi"
#include "m1-x_thermal_cooling.dtsi"
/ {
model = "spacemit k1-x MUSE-Pi board";

145
arch/riscv/boot/dts/spacemit/k1-x_opp_table.dtsi
View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2024 Spacemit, Inc */
/* Copyright (c) 2023 Spacemit, Inc */
&cpus {
clst_core_opp_table0: opp_table0 {
@@ -11,6 +11,133 @@
clock-names = "ace0","ace1","tcm","cci","pll3", "c0hi", "c1hi";
cci-hz = /bits/ 64 <614000000>;
opp1800000000 {
opp-hz = /bits/ 64 <1800000000>, /bits/ 64 <1800000000>;
tcm-hz = /bits/ 64 <900000000>;
ace-hz = /bits/ 64 <900000000>;
opp-microvolt = <1160000>;
clock-latency-ns = <200000>;
turbo-mode;
};
opp1600000000 {
opp-hz = /bits/ 64 <1600000000>, /bits/ 64 <1600000000>;
tcm-hz = /bits/ 64 <800000000>;
ace-hz = /bits/ 64 <800000000>;
opp-microvolt = <1050000>;
clock-latency-ns = <200000>;
};
opp1228800000 {
opp-hz = /bits/ 64 <1228800000>, /bits/ 64 <1228800000>;
tcm-hz = /bits/ 64 <614400000>;
ace-hz = /bits/ 64 <614400000>;
opp-microvolt = <950000>;
clock-latency-ns = <200000>;
};
opp1000000000 {
opp-hz = /bits/ 64 <1000000000>, /bits/ 64 <1000000000>;
tcm-hz = /bits/ 64 <500000000>;
ace-hz = /bits/ 64 <500000000>;
opp-microvolt = <950000>;
clock-latency-ns = <200000>;
};
opp819000000 {
opp-hz = /bits/ 64 <819000000>, /bits/ 64 <819000000>;
opp-microvolt = <950000>;
tcm-hz = /bits/ 64 <409500000>;
ace-hz = /bits/ 64 <409500000>;
clock-latency-ns = <200000>;
};
opp614400000 {
opp-hz = /bits/ 64 <614400000>, /bits/ 64 <614400000>;
tcm-hz = /bits/ 64 <307200000>;
ace-hz = /bits/ 64 <307200000>;
opp-microvolt = <950000>;
clock-latency-ns = <200000>;
};
};
clst_core_opp_table1: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
clocks = <&ccu CLK_CPU_C0_ACE>, <&ccu CLK_CPU_C1_ACE>, <&ccu CLK_CPU_C0_TCM>,
<&ccu CLK_CCI550>, <&ccu CLK_PLL3>, <&ccu CLK_CPU_C0_HI>, <&ccu CLK_CPU_C1_HI>;
clock-names = "ace0","ace1","tcm","cci","pll3", "c0hi", "c1hi";
cci-hz = /bits/ 64 <614000000>;
opp1800000000 {
opp-hz = /bits/ 64 <1800000000>, /bits/ 64 <1800000000>;
tcm-hz = /bits/ 64 <900000000>;
ace-hz = /bits/ 64 <900000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <200000>;
turbo-mode;
};
opp1600000000 {
opp-hz = /bits/ 64 <1600000000>, /bits/ 64 <1600000000>;
tcm-hz = /bits/ 64 <800000000>;
ace-hz = /bits/ 64 <800000000>;
opp-microvolt = <1050000>;
clock-latency-ns = <200000>;
};
opp1228800000 {
opp-hz = /bits/ 64 <1228800000>, /bits/ 64 <1228800000>;
tcm-hz = /bits/ 64 <614400000>;
ace-hz = /bits/ 64 <614400000>;
opp-microvolt = <950000>;
clock-latency-ns = <200000>;
};
opp1000000000 {
opp-hz = /bits/ 64 <1000000000>, /bits/ 64 <1000000000>;
tcm-hz = /bits/ 64 <500000000>;
ace-hz = /bits/ 64 <500000000>;
opp-microvolt = <950000>;
clock-latency-ns = <200000>;
};
opp819000000 {
opp-hz = /bits/ 64 <819000000>, /bits/ 64 <819000000>;
opp-microvolt = <950000>;
tcm-hz = /bits/ 64 <409500000>;
ace-hz = /bits/ 64 <409500000>;
clock-latency-ns = <200000>;
};
opp614400000 {
opp-hz = /bits/ 64 <614400000>, /bits/ 64 <614400000>;
tcm-hz = /bits/ 64 <307200000>;
ace-hz = /bits/ 64 <307200000>;
opp-microvolt = <950000>;
clock-latency-ns = <200000>;
};
};
clst_core_opp_table2: opp_table2 {
compatible = "operating-points-v2";
opp-shared;
clocks = <&ccu CLK_CPU_C0_ACE>, <&ccu CLK_CPU_C1_ACE>, <&ccu CLK_CPU_C0_TCM>,
<&ccu CLK_CCI550>, <&ccu CLK_PLL3>, <&ccu CLK_CPU_C0_HI>, <&ccu CLK_CPU_C1_HI>;
clock-names = "ace0","ace1","tcm","cci","pll3", "c0hi", "c1hi";
cci-hz = /bits/ 64 <614000000>;
opp1800000000 {
opp-hz = /bits/ 64 <1800000000>, /bits/ 64 <1800000000>;
tcm-hz = /bits/ 64 <900000000>;
ace-hz = /bits/ 64 <900000000>;
opp-microvolt = <1050000>;
clock-latency-ns = <200000>;
turbo-mode;
};
opp1600000000 {
opp-hz = /bits/ 64 <1600000000>, /bits/ 64 <1600000000>;
tcm-hz = /bits/ 64 <800000000>;
@@ -57,54 +184,54 @@
clst-supply = <&dcdc_1>;
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
clock-names = "cls0", "cls1";
operating-points-v2 = <&clst_core_opp_table0>;
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
};
&cpu_1 {
clst-supply = <&dcdc_1>;
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
clock-names = "cls0", "cls1";
operating-points-v2 = <&clst_core_opp_table0>;
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
};
&cpu_2 {
clst-supply = <&dcdc_1>;
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
clock-names = "cls0", "cls1";
operating-points-v2 = <&clst_core_opp_table0>;
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
};
&cpu_3 {
clst-supply = <&dcdc_1>;
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
clock-names = "cls0", "cls1";
operating-points-v2 = <&clst_core_opp_table0>;
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
};
&cpu_4 {
clst-supply = <&dcdc_1>;
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
clock-names = "cls0", "cls1";
operating-points-v2 = <&clst_core_opp_table0>;
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
};
&cpu_5 {
clst-supply = <&dcdc_1>;
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
clock-names = "cls0", "cls1";
operating-points-v2 = <&clst_core_opp_table0>;
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
};
&cpu_6 {
clst-supply = <&dcdc_1>;
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
clock-names = "cls0", "cls1";
operating-points-v2 = <&clst_core_opp_table0>;
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
};
&cpu_7 {
clst-supply = <&dcdc_1>;
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
clock-names = "cls0", "cls1";
operating-points-v2 = <&clst_core_opp_table0>;
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
};

32
arch/riscv/boot/dts/spacemit/k1-x_thermal_cooling.dtsi
View File

@@ -30,26 +30,26 @@
cooling-maps {
map0 {
trip = <&cls0_trip0>;
cooling-device = <&cpu_0 1 2>,
<&cpu_1 1 2>,
<&cpu_2 1 2>,
<&cpu_3 1 2>,
<&cpu_4 1 2>,
<&cpu_5 1 2>,
<&cpu_6 1 2>,
<&cpu_7 1 2>;
cooling-device = <&cpu_0 2 3>,
<&cpu_1 2 3>,
<&cpu_2 2 3>,
<&cpu_3 2 3>,
<&cpu_4 2 3>,
<&cpu_5 2 3>,
<&cpu_6 2 3>,
<&cpu_7 2 3>;
};
map1 {
trip = <&cls0_trip1>;
cooling-device = <&cpu_0 3 3>,
<&cpu_1 3 3>,
<&cpu_2 3 3>,
<&cpu_3 3 3>,
<&cpu_4 3 3>,
<&cpu_5 3 3>,
<&cpu_6 3 3>,
<&cpu_7 3 3>;
cooling-device = <&cpu_0 4 4>,
<&cpu_1 4 4>,
<&cpu_2 4 4>,
<&cpu_3 4 4>,
<&cpu_4 4 4>,
<&cpu_5 4 4>,
<&cpu_6 4 4>,
<&cpu_7 4 4>;
};
};
};

2
arch/riscv/boot/dts/spacemit/m1-x_milkv-jupiter.dts
View File

@@ -10,7 +10,7 @@
#include "k1-x-hdmi.dtsi"
#include "k1-x-lcd.dtsi"
#include "k1-x-camera-sdk.dtsi"
#include "m1-x_opp_table.dtsi"
#include "k1-x_opp_table.dtsi"
#include "m1-x_thermal_cooling.dtsi"
/ {

234
arch/riscv/boot/dts/spacemit/m1-x_opp_table.dtsi
View File

@@ -1,234 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2023 Spacemit, Inc */
&cpus {
clst_core_opp_table0: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
clocks = <&ccu CLK_CPU_C0_ACE>, <&ccu CLK_CPU_C1_ACE>, <&ccu CLK_CPU_C0_TCM>,
<&ccu CLK_CCI550>, <&ccu CLK_PLL3>, <&ccu CLK_CPU_C0_HI>, <&ccu CLK_CPU_C1_HI>;
clock-names = "ace0","ace1","tcm","cci","pll3", "c0hi", "c1hi";
cci-hz = /bits/ 64 <614000000>;
opp1800000000 {
opp-hz = /bits/ 64 <1800000000>, /bits/ 64 <1800000000>;
tcm-hz = /bits/ 64 <900000000>;
ace-hz = /bits/ 64 <900000000>;
opp-microvolt = <1160000>;
clock-latency-ns = <200000>;
};
opp1600000000 {
opp-hz = /bits/ 64 <1600000000>, /bits/ 64 <1600000000>;
tcm-hz = /bits/ 64 <800000000>;
ace-hz = /bits/ 64 <800000000>;
opp-microvolt = <1050000>;
clock-latency-ns = <200000>;
};
opp1228800000 {
opp-hz = /bits/ 64 <1228800000>, /bits/ 64 <1228800000>;
tcm-hz = /bits/ 64 <614400000>;
ace-hz = /bits/ 64 <614400000>;
opp-microvolt = <950000>;
clock-latency-ns = <200000>;
};
opp1000000000 {
opp-hz = /bits/ 64 <1000000000>, /bits/ 64 <1000000000>;
tcm-hz = /bits/ 64 <500000000>;
ace-hz = /bits/ 64 <500000000>;
opp-microvolt = <950000>;
clock-latency-ns = <200000>;
};
opp819000000 {
opp-hz = /bits/ 64 <819000000>, /bits/ 64 <819000000>;
opp-microvolt = <950000>;
tcm-hz = /bits/ 64 <409500000>;
ace-hz = /bits/ 64 <409500000>;
clock-latency-ns = <200000>;
};
opp614400000 {
opp-hz = /bits/ 64 <614400000>, /bits/ 64 <614400000>;
tcm-hz = /bits/ 64 <307200000>;
ace-hz = /bits/ 64 <307200000>;
opp-microvolt = <950000>;
clock-latency-ns = <200000>;
};
};
clst_core_opp_table1: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
clocks = <&ccu CLK_CPU_C0_ACE>, <&ccu CLK_CPU_C1_ACE>, <&ccu CLK_CPU_C0_TCM>,
<&ccu CLK_CCI550>, <&ccu CLK_PLL3>, <&ccu CLK_CPU_C0_HI>, <&ccu CLK_CPU_C1_HI>;
clock-names = "ace0","ace1","tcm","cci","pll3", "c0hi", "c1hi";
cci-hz = /bits/ 64 <614000000>;
opp1800000000 {
opp-hz = /bits/ 64 <1800000000>, /bits/ 64 <1800000000>;
tcm-hz = /bits/ 64 <900000000>;
ace-hz = /bits/ 64 <900000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <200000>;
};
opp1600000000 {
opp-hz = /bits/ 64 <1600000000>, /bits/ 64 <1600000000>;
tcm-hz = /bits/ 64 <800000000>;
ace-hz = /bits/ 64 <800000000>;
opp-microvolt = <1050000>;
clock-latency-ns = <200000>;
};
opp1228800000 {
opp-hz = /bits/ 64 <1228800000>, /bits/ 64 <1228800000>;
tcm-hz = /bits/ 64 <614400000>;
ace-hz = /bits/ 64 <614400000>;
opp-microvolt = <950000>;
clock-latency-ns = <200000>;
};
opp1000000000 {
opp-hz = /bits/ 64 <1000000000>, /bits/ 64 <1000000000>;
tcm-hz = /bits/ 64 <500000000>;
ace-hz = /bits/ 64 <500000000>;
opp-microvolt = <950000>;
clock-latency-ns = <200000>;
};
opp819000000 {
opp-hz = /bits/ 64 <819000000>, /bits/ 64 <819000000>;
opp-microvolt = <950000>;
tcm-hz = /bits/ 64 <409500000>;
ace-hz = /bits/ 64 <409500000>;
clock-latency-ns = <200000>;
};
opp614400000 {
opp-hz = /bits/ 64 <614400000>, /bits/ 64 <614400000>;
tcm-hz = /bits/ 64 <307200000>;
ace-hz = /bits/ 64 <307200000>;
opp-microvolt = <950000>;
clock-latency-ns = <200000>;
};
};
clst_core_opp_table2: opp_table2 {
compatible = "operating-points-v2";
opp-shared;
clocks = <&ccu CLK_CPU_C0_ACE>, <&ccu CLK_CPU_C1_ACE>, <&ccu CLK_CPU_C0_TCM>,
<&ccu CLK_CCI550>, <&ccu CLK_PLL3>, <&ccu CLK_CPU_C0_HI>, <&ccu CLK_CPU_C1_HI>;
clock-names = "ace0","ace1","tcm","cci","pll3", "c0hi", "c1hi";
cci-hz = /bits/ 64 <614000000>;
opp1800000000 {
opp-hz = /bits/ 64 <1800000000>, /bits/ 64 <1800000000>;
tcm-hz = /bits/ 64 <900000000>;
ace-hz = /bits/ 64 <900000000>;
opp-microvolt = <1050000>;
clock-latency-ns = <200000>;
};
opp1600000000 {
opp-hz = /bits/ 64 <1600000000>, /bits/ 64 <1600000000>;
tcm-hz = /bits/ 64 <800000000>;
ace-hz = /bits/ 64 <800000000>;
opp-microvolt = <1050000>;
clock-latency-ns = <200000>;
};
opp1228800000 {
opp-hz = /bits/ 64 <1228800000>, /bits/ 64 <1228800000>;
tcm-hz = /bits/ 64 <614400000>;
ace-hz = /bits/ 64 <614400000>;
opp-microvolt = <950000>;
clock-latency-ns = <200000>;
};
opp1000000000 {
opp-hz = /bits/ 64 <1000000000>, /bits/ 64 <1000000000>;
tcm-hz = /bits/ 64 <500000000>;
ace-hz = /bits/ 64 <500000000>;
opp-microvolt = <950000>;
clock-latency-ns = <200000>;
};
opp819000000 {
opp-hz = /bits/ 64 <819000000>, /bits/ 64 <819000000>;
opp-microvolt = <950000>;
tcm-hz = /bits/ 64 <409500000>;
ace-hz = /bits/ 64 <409500000>;
clock-latency-ns = <200000>;
};
opp614400000 {
opp-hz = /bits/ 64 <614400000>, /bits/ 64 <614400000>;
tcm-hz = /bits/ 64 <307200000>;
ace-hz = /bits/ 64 <307200000>;
opp-microvolt = <950000>;
clock-latency-ns = <200000>;
};
};
};
&cpu_0 {
clst-supply = <&dcdc_1>;
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
clock-names = "cls0", "cls1";
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
};
&cpu_1 {
clst-supply = <&dcdc_1>;
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
clock-names = "cls0", "cls1";
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
};
&cpu_2 {
clst-supply = <&dcdc_1>;
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
clock-names = "cls0", "cls1";
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
};
&cpu_3 {
clst-supply = <&dcdc_1>;
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
clock-names = "cls0", "cls1";
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
};
&cpu_4 {
clst-supply = <&dcdc_1>;
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
clock-names = "cls0", "cls1";
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
};
&cpu_5 {
clst-supply = <&dcdc_1>;
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
clock-names = "cls0", "cls1";
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
};
&cpu_6 {
clst-supply = <&dcdc_1>;
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
clock-names = "cls0", "cls1";
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
};
&cpu_7 {
clst-supply = <&dcdc_1>;
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
clock-names = "cls0", "cls1";
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
};

8
drivers/cpufreq/cpufreq-dt.c
View File

@@ -191,10 +191,18 @@ static int cpufreq_exit(struct cpufreq_policy *policy)
return 0;
}
#ifdef CONFIG_SOC_SPACEMIT_K1X
extern int spacmeit_cpufreq_veritfy(struct cpufreq_policy_data *policy);
#endif
static struct cpufreq_driver dt_cpufreq_driver = {
.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
CPUFREQ_IS_COOLING_DEV,
#ifndef CONFIG_SOC_SPACEMIT_K1X
.verify = cpufreq_generic_frequency_table_verify,
#else
.verify = spacmeit_cpufreq_veritfy,
#endif
.target_index = set_target,
.get = cpufreq_generic_get,
.init = cpufreq_init,

74
drivers/cpufreq/spacemit-cpufreq.c
View File

@@ -28,24 +28,33 @@ struct private_data {
int opp_token;
};
static u32 product_prop = 0, wafer_prop = 0;
#ifdef CONFIG_CPU_HOTPLUG_THERMAL
struct thermal_cooling_device **ghotplug_cooling;
extern struct thermal_cooling_device **
of_hotplug_cooling_register(struct cpufreq_policy *policy);
#endif
#define TURBO0_FREQUENCY (1600000000)
#define TURBO1_FREQUENCY (3200000000)
#define STABLE_FREQUENCY (1200000000)
#define FILTER_POINTS_0 (135)
#define FILTER_POINTS_1 (142)
#define FREQ_TABLE_0 (0)
#define FREQ_TABLE_1 (1)
#define FREQ_TABLE_2 (2)
#define PRODUCT_ID_M1 (0x36070000)
#ifdef CONFIG_SOC_SPACEMIT_K1X
#define TURBO0_FREQUENCY (1600000000)
#define TURBO1_FREQUENCY (3200000000)
#define STABLE_FREQUENCY (1200000000)
#define FILTER_POINTS_0 (135)
#define FILTER_POINTS_1 (142)
#define K1_MAX_FREQ_LIMITATION (1600000)
#define M1_MAX_FREQ_LIMITATION (1800000)
#endif
#define PRODUCT_ID_M1 (0x36070000)
static int spacemit_policy_notifier(struct notifier_block *nb,
unsigned long event, void *data)
@@ -408,13 +417,58 @@ free_cpumask:
return ret;
}
#ifdef CONFIG_SOC_SPACEMIT_K1X
int spacmeit_cpufreq_veritfy(struct cpufreq_policy_data *policy)
{
struct cpufreq_frequency_table *pos;
unsigned int freq, next_larger = ~0;
bool found = false;
if (!policy->freq_table)
return -ENODEV;
if ((wafer_prop << 16 | product_prop) == PRODUCT_ID_M1) {
/* M1 */
/* can update to 1.8G */
policy->max = policy->max > M1_MAX_FREQ_LIMITATION ? M1_MAX_FREQ_LIMITATION : policy->max;
cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
M1_MAX_FREQ_LIMITATION);
} else {
/* K1 */
/* only 1.6G allowed max */
policy->max = policy->max > K1_MAX_FREQ_LIMITATION ? K1_MAX_FREQ_LIMITATION : policy->max;
cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
K1_MAX_FREQ_LIMITATION);
}
cpufreq_for_each_valid_entry(pos, policy->freq_table) {
freq = pos->frequency;
if ((freq >= policy->min) && (freq <= policy->max)) {
found = true;
break;
}
if ((next_larger > freq) && (freq > policy->max))
next_larger = freq;
}
if (!found) {
policy->max = next_larger;
cpufreq_verify_within_cpu_limits(policy);
}
pr_debug("verification lead to (%u - %u kHz) for cpu %u\n",
policy->min, policy->max, policy->cpu);
return 0;
}
#endif
static int spacemit_dt_cpufreq_pre_probe(struct platform_device *pdev)
{
int cpu, ret;
struct device_node *cpus;
struct device_node *product_id, *wafer_id;
u32 prop = 0;
u32 product_prop = 0, wafer_prop = 0;
if (strncmp(pdev->name, "cpufreq-dt", 10) != 0)
return 0;
@@ -434,6 +488,7 @@ static int spacemit_dt_cpufreq_pre_probe(struct platform_device *pdev)
pr_info("Spacemit Platform with no 'product-id' in DTS\n");
}
#ifdef CONFIG_SOC_SPACEMIT_K1X
if ((wafer_prop << 16 | product_prop) == PRODUCT_ID_M1) {
for_each_possible_cpu(cpu) {
if (prop <= FILTER_POINTS_0)
@@ -450,6 +505,7 @@ static int spacemit_dt_cpufreq_pre_probe(struct platform_device *pdev)
spacemit_dt_cpufreq_pre_early_init(&pdev->dev, cpu, FREQ_TABLE_0);
}
}
#endif
return 0;
}