spi: k1: Add clock phase adjustment support

For high-frequency communication between an SPI controller
and peripheral devices, clock phase misalignment may
occur, requiring calibration.

Change-Id: I673a9f2b69e08a7ba41c2c9d27b43b392212628e
Signed-off-by: huzhen <george.hu@spacemit.com>

drivers/spi/spi-k1x.c

@@ -1004,6 +1004,11 @@ static int k1x_spi_probe(struct platform_device *pdev)
 	clk_prepare_enable(drv_data->clk);
     	reset_control_deassert(drv_data->reset);
 
+	if ((master->bus_num == 2 || master->bus_num == 3) && \
+		of_get_property(np, "k1x,ssp-enable-clk-phase-adj", NULL)) {
+			k1x_spi_write(drv_data, CLK_PHASE_ADJ, 0x1);
+	}
+
 	/* Load default SSP configuration */
 	k1x_spi_write(drv_data, TOP_CTRL, 0);
 	k1x_spi_write(drv_data, FIFO_CTRL, 0);

drivers/spi/spi-k1x.h

@@ -37,6 +37,7 @@
 #define RWOT_CTRL		0x24    /* SSP RWOT Control Register */
 #define RWOT_CCM		0x28    /* SSP RWOT Counter Cycles Match Register */
 #define RWOT_CVWRn		0x2C    /* SSP RWOT Counter Value Write for Read Request Register */
+#define CLK_PHASE_ADJ		0x30    /* SSP clock phase adjustment for debug */
 
 /* 0x00 TOP_CTRL */
 #define TOP_TTELP		(1 << 18)