RISC-V: Fold boolean vector lane extraction into scalar loads

src/hotspot/cpu/riscv/riscv_v.ad

@@ -5113,6 +5113,29 @@ instruct extractD(fRegD dst, vReg src, immI idx, vReg tmp)
   ins_pipe(pipe_slow);
 %}
 
+instruct extractUB_loadV_index_imm(iRegINoSp dst, memory mem, immI idx)
+%{
+  match(Set dst (ExtractUB (LoadVector mem) idx));
+  format %{ "lbu $dst, $mem+$idx\t# boolean vector lane" %}
+  ins_encode %{
+    __ lbu(as_Register($dst$$reg),
+           Address(as_Register($mem$$base), $mem$$disp + (int)($idx$$constant)));
+  %}
+  ins_pipe(iload_reg_mem);
+%}
+
+instruct extractUB_loadV_index_reg(iRegINoSp dst, memory mem, iRegI idx)
+%{
+  match(Set dst (ExtractUB (LoadVector mem) idx));
+  format %{ "lbu $dst, $mem+$idx\t# boolean vector lane" %}
+  ins_encode %{
+    Register dst = as_Register($dst$$reg);
+    __ add(dst, as_Register($mem$$base), as_Register($idx$$reg));
+    __ lbu(dst, Address(dst, $mem$$disp));
+  %}
+  ins_pipe(pipe_slow);
+%}
+
 instruct extractUB_index_imm(iRegINoSp dst, vReg src, immI idx, vReg tmp)
 %{
   match(Set dst (ExtractUB src idx));