Jagan Teki 6901aab8e3 clk: sunxi: Add Allwinner A80 CLK driver ...

Add initial clock driver for Allwinner A80.

- Implement UART bus clocks via ccu_clk_gate table for
  A80, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for A80,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

2019-01-18 22:19:09 +05:30

2.2 KiB

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