forked from OERV-BSP/u-boot
fca70d6181
Aspeed AST27xx SoCs integrate the CPTRA 1.0 secure IP, which export a SHA accelerator interface for SoC to use. Note that CPTRA 1.0 supports only SHA384 and SHA512 and this patch is verified by the 'hash test sha384/sha512' commands. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
31 lines
1.0 KiB
Plaintext
31 lines
1.0 KiB
Plaintext
config ASPEED_HACE
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bool "ASPEED Hash and Crypto Engine"
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depends on DM_HASH
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help
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Select this option to enable a driver for using the SHA engine in
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the ASPEED BMC SoCs.
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Enabling this allows the use of SHA operations in hardware without
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requiring the SHA software implementations. It also improves performance
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and saves code size.
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config ASPEED_ACRY
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bool "ASPEED RSA and ECC Engine"
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depends on ASPEED_AST2600
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help
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Select this option to enable a driver for using the RSA/ECC engine in
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the ASPEED BMC SoCs.
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Enabling this allows the use of RSA/ECC operations in hardware without requiring the
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software implementations. It also improves performance and saves code size.
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config ASPEED_CPTRA_SHA
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bool "Caliptra SHA ACC for Aspeed AST27xx SoCs"
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depends on DM_HASH
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help
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Select this option to enable a driver for using the SHA accelerator provided
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by Caliptra 1.0, which is integrated in AST27xx BMC SoCs.
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Enabling this allows the use of SHA operations in hardware. Note that only
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SHA384 and SHA512 are supported by Caliptra 1.0.
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