forked from OERV-BSP/u-boot
f28911368e
On coldboot, only HART 0 among the four HARTs of TH1520 is brought up by hardware, and the remaining HARTs are in reset states, requiring manual setup of reset address and deassertion to function normal. Introduce a routine to do the work. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
49 lines
1.5 KiB
C
49 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2025 Yao Zi <ziyao@disroot.org>
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*
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* TH1520 SoC has a set of undocumented customized PMP registers that are
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* configured through MMIO operation. It must be disabled before entering
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* the DRAM region, or an exception will be raised.
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*/
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#include <asm/io.h>
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#include <cpu_func.h>
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#include <linux/bitops.h>
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#define TH1520_C910_RST (void __iomem *)(0xffef014000 + 0x004)
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#define TH1520_C910_CORE_RST_N(n) BIT((n) + 1)
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#define TH1520_SYSCFG_AP_BASE (void __iomem *)(0xffef018000)
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#define TH1520_SYSCFG_CORE_START_L(n) (TH1520_SYSCFG_AP_BASE + 0x50 + 8 * (n))
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#define TH1520_SYSCFG_CORE_START_H(n) (TH1520_SYSCFG_AP_BASE + 0x54 + 8 * (n))
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#define TH1520_PMP_BASE (void *)0xffdc020000
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void th1520_kick_secondary_cores(void)
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{
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int i;
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/*
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* On coldboot, only HART 0 is brought up by hardware, and resets for
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* secondary cores are asserted. Set reset address of secondary cores
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* to the entry of SPL, then deassert the resets to bring them up.
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*/
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for (i = 1; i < 4; i++) {
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writel(CONFIG_SPL_TEXT_BASE & 0xffffffff,
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TH1520_SYSCFG_CORE_START_L(i));
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writel(CONFIG_SPL_TEXT_BASE >> 32,
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TH1520_SYSCFG_CORE_START_H(i));
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}
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setbits_le32(TH1520_C910_RST, TH1520_C910_CORE_RST_N(1) |
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TH1520_C910_CORE_RST_N(2) |
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TH1520_C910_CORE_RST_N(3));
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}
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void th1520_invalidate_pmp(void)
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{
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/* Invalidate the PMP configuration as in vendor U-Boot code */
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writel(0x0, TH1520_PMP_BASE + 0x0);
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invalidate_icache_all();
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}
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