2 Commits

Author	SHA1	Message	Date
Yao Zi	f28911368e	riscv: cpu: th1520: Add a routine to bring up secondary cores ... On coldboot, only HART 0 among the four HARTs of TH1520 is brought up by hardware, and the remaining HARTs are in reset states, requiring manual setup of reset address and deassertion to function normal. Introduce a routine to do the work. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>	2025-07-03 16:14:13 +08:00
Yao Zi	5fe9ced355	riscv: cpu: Add TH1520 CPU support ... Introduce the SoC-specific code and corresponding Kconfig entries for TH1520 SoC. Following features are implemented for TH1520, - Cache enable/disable through customized CSR - Invalidation of customized PMP entries - DRAM driver probing for SPL Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>	2025-05-21 16:49:52 +08:00