define a suitable default address for CONFIG_SPL_LOAD_FIT_ADDRESS
to make it easier on folks enabling HABv4.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Move CONFIG_ENV_OVERWRITE=y into commont renesas_rcar.config to make sure
this configuration option is consistently enabled on all of Renesas R-Car
Gen2, Gen3, Gen4. Currently this option is not enabled on Gen4, this fix
corrects that omission.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
("Enable EFI_LOADER_BOUNCE_BUFFER") is not the correct fix for the
problem it describes.
The change of memory addressing leading to side-effects in commit
22f2c9ed9f ("efi: memory: use the lmb API's for allocating and
freeing memory") is remedied by commit 1a48b0be93 ("lmb: prohibit
allocations above ram_top even from same bank").
This reverts commit 9c792ab336.
The current value of CONFIG_FASTBOOT_BUF_ADDR is incorrect for hardware
with 512MB and 1GB of RAM. The RAM address ranges for these devices are:
- 512MB:
- Start: 0x80000000
- End: 0xA0000000
- 1GB:
- Start: 0x80000000
- End: 0xC0000000
The current buffer address makes fastboot downloads work only on
hardware with 2GB of RAM.
To fix this issue:
1. Lower CONFIG_FASTBOOT_BUF_ADDR to 0x88200000. This makes the buffer
to be equal ot CONFIG_SYS_LOAD_ADDR, which is a safe address to
download files using fastboot.
2. Reduce the size of the download buffer to 128MB, avoiding overlaps
with RAMDISK_ADDR_R. This is a good enough value for individual
downloads.
These changes make fastboot downloads work with 512MB and 1GB devices.
Fixes: defe30a78b ("verdin-am62: add DFU, USB and UUU fastboot support")
Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
The content of CONFIG_OF_SPL_REMOVE_PROPS is the same in both
STM32MP15xx DHCOM and DHCOR defconfigs, deduplicate the content
into stm32mp15_dhsom.config .
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The access-controllers DT property is not useful in STM32MP15xx SPL,
remove it to reduce SPL control DT size. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Commit 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")
broke booting from SD card on STM32MP15xx , reinstate raw mode SD
boot configuration options and select the correct raw mode partition
for STM32MP15xx to fix SD boot on STM32MP15xx DHSOM.
Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")
Reported-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Enable driver for DesignWare MSHC. TH1520 supports all
speed modes up to HS400ES and UHS SDR105.
Also enable ADMA and mmc command.
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Enable OF_UPSTREAM to use upstream DT and add starfive/ prefix to
the DEFAULT_DEVICE_TREE. Rename jh7110-starfive-visionfive-2-u-boot.dtsi
to jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi and set the v1.3b
device tree as the default device tree.
Drop redundant DT files from arch/riscv/dts/ and redundant clock and
reset definitions from include/dt-bindings/.
Since the old clock definitions is a little different from those in
upstream Linux, update the clock definitions in clock drivers
accordingly.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Without this patch, there will be error indicating that
"Cannot use 64 bit addresses with SDMA", and the booting
process will stuck.
please see full boot log below
U-Boot 2022.04-g18185931 (Sep 11 2024 - 13:15:30 +0800)
SoC: LS1028AE Rev1.0 (0x870b0010)
Clock Configuration:
CPU0(A72):1500 MHz CPU1(A72):1500 MHz
Bus: 400 MHz DDR: 1600 MT/s
Reset Configuration Word (RCW):
00000000: 3c004010 00000030 00000000 00000000
00000010: 00000000 018f0000 0030c000 00000000
00000020: 020031a0 00002580 00000000 00003296
00000030: 00000000 00000010 00000000 00000000
00000040: 00000000 00000000 00000000 00000000
00000050: 00000000 00000000 00000000 00000000
00000060: 00000000 00000000 200e705a 00000000
00000070: bb580000 00000000
Model: LS1028A RDB Board
Board: LS1028AE Rev1.0-RDB, Version: C, boot from SD
FPGA: v8 (RDB)
SERDES1 Reference : Clock1 = 100.00MHz Clock2 = 100.00MHz
DRAM: 3.9 GiB
DDR 3.9 GiB (DDR4, 32-bit, CL=11, ECC on)
Using SERDES1 Protocol: 47960 (0xbb58)
PCIe1: pcie@3400000 Root Complex: no link
PCIe2: pcie@3500000 Root Complex: x1 gen2
Core: 45 devices, 22 uclasses, devicetree: separate
WDT: Started watchdog@c000000 with servicing (60s timeout)
WDT: Started watchdog@c010000 with servicing (60s timeout)
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment
EEPROM: Invalid ID (ff ff ff ff)
In: serial
Out: serial
Err: serial
SEC0: RNG instantiated
Net:
Warning: enetc-0 (eth0) using random MAC address - d2:9b:a5:37:7b:b5
eth0: enetc-0
Warning: enetc-2 (eth1) using random MAC address - ca:57:11:de:de:cb
, eth1: enetc-2, eth2: swp0, eth3: swp1, eth4: swp2, eth5: swp3
Hit any key to stop autoboot: 0
Trying load HDP firmware from SD..
switch to partitions #0, OK
mmc0 is current device
Device: FSL_SDHC
Manufacturer ID: 9f
OEM: 5449
Name: SD32G
Bus Speed: 50000000
Mode: SD High Speed (50MHz)
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 28.9 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
MMC read: dev # 0, block # 18944, count 512 ... 512 blocks read: OK
Loading hdp firmware from 0x00000000a0000000 offset 0x0000000000002000
Loading hdp firmware Complete
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
** Unable to read file / **
Failed to load '/'
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
Scanning disk mmc@2140000.blk...
Scanning disk mmc@2150000.blk...
Found 7 disks
ERROR: invalid device tree
Found EFI removable media binary efi/boot/bootaa64.efi
981992 bytes read in 44 ms (21.3 MiB/s)
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
WARNING could not find node vivante,gc: FDT_ERR_NOTFOUND.
Booting /efi\boot\bootaa64.efi
Cannot use 64 bit addresses with SDMA
Error reading cluster
** Unable to read file /efi/boot/grubaa64.efi **
Unexpected return from initial read: Device Error, buffersize 29D790
Failed to load image ￢ : Device Error
start_image() returned Device Error
EFI LOAD FAILED: continuing...
switch to partitions #0, OK
mmc1(part 0) is current device
Scanning mmc 1:1...
** Unable to read file / **
Failed to load '/'
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
BootOrder not defined
EFI boot manager: Cannot load any image
Scanning mmc 1:2...
** Unable to read file / **
Failed to load '/'
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
BootOrder not defined
EFI boot manager: Cannot load any image
starting USB...
Bus usb@3100000: Register 200017f NbrPorts 2
Starting the controller
USB XHCI 1.00
Bus usb@3110000: Register 200017f NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus usb@3100000 for devices... 1 USB Device(s) found
scanning bus usb@3110000 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
Device 0: unknown device
Trying load from SD ...
switch to partitions #0, OK
mmc0 is current device
Device: FSL_SDHC
Manufacturer ID: 9f
OEM: 5449
Name: SD32G
Bus Speed: 50000000
Mode: SD High Speed (50MHz)
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 28.9 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
MMC read: dev # 0, block # 32768, count 81920 ... 81920 blocks read: OK
Wrong Image Format for bootm command
ERROR: can't get kernel image!
Signed-off-by: Wei Ming Chen <jj251510319013@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Network is broken on variant 3 boards since commit 61ff13283c ("board:
sl28: move to OF_UPSTREAM") because it was removing the variant 3
handling. That is because at that time the var3 device tree was not
upstream. FWIW variant 3 is actually the same as the base variant, but
I've missed that the -u-boot.dtsi is not inlcuded in this case which
will set the ethernet alias. Now that the var3 device tree is upstream,
just re-add it to the SPL handling again.
Fixes: 61ff13283c ("board: sl28: move to OF_UPSTREAM")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Increase the malloc size to 2MiB because our FIT image exceeds the 1MiB
limit either if BL31 mode is enabled or if another device tree is added
to the image.
Signed-off-by: Michael Walle <mwalle@kernel.org>
Tested-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Instead of bloating the defconfig with CONFIG_CMD_*, move J7 devices to
start using TI_COMMON_CMD_OPTIONS.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Garrett Giordano <ggiordano@phytec.com> says:
This patch set adds the phyCORE AM62Ax board support and documenation to
u-boot.
The phyCORE-AM62Ax is a SoM (System on Module) featuring TI's AM62Ax SoC. It can
be used in combination with different carrier boards. This module can come
with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs
from the AM62x family.
A development Kit, called phyBOARD-Lyra is used as a carrier board reference
design around the AM62x SoM.
This series depends on the following two patches:
- [PATCH v2] arm: mach-k3: am62a7: Provide a way to obtain boot device for non SPL
https://lists.denx.de/pipermail/u-boot/2024-October/570156.html
- [PATCH] board: phytec: common: Introduce CONFIG_PHYTEC_K3_DDR_PATCH
https://lists.denx.de/pipermail/u-boot/2024-November/571543.html
Link: https://lore.kernel.org/r/20241118231606.3161665-1-ggiordano@phytec.com
[trini: Fix warning in board/phytec/common/k3/board.c when
CONFIG_EFI_HAVE_CAPSULE_SUPPORT is not enabled]
Signed-off-by: Tom Rini <trini@konsulko.com>
Enable raw & on disk capsule updates and provide configs required
for updating MTD devices. Also resync after savedefconfig.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Enables ESM configs for j721s2 and disables them for AM68 as AM68
includes J721s2 configs by default.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
This reverts commit 1fdf53ace1, reversing
changes made to e5aef1bbf1.
I had missed that this caused too much size growth on rcar3_salvator-x.
Signed-off-by: Tom Rini <trini@konsulko.com>
With VBE we want to use FIT in all phases of the boot. Add Kconfig
options to support this.
Disable the options for sandbox_vpl for now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since RPI works well using EFI and has no size limitations with regards
to U-Boot, add the needed structures to support capsule updates.
While at it update the most commonly used defconfigs and include capsule
support and U-Boot commands needed by EFI
Tested-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
The env variable "SN" is used to store the serial number on DH electronics
SoMs. New SoMs will use the variable "dh_som_serial_number". To ensure
compatibility, these env variables are synchronized. This is achieved
using callback functions.
Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Bryan Brattlof <bb@ti.com> says:
Hello Everyone!
This small series converts TI's AM65x reference board to use
CONFIG_OF_UPSTREAM and removes the unused device tree files from
arch/arm/dts.
Because it's the last board using a AM65x without enabling OF_UPSTREAM
it allows us to also remove all the SoC FDT files as well and keep a
single version of the SoC's DT files in the dts/upstream directory going
forward.
Link: https://lore.kernel.org/r/20241121-am65x-v1-0-fe87aff1b5fc@ti.com
Rather than rely on manual updates from the arch/arm/dts directory,
enable CONFIG_OF_UPSTREAM to receive automatic device tree updates for
the am65x reference board.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Aniket Limaye <a-limaye@ti.com> says:
This series adds OPP_LOW spec data in k3_avs driver and enables a config
option to select the OPP_LOW performance point.
J7200 SOC supports OPP_LOW and OPP_NOM as two Operating Performance
Points as per (7.5 Operating Performance Points) section in the
Datasheet [0].
- A72SS/MSMC at 2 GHz/1GHz operation must use OPP_NOM.
- A72SS/MSMC at 1 GHz/500 MHz operation can use OPP_NOM or OPP_LOW
voltage (though OPP_LOW voltage is recommended to reduce power
consumption).
The actual OPP voltage for the device is read from the efuse and
updated in k3_avs_probe().
The default j7200 devicetree and k3_avs driver set OPP_NOM spec
frequency and voltage.
In the board init file, if K3_OPP_LOW config is enabled, Check if
OPP_LOW AVS voltage read from efuse is valid and update frequency (A72
and MSMC) and voltage (VDD_CPU) as per the OPP_LOW spec.
[0]: https://www.ti.com/lit/gpn/dra821u (J7200 Datasheet)
Test logs:
https://gist.github.com/aniket-l/328ad93ed60c2419ed7be9f85e6b6075
- With series applied on master and CONFIG_K3_OPP_LOW enabled in
j7200_evm_r5_defconfig
- Logs shown with and without efuse register programmed for OPP_0
(Errors out if OPP_0 not found, programs OPP_LOW spec if found)
- Voltage update verified using 'i2c md 0x4c 0xe' in u-boot
- Frequency update verified using 'k3conf clock dump' in linux
Link: https://lore.kernel.org/r/20241119003617.1871183-1-a-limaye@ti.com
Define new CONFIG_K3_OPP_LOW under arm/mach-k3/r5/Kconfig and add
default value to j7200_evm_r5_defconfig
Signed-off-by: Reid Tonking <reidt@ti.com>
Signed-off-by: Aniket Limaye <a-limaye@ti.com>
