Merge patch series "modify npcm7xx/8xx feature and bug fixed"

Jim Liu <jim.t90615@gmail.com> says:

modify npcm7xx/8xx feature and bug fixed

Link: https://lore.kernel.org/r/20250807053224.2169557-1-JJLIU0@nuvoton.com

arch/arm/dts/nuvoton-common-npcm8xx.dtsi

@@ -62,6 +62,11 @@
 			reg = <0x0 0xf0801000 0x0 0x1000>;
 		};
 
+		timer0: timer@f0801068 {
+			compatible = "nuvoton,npcm845-timer";
+			reg = <0x0 0xf0801068 0x0 0x8>;
+		};
+
 		sdhci0: sdhci@f0842000 {
 			compatible = "nuvoton,npcm845-sdhci";
 			reg = <0x0 0xf0842000 0x0 0x100>;
@@ -136,7 +141,7 @@
 
 			host_intf: host_intf@9f000 {
 				compatible = "nuvoton,npcm845-host-intf";
-				reg = <0x9f000 0x1000>;
+				reg = <0x9f000 0x1000>, <0x7000 0x40>;
 				type = "espi";
 				ioaddr = <0x4e>;
 				channel-support = <0xf>;
@@ -157,14 +162,6 @@
 				status = "disabled";
 			};
 
-			timer0: timer@8000 {
-				compatible = "nuvoton,npcm845-timer";
-				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-				reg = <0x8000 0x1C>;
-				clocks = <&clk NPCM8XX_CLK_REFCLK>;
-				clock-names = "refclk";
-			};
-
 			serial0: serial@0 {
 				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
 				reg = <0x0 0x1000>;

arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi

@@ -1056,5 +1056,9 @@
 			groups = "jtag2";
 			function = "jtag2";
 		};
+		vcdhs_pins: vcdhs-pins {
+			groups = "vcdhs";
+			function = "vcdhs";
+		};
 	};
 };

board/nuvoton/arbel_evb/arbel_evb.c

@@ -94,5 +94,12 @@ int dram_init_banksize(void)
 	return 0;
 }
 
-EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, board_set_console);
+static int last_stage_init(void)
+{
+#ifdef CONFIG_SYS_SKIP_UART_INIT
+	return board_set_console();
+#endif
+	return 0;
+}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
 

board/nuvoton/poleg_evb/poleg_evb.c

@@ -64,7 +64,9 @@ static int last_stage_init(void)
 		}
 		sprintf(value, "ttyS%d,115200n8", dev->seq_);
 		env_set("console", value);
+#ifdef CONFIG_SYS_SKIP_UART_INIT
 		return board_set_console();
+#endif
 	}
 
 	return 0;

configs/arbel_evb_defconfig

@@ -17,7 +17,6 @@ CONFIG_SYS_LOAD_ADDR=0x06208000
 CONFIG_WATCHDOG_TIMEOUT_MSECS=120000
 # CONFIG_PSCI_RESET is not set
 CONFIG_ARCH_NPCM8XX=y
-CONFIG_SYS_SKIP_UART_INIT=y
 CONFIG_TARGET_ARBEL_EVB=y
 CONFIG_ENV_ADDR=0x807C0000
 # CONFIG_EFI_LOADER is not set

configs/poleg_evb_defconfig

@@ -16,7 +16,6 @@ CONFIG_DEFAULT_DEVICE_TREE="nuvoton-npcm750-evb"
 CONFIG_DM_RESET=y
 CONFIG_SYS_LOAD_ADDR=0x10000000
 CONFIG_TARGET_POLEG=y
-CONFIG_SYS_SKIP_UART_INIT=y
 CONFIG_ENV_ADDR=0x80100000
 CONFIG_FIT=y
 CONFIG_USE_BOOTCOMMAND=y

drivers/i2c/npcm_i2c.c

@@ -34,6 +34,7 @@
 #define SMBCTL3_SDA_LVL		BIT(6)
 
 /* SMBCST */
+#define SMBCST_BUSY		BIT(0)
 #define SMBCST_BB		BIT(1)
 #define SMBCST_TGSCL		BIT(5)
 
@@ -479,11 +480,17 @@ static int npcm_i2c_xfer(struct udevice *dev,
 	struct npcm_i2c_bus *bus = dev_get_priv(dev);
 	struct npcm_i2c_regs *reg = bus->reg;
 	int ret = 0, err = 0;
+	u8 val;
 
 	if (nmsgs < 1 || nmsgs > 2) {
 		printf("%s: commands not support\n", __func__);
 		return -EREMOTEIO;
 	}
+
+	/* Wait for module out of busy */
+	if (readb_poll_timeout(&reg->cst, val, !(val & SMBCST_BUSY), 1000))
+		return -EBUSY;
+
 	/* clear ST register */
 	writeb(0xFF, &reg->st);
 

drivers/misc/npcm_host_intf.c

@@ -22,6 +22,8 @@
 /* ESPI Register offsets */
 #define ESPICFG			0x4
 #define ESPIHINDP		0x80
+#define ESPI_TEN		0xF0
+#define ESPI_ENG		0xF1
 
 /* MFSEL bit fileds */
 #define MFSEL1_LPCSEL		BIT(26)
@@ -40,10 +42,23 @@
 #define AUTO_HS2		BIT(12)
 #define AUTO_HS3		BIT(16)
 
+#define ESPI_TEN_ENABLE		0x55
+#define ESPI_TEN_DISABLE	0
+
+/* KCS/BPC interrupt control */
+#define BPCFEN			0x46
+#define FRIE			BIT(3)
+#define HRIE			BIT(4)
+#define KCS1CTL			0x18
+#define KCS2CTL			0x2a
+#define KCS3CTL			0x3c
+#define IBFIE			BIT(0)
+#define OBEIE			BIT(1)
+
 static int npcm_host_intf_bind(struct udevice *dev)
 {
 	struct regmap *syscon;
-	void __iomem *base;
+	void __iomem *base, *kcs_base;
 	u32 ch_supp, val;
 	u32 ioaddr;
 	const char *type;
@@ -83,6 +98,13 @@ static int npcm_host_intf_bind(struct udevice *dev)
 		val &= ~(CHSUPP_MASK | IOMODE_MASK | MAXFREQ_MASK);
 		val |= IOMODE_SDQ | MAXFREQ_33MHZ | FIELD_PREP(CHSUPP_MASK, ch_supp);
 		writel(val, base + ESPICFG);
+
+		if (device_is_compatible(dev, "nuvoton,npcm845-host-intf")) {
+			/* Workaround: avoid eSPI module getting into wrong state */
+			writeb(ESPI_TEN_ENABLE, base + ESPI_TEN);
+			writeb(BIT(6), base + ESPI_ENG);
+			writeb(ESPI_TEN_DISABLE, base + ESPI_TEN);
+		}
 	} else if (!strcmp(type, "lpc")) {
 		/* Select LPC pin function */
 		regmap_update_bits(syscon, MFSEL4, MFSEL4_ESPISEL, 0);
@@ -92,6 +114,15 @@ static int npcm_host_intf_bind(struct udevice *dev)
 	/* Release host wait */
 	setbits_8(SMC_CTL_REG_ADDR, SMC_CTL_HOSTWAIT);
 
+	kcs_base = dev_read_addr_index_ptr(dev, 1);
+	if (kcs_base) {
+		/* Disable KCS/BPC interrupts */
+		clrbits_8(kcs_base + BPCFEN, FRIE | HRIE);
+		clrbits_8(kcs_base + KCS1CTL, IBFIE | OBEIE);
+		clrbits_8(kcs_base + KCS2CTL, IBFIE | OBEIE);
+		clrbits_8(kcs_base + KCS3CTL, IBFIE | OBEIE);
+	}
+
 	return 0;
 }
 

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

@@ -23,6 +23,7 @@
 #define TIPRSTC		0x50
 #define CORSTC		0x5c
 #define FLOCKR1		0x74
+#define INTCR		0x3c
 #define INTCR4		0xc0
 #define I2CSEGSEL	0xe0
 #define MFSEL1		0x260
@@ -280,6 +281,7 @@ struct npcm8xx_pinctrl_priv {
 	FUNC(lkgpo2, FLOCKR1, 8, 9) \
 	FUNC(nprd_smi, FLOCKR1, 20, 190) \
 	FUNC(mmcwp, FLOCKR1, 24, 153) \
+	FUNC(vcdhs, INTCR, 27) \
 	FUNC(rg2refck, INTCR4, 6) \
 	FUNC(r1en, INTCR4, 12) \
 	FUNC(r2en, INTCR4, 13) \