arm64: dts: renesas: Add Renesas R-Car X5H R8A78000 SoC DTs

Add initial device trees for Renesas R-Car X5H R8A78000 SoC.
Include very basic clock, reset, power domain headers which
are used to control supported peripherals via SCMI / SCP. The
headers are currently kept limited to avoid possible ABI break.
A lot of clock are still stubbed via fixed-clock, this is going
to be gradually removed over time, as more of the platform is
upstreamed.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Khanh Le <khanh.le.xr@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

arch/arm/dts/r8a78000-u-boot.dtsi

@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source extras for U-Boot on R-Car R8A78000 SoC
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/ {
+	soc {
+		bootph-all;
+	};
+
+	/* Placeholder clock until the clock provider is in place */
+	clk_stub_gpio: clk-stub-gpio {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1000000>;
+	};
+
+	clk_stub_i2c0: clk-stub-i2c0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <150000000>;
+	};
+
+	clk_stub_i2c1: clk-stub-i2c1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <133333333>;
+	};
+
+	clk_stub_mmc: clk-stub-mmc {
+		compatible = "renesas,compound-clock";
+		#clock-cells = <0>;
+		clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_SDHI0>,
+			 <&scmi_clk 1691>;
+		clock-names = "mdlc", "per";
+	};
+};
+
+&cpg {
+	bootph-all;
+};
+
+&extal_clk {
+	bootph-all;
+};
+
+&extalr_clk {
+	bootph-all;
+};
+
+&gpio0 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio1 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio2 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio3 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio4 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio5 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio6 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio7 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio8 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio9 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio10 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&i2c0 {
+	clocks = <&clk_stub_i2c0>;
+};
+
+&i2c1 {
+	clocks = <&clk_stub_i2c1>;
+};
+
+&i2c2 {
+	clocks = <&clk_stub_i2c1>;
+};
+
+&i2c3 {
+	clocks = <&clk_stub_i2c1>;
+};
+
+&i2c4 {
+	clocks = <&clk_stub_i2c1>;
+};
+
+&i2c5 {
+	clocks = <&clk_stub_i2c1>;
+};
+
+&i2c6 {
+	clocks = <&clk_stub_i2c1>;
+};
+
+&i2c7 {
+	clocks = <&clk_stub_i2c1>;
+};
+
+&i2c8 {
+	clocks = <&clk_stub_i2c1>;
+};
+
+&mmc0 {
+	clocks = <&clk_stub_mmc>;
+};
+
+&prr {
+	bootph-all;
+};

include/dt-bindings/clock/r8a78000-clock-scmi.h

@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ *
+ * IDs match SCP 4.27
+ */
+
+#ifndef __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__
+#define __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__
+
+/*
+ * These definition indices match the Clock ID defined by SCP FW 4.27.
+ */
+
+#define SCP_CLOCK_ID_MDLC_UFS0		202
+#define SCP_CLOCK_ID_MDLC_UFS1		203
+#define SCP_CLOCK_ID_MDLC_SDHI0		204
+
+#define SCP_CLOCK_ID_MDLC_XPCS0		316
+#define SCP_CLOCK_ID_MDLC_XPCS1		317
+#define SCP_CLOCK_ID_MDLC_XPCS2		318
+#define SCP_CLOCK_ID_MDLC_XPCS3		319
+#define SCP_CLOCK_ID_MDLC_XPCS4		320
+#define SCP_CLOCK_ID_MDLC_XPCS5		321
+#define SCP_CLOCK_ID_MDLC_XPCS6		322
+#define SCP_CLOCK_ID_MDLC_XPCS7		323
+#define SCP_CLOCK_ID_MDLC_RSW3		324
+#define SCP_CLOCK_ID_MDLC_RSW3TSN	325
+#define SCP_CLOCK_ID_MDLC_RSW3AES	326
+#define SCP_CLOCK_ID_MDLC_RSW3TSNTES0	327
+#define SCP_CLOCK_ID_MDLC_RSW3TSNTES1	328
+#define SCP_CLOCK_ID_MDLC_RSW3TSNTES2	329
+#define SCP_CLOCK_ID_MDLC_RSW3TSNTES3	330
+#define SCP_CLOCK_ID_MDLC_RSW3TSNTES4	331
+#define SCP_CLOCK_ID_MDLC_RSW3TSNTES5	332
+#define SCP_CLOCK_ID_MDLC_RSW3TSNTES6	333
+#define SCP_CLOCK_ID_MDLC_RSW3TSNTES7	334
+#define SCP_CLOCK_ID_MDLC_RSW3MFWD	335
+
+#define SCP_CLOCK_ID_MDLC_MPPHY01	344
+#define SCP_CLOCK_ID_MDLC_MPPHY11	345
+#define SCP_CLOCK_ID_MDLC_MPPHY21	346
+#define SCP_CLOCK_ID_MDLC_MPPHY31	347
+#define SCP_CLOCK_ID_MDLC_MPPHY02	348
+
+#endif /* __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ */

include/dt-bindings/power/r8a78000-power-scmi.h

@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ *
+ * IDs match SCP 4.27
+ */
+
+#ifndef __DT_BINDINGS_R8A78000_SCMI_POWER_H__
+#define __DT_BINDINGS_R8A78000_SCMI_POWER_H__
+
+/*
+ * These power domain indices match the Power Domain ID defined by SCP FW 4.27.
+ */
+
+#define X5H_POWER_DOMAIN_ID_UFS0	12
+#define X5H_POWER_DOMAIN_ID_UFS1	13
+
+#define X5H_POWER_DOMAIN_ID_RSW		15
+
+#define X5H_POWER_DOMAIN_ID_MPP0	17
+#define X5H_POWER_DOMAIN_ID_MPP1	18
+#define X5H_POWER_DOMAIN_ID_MPP2	19
+#define X5H_POWER_DOMAIN_ID_MPP3	20
+
+#endif /* __DT_BINDINGS_R8A78000_SCMI_POWER_H__ */

include/dt-bindings/reset/r8a78000-reset-scmi.h

@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ *
+ * IDs match SCP 4.27
+ */
+
+#ifndef __DT_BINDINGS_R8A78000_SCMI_RESET_H__
+#define __DT_BINDINGS_R8A78000_SCMI_RESET_H__
+
+/*
+ * These definition indices match the Reset ID defined by SCP FW 4.27.
+ */
+
+#define SCP_RESET_DOMAIN_ID_UFS0	202
+#define SCP_RESET_DOMAIN_ID_UFS1	203
+
+#define SCP_RESET_DOMAIN_ID_XPCS0	316
+#define SCP_RESET_DOMAIN_ID_XPCS1	317
+#define SCP_RESET_DOMAIN_ID_XPCS2	318
+#define SCP_RESET_DOMAIN_ID_XPCS3	319
+#define SCP_RESET_DOMAIN_ID_XPCS4	320
+#define SCP_RESET_DOMAIN_ID_XPCS5	321
+#define SCP_RESET_DOMAIN_ID_XPCS6	322
+#define SCP_RESET_DOMAIN_ID_XPCS7	323
+
+#define SCP_RESET_DOMAIN_ID_MPPHY01	344
+#define SCP_RESET_DOMAIN_ID_MPPHY11	345
+#define SCP_RESET_DOMAIN_ID_MPPHY21	346
+#define SCP_RESET_DOMAIN_ID_MPPHY31	347
+#define SCP_RESET_DOMAIN_ID_MPPHY02	348
+
+#endif /* __DT_BINDINGS_R8A78000_SCMI_RESET_H__ */