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ARM: stm32: Add STM32MP13xx PMIC initialization for DDR3 DRAM type

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The STM32MP13xx PMIC initialization for DDR3 DRAM type is similar
to the STM32MP15xx PMIC initialization, except the VTT rail is not
enabled. Fill in the STM32MP13xx support.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
This commit is contained in:
Marek Vasut
2025-06-30 02:10:30 +02:00
committed by Patrice Chotard
parent a36e87127a
commit 61d353dc92
1 changed files with 32 additions and 15 deletions
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47
board/st/common/stpmic1.c
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@@ -14,8 +14,19 @@
#include <power/pmic.h> #include <power/pmic.h>
#include <power/stpmic1.h> #include <power/stpmic1.h>
static bool is_stm32mp13xx(void)
{
if (!IS_ENABLED(CONFIG_STM32MP13X))
return false;
return of_machine_is_compatible("st,stm32mp131") ||
of_machine_is_compatible("st,stm32mp133") ||
of_machine_is_compatible("st,stm32mp135");
}
int board_ddr_power_init(enum ddr_type ddr_type) int board_ddr_power_init(enum ddr_type ddr_type)
{ {
bool is_mp13 = is_stm32mp13xx();
struct udevice *dev; struct udevice *dev;
bool buck3_at_1800000v = false; bool buck3_at_1800000v = false;
int ret; int ret;
@@ -30,18 +41,21 @@ int board_ddr_power_init(enum ddr_type ddr_type)
switch (ddr_type) { switch (ddr_type) {
case STM32MP_DDR3: case STM32MP_DDR3:
/* VTT = Set LDO3 to sync mode */ /* VTT = Set LDO3 to sync mode */
ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3)); if (!is_mp13) {
if (ret < 0) /* Enable VTT only on STM32MP15xx */
return ret; ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
if (ret < 0)
return ret;
ret &= ~STPMIC1_LDO3_MODE; ret &= ~STPMIC1_LDO3_MODE;
ret &= ~STPMIC1_LDO12356_VOUT_MASK; ret &= ~STPMIC1_LDO12356_VOUT_MASK;
ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL); ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
ret); ret);
if (ret < 0) if (ret < 0)
return ret; return ret;
}
/* VDD_DDR = Set BUCK2 to 1.35V */ /* VDD_DDR = Set BUCK2 to 1.35V */
ret = pmic_clrsetbits(dev, ret = pmic_clrsetbits(dev,
@@ -69,11 +83,14 @@ int board_ddr_power_init(enum ddr_type ddr_type)
mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
/* Enable VTT = LDO3 */ /* Enable VTT = LDO3 */
ret = pmic_clrsetbits(dev, if (!is_mp13) {
STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), /* Enable VTT only on STM32MP15xx */
STPMIC1_LDO_ENA, STPMIC1_LDO_ENA); ret = pmic_clrsetbits(dev,
if (ret < 0) STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
return ret; STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
if (ret < 0)
return ret;
}
mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);