forked from OERV-BSP/u-boot
ARM: stm32: Add STM32MP13xx PMIC initialization for DDR3 DRAM type
The STM32MP13xx PMIC initialization for DDR3 DRAM type is similar to the STM32MP15xx PMIC initialization, except the VTT rail is not enabled. Fill in the STM32MP13xx support. Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
This commit is contained in:
committed by
Patrice Chotard
parent
a36e87127a
commit
61d353dc92
@@ -14,8 +14,19 @@
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#include <power/pmic.h>
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#include <power/stpmic1.h>
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static bool is_stm32mp13xx(void)
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{
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if (!IS_ENABLED(CONFIG_STM32MP13X))
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return false;
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return of_machine_is_compatible("st,stm32mp131") ||
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of_machine_is_compatible("st,stm32mp133") ||
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of_machine_is_compatible("st,stm32mp135");
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}
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int board_ddr_power_init(enum ddr_type ddr_type)
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{
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bool is_mp13 = is_stm32mp13xx();
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struct udevice *dev;
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bool buck3_at_1800000v = false;
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int ret;
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@@ -30,18 +41,21 @@ int board_ddr_power_init(enum ddr_type ddr_type)
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switch (ddr_type) {
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case STM32MP_DDR3:
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/* VTT = Set LDO3 to sync mode */
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ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
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if (ret < 0)
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return ret;
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if (!is_mp13) {
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/* Enable VTT only on STM32MP15xx */
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ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
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if (ret < 0)
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return ret;
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ret &= ~STPMIC1_LDO3_MODE;
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ret &= ~STPMIC1_LDO12356_VOUT_MASK;
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ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
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ret &= ~STPMIC1_LDO3_MODE;
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ret &= ~STPMIC1_LDO12356_VOUT_MASK;
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ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
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ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
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ret);
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if (ret < 0)
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return ret;
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ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
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ret);
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if (ret < 0)
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return ret;
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}
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/* VDD_DDR = Set BUCK2 to 1.35V */
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ret = pmic_clrsetbits(dev,
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@@ -69,11 +83,14 @@ int board_ddr_power_init(enum ddr_type ddr_type)
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mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
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/* Enable VTT = LDO3 */
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ret = pmic_clrsetbits(dev,
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STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
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STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
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if (ret < 0)
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return ret;
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if (!is_mp13) {
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/* Enable VTT only on STM32MP15xx */
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ret = pmic_clrsetbits(dev,
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STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
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STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
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if (ret < 0)
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return ret;
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}
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mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
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