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arm: dts: agilex5: Update CCU configuration

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Cache allocation for dirty writes in the CCU system cache was disabled
for performance optimization.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
This commit is contained in:
Tingting Meng
2025-04-15 09:55:35 +08:00
committed by Tien Fong Chee
parent d0bf7bebfd
commit 52891fda68
1 changed files with 4 additions and 2 deletions
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6
arch/arm/dts/socfpga_agilex5-u-boot.dtsi
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@@ -208,7 +208,8 @@
intel,offset-settings =
/* DMIUSMCTCR */
<0x00000300 0x00000001 0x00000003>,
<0x00000300 0x00000003 0x00000003>;
<0x00000300 0x00000003 0x00000003>,
<0x00000308 0x00000004 0x0000001F>;
bootph-all;
};
@@ -218,7 +219,8 @@
intel,offset-settings =
/* DMIUSMCTCR */
<0x00000300 0x00000001 0x00000003>,
<0x00000300 0x00000003 0x00000003>;
<0x00000300 0x00000003 0x00000003>,
<0x00000308 0x00000004 0x0000001F>;
bootph-all;
};
};