From 976719aa1923c4be7886676f64d96eeff767ca6f Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 5 Dec 2024 13:24:13 +0800 Subject: [PATCH] SOPHGO: riscv: dts: sophgo: sg2044: Add eFUSE device Add eFUSE controller node for SG2044. Signed-off-by: Inochi Amaoto --- arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 4 ++++ arch/riscv/boot/dts/sophgo/sg2044.dtsi | 12 ++++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts index fed3d9a384a0..1b506972d465 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts @@ -36,6 +36,10 @@ status = "okay"; }; +&efuse0 { + status = "okay"; +}; + &gmac0 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi index 320c4d1d08e6..9577aae08f7f 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi @@ -408,6 +408,18 @@ status = "disabled"; }; + efuse0: efuse@7040000000 { + compatible = "sophgo,sg2044-efuse"; + reg = <0x70 0x40000000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&clk CLK_GATE_EFUSE>, + <&clk CLK_GATE_APB_EFUSE>; + clock-names = "core", "apb"; + resets = <&rst RST_EFUSE0>; + status = "disabled"; + }; + i2c0: i2c@7040005000 { compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; reg = <0x70 0x40005000 0x0 0x1000>;