Files
linux/drivers
Dmitry Osipenko cb98598e68 clk: tegra20/30: Don't pre-initialize displays parent clock
Both Tegra20 and Tegra30 are initializing display's parent clock
incorrectly because PLLP is running at 216/408MHz while display rate is
set to 600MHz, but pre-setting the parent isn't needed at all because
display driver selects proper parent anyways.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-10 15:50:25 +01:00
..
2019-11-22 11:16:26 +05:30
2019-11-22 19:56:35 +00:00
2019-12-05 13:18:54 -08:00