From b136468a0024ea90c1259767c732eed12ce6edba Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Tue, 27 Sep 2022 07:55:04 +0000 Subject: [PATCH 01/36] clk: rockchip: use proper crypto0 name on rk3399 RK3399 has 2 crypto instance, named crypto0 and crypto1 in the TRM. Only reset for crypto1 is correctly named, but crypto0 is not. Since nobody use them, add a 0 to be consistent with the TRM and crypto1 entries. Acked-by: Rob Herring Signed-off-by: Corentin Labbe Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20220927075511.3147847-27-clabbe@baylibre.com Signed-off-by: Heiko Stuebner --- include/dt-bindings/clock/rk3399-cru.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 44e0a319f077..39169d94a44e 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -547,8 +547,8 @@ #define SRST_H_PERILP0 171 #define SRST_H_PERILP0_NOC 172 #define SRST_ROM 173 -#define SRST_CRYPTO_S 174 -#define SRST_CRYPTO_M 175 +#define SRST_CRYPTO0_S 174 +#define SRST_CRYPTO0_M 175 /* cru_softrst_con11 */ #define SRST_P_DCF 176 @@ -556,7 +556,7 @@ #define SRST_CM0S 178 #define SRST_CM0S_DBG 179 #define SRST_CM0S_PO 180 -#define SRST_CRYPTO 181 +#define SRST_CRYPTO0 181 #define SRST_P_PERILP1_SGRF 182 #define SRST_P_PERILP1_GRF 183 #define SRST_CRYPTO1_S 184 From f204a60e545ccd4bc28939054389690fd194cb5e Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 18 Oct 2022 17:13:59 +0200 Subject: [PATCH 02/36] dt-bindings: clock: add rk3588 clock definitions Add clock ID defines for rk3588. Compared to the downstream bindings written by Elaine, this uses continous gapless clock IDs starting at 0. Thus all numbers are different between downstream and upstream, but I kept exactly the same names. Co-Developed-by: Elaine Zhang Signed-off-by: Elaine Zhang Acked-by: Rob Herring Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-2-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- .../dt-bindings/clock/rockchip,rk3588-cru.h | 766 ++++++++++++++++++ 1 file changed, 766 insertions(+) create mode 100644 include/dt-bindings/clock/rockchip,rk3588-cru.h diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-bindings/clock/rockchip,rk3588-cru.h new file mode 100644 index 000000000000..b5616bca7b44 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h @@ -0,0 +1,766 @@ +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +/* + * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Copyright (c) 2022 Collabora Ltd. + * + * Author: Elaine Zhang + * Author: Sebastian Reichel + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H + +/* cru-clocks indices */ + +#define PLL_B0PLL 0 +#define PLL_B1PLL 1 +#define PLL_LPLL 2 +#define PLL_V0PLL 3 +#define PLL_AUPLL 4 +#define PLL_CPLL 5 +#define PLL_GPLL 6 +#define PLL_NPLL 7 +#define PLL_PPLL 8 +#define ARMCLK_L 9 +#define ARMCLK_B01 10 +#define ARMCLK_B23 11 +#define PCLK_BIGCORE0_ROOT 12 +#define PCLK_BIGCORE0_PVTM 13 +#define PCLK_BIGCORE1_ROOT 14 +#define PCLK_BIGCORE1_PVTM 15 +#define PCLK_DSU_S_ROOT 16 +#define PCLK_DSU_ROOT 17 +#define PCLK_DSU_NS_ROOT 18 +#define PCLK_LITCORE_PVTM 19 +#define PCLK_DBG 20 +#define PCLK_DSU 21 +#define PCLK_S_DAPLITE 22 +#define PCLK_M_DAPLITE 23 +#define MBIST_MCLK_PDM1 24 +#define MBIST_CLK_ACDCDIG 25 +#define HCLK_I2S2_2CH 26 +#define HCLK_I2S3_2CH 27 +#define CLK_I2S2_2CH_SRC 28 +#define CLK_I2S2_2CH_FRAC 29 +#define CLK_I2S2_2CH 30 +#define MCLK_I2S2_2CH 31 +#define I2S2_2CH_MCLKOUT 32 +#define CLK_DAC_ACDCDIG 33 +#define CLK_I2S3_2CH_SRC 34 +#define CLK_I2S3_2CH_FRAC 35 +#define CLK_I2S3_2CH 36 +#define MCLK_I2S3_2CH 37 +#define I2S3_2CH_MCLKOUT 38 +#define PCLK_ACDCDIG 39 +#define HCLK_I2S0_8CH 40 +#define CLK_I2S0_8CH_TX_SRC 41 +#define CLK_I2S0_8CH_TX_FRAC 42 +#define MCLK_I2S0_8CH_TX 43 +#define CLK_I2S0_8CH_TX 44 +#define CLK_I2S0_8CH_RX_SRC 45 +#define CLK_I2S0_8CH_RX_FRAC 46 +#define MCLK_I2S0_8CH_RX 47 +#define CLK_I2S0_8CH_RX 48 +#define I2S0_8CH_MCLKOUT 49 +#define HCLK_PDM1 50 +#define MCLK_PDM1 51 +#define HCLK_AUDIO_ROOT 52 +#define PCLK_AUDIO_ROOT 53 +#define HCLK_SPDIF0 54 +#define CLK_SPDIF0_SRC 55 +#define CLK_SPDIF0_FRAC 56 +#define MCLK_SPDIF0 57 +#define CLK_SPDIF0 58 +#define CLK_SPDIF1 59 +#define HCLK_SPDIF1 60 +#define CLK_SPDIF1_SRC 61 +#define CLK_SPDIF1_FRAC 62 +#define MCLK_SPDIF1 63 +#define ACLK_AV1_ROOT 64 +#define ACLK_AV1 65 +#define PCLK_AV1_ROOT 66 +#define PCLK_AV1 67 +#define PCLK_MAILBOX0 68 +#define PCLK_MAILBOX1 69 +#define PCLK_MAILBOX2 70 +#define PCLK_PMU2 71 +#define PCLK_PMUCM0_INTMUX 72 +#define PCLK_DDRCM0_INTMUX 73 +#define PCLK_TOP 74 +#define PCLK_PWM1 75 +#define CLK_PWM1 76 +#define CLK_PWM1_CAPTURE 77 +#define PCLK_PWM2 78 +#define CLK_PWM2 79 +#define CLK_PWM2_CAPTURE 80 +#define PCLK_PWM3 81 +#define CLK_PWM3 82 +#define CLK_PWM3_CAPTURE 83 +#define PCLK_BUSTIMER0 84 +#define PCLK_BUSTIMER1 85 +#define CLK_BUS_TIMER_ROOT 86 +#define CLK_BUSTIMER0 87 +#define CLK_BUSTIMER1 88 +#define CLK_BUSTIMER2 89 +#define CLK_BUSTIMER3 90 +#define CLK_BUSTIMER4 91 +#define CLK_BUSTIMER5 92 +#define CLK_BUSTIMER6 93 +#define CLK_BUSTIMER7 94 +#define CLK_BUSTIMER8 95 +#define CLK_BUSTIMER9 96 +#define CLK_BUSTIMER10 97 +#define CLK_BUSTIMER11 98 +#define PCLK_WDT0 99 +#define TCLK_WDT0 100 +#define PCLK_CAN0 101 +#define CLK_CAN0 102 +#define PCLK_CAN1 103 +#define CLK_CAN1 104 +#define PCLK_CAN2 105 +#define CLK_CAN2 106 +#define ACLK_DECOM 107 +#define PCLK_DECOM 108 +#define DCLK_DECOM 109 +#define ACLK_DMAC0 110 +#define ACLK_DMAC1 111 +#define ACLK_DMAC2 112 +#define ACLK_BUS_ROOT 113 +#define ACLK_GIC 114 +#define PCLK_GPIO1 115 +#define DBCLK_GPIO1 116 +#define PCLK_GPIO2 117 +#define DBCLK_GPIO2 118 +#define PCLK_GPIO3 119 +#define DBCLK_GPIO3 120 +#define PCLK_GPIO4 121 +#define DBCLK_GPIO4 122 +#define PCLK_I2C1 123 +#define PCLK_I2C2 124 +#define PCLK_I2C3 125 +#define PCLK_I2C4 126 +#define PCLK_I2C5 127 +#define PCLK_I2C6 128 +#define PCLK_I2C7 129 +#define PCLK_I2C8 130 +#define CLK_I2C1 131 +#define CLK_I2C2 132 +#define CLK_I2C3 133 +#define CLK_I2C4 134 +#define CLK_I2C5 135 +#define CLK_I2C6 136 +#define CLK_I2C7 137 +#define CLK_I2C8 138 +#define PCLK_OTPC_NS 139 +#define CLK_OTPC_NS 140 +#define CLK_OTPC_ARB 141 +#define CLK_OTPC_AUTO_RD_G 142 +#define CLK_OTP_PHY_G 143 +#define PCLK_SARADC 144 +#define CLK_SARADC 145 +#define PCLK_SPI0 146 +#define PCLK_SPI1 147 +#define PCLK_SPI2 148 +#define PCLK_SPI3 149 +#define PCLK_SPI4 150 +#define CLK_SPI0 151 +#define CLK_SPI1 152 +#define CLK_SPI2 153 +#define CLK_SPI3 154 +#define CLK_SPI4 155 +#define ACLK_SPINLOCK 156 +#define PCLK_TSADC 157 +#define CLK_TSADC 158 +#define PCLK_UART1 159 +#define PCLK_UART2 160 +#define PCLK_UART3 161 +#define PCLK_UART4 162 +#define PCLK_UART5 163 +#define PCLK_UART6 164 +#define PCLK_UART7 165 +#define PCLK_UART8 166 +#define PCLK_UART9 167 +#define CLK_UART1_SRC 168 +#define CLK_UART1_FRAC 169 +#define CLK_UART1 170 +#define SCLK_UART1 171 +#define CLK_UART2_SRC 172 +#define CLK_UART2_FRAC 173 +#define CLK_UART2 174 +#define SCLK_UART2 175 +#define CLK_UART3_SRC 176 +#define CLK_UART3_FRAC 177 +#define CLK_UART3 178 +#define SCLK_UART3 179 +#define CLK_UART4_SRC 180 +#define CLK_UART4_FRAC 181 +#define CLK_UART4 182 +#define SCLK_UART4 183 +#define CLK_UART5_SRC 184 +#define CLK_UART5_FRAC 185 +#define CLK_UART5 186 +#define SCLK_UART5 187 +#define CLK_UART6_SRC 188 +#define CLK_UART6_FRAC 189 +#define CLK_UART6 190 +#define SCLK_UART6 191 +#define CLK_UART7_SRC 192 +#define CLK_UART7_FRAC 193 +#define CLK_UART7 194 +#define SCLK_UART7 195 +#define CLK_UART8_SRC 196 +#define CLK_UART8_FRAC 197 +#define CLK_UART8 198 +#define SCLK_UART8 199 +#define CLK_UART9_SRC 200 +#define CLK_UART9_FRAC 201 +#define CLK_UART9 202 +#define SCLK_UART9 203 +#define ACLK_CENTER_ROOT 204 +#define ACLK_CENTER_LOW_ROOT 205 +#define HCLK_CENTER_ROOT 206 +#define PCLK_CENTER_ROOT 207 +#define ACLK_DMA2DDR 208 +#define ACLK_DDR_SHAREMEM 209 +#define ACLK_CENTER_S200_ROOT 210 +#define ACLK_CENTER_S400_ROOT 211 +#define FCLK_DDR_CM0_CORE 212 +#define CLK_DDR_TIMER_ROOT 213 +#define CLK_DDR_TIMER0 214 +#define CLK_DDR_TIMER1 215 +#define TCLK_WDT_DDR 216 +#define CLK_DDR_CM0_RTC 217 +#define PCLK_WDT 218 +#define PCLK_TIMER 219 +#define PCLK_DMA2DDR 220 +#define PCLK_SHAREMEM 221 +#define CLK_50M_SRC 222 +#define CLK_100M_SRC 223 +#define CLK_150M_SRC 224 +#define CLK_200M_SRC 225 +#define CLK_250M_SRC 226 +#define CLK_300M_SRC 227 +#define CLK_350M_SRC 228 +#define CLK_400M_SRC 229 +#define CLK_450M_SRC 230 +#define CLK_500M_SRC 231 +#define CLK_600M_SRC 232 +#define CLK_650M_SRC 233 +#define CLK_700M_SRC 234 +#define CLK_800M_SRC 235 +#define CLK_1000M_SRC 236 +#define CLK_1200M_SRC 237 +#define ACLK_TOP_M300_ROOT 238 +#define ACLK_TOP_M500_ROOT 239 +#define ACLK_TOP_M400_ROOT 240 +#define ACLK_TOP_S200_ROOT 241 +#define ACLK_TOP_S400_ROOT 242 +#define CLK_MIPI_CAMARAOUT_M0 243 +#define CLK_MIPI_CAMARAOUT_M1 244 +#define CLK_MIPI_CAMARAOUT_M2 245 +#define CLK_MIPI_CAMARAOUT_M3 246 +#define CLK_MIPI_CAMARAOUT_M4 247 +#define MCLK_GMAC0_OUT 248 +#define REFCLKO25M_ETH0_OUT 249 +#define REFCLKO25M_ETH1_OUT 250 +#define CLK_CIFOUT_OUT 251 +#define PCLK_MIPI_DCPHY0 252 +#define PCLK_MIPI_DCPHY1 253 +#define PCLK_CSIPHY0 254 +#define PCLK_CSIPHY1 255 +#define ACLK_TOP_ROOT 256 +#define PCLK_TOP_ROOT 257 +#define ACLK_LOW_TOP_ROOT 258 +#define PCLK_CRU 259 +#define PCLK_GPU_ROOT 260 +#define CLK_GPU_SRC 261 +#define CLK_GPU 262 +#define CLK_GPU_COREGROUP 263 +#define CLK_GPU_STACKS 264 +#define PCLK_GPU_PVTM 265 +#define CLK_GPU_PVTM 266 +#define CLK_CORE_GPU_PVTM 267 +#define PCLK_GPU_GRF 268 +#define ACLK_ISP1_ROOT 269 +#define HCLK_ISP1_ROOT 270 +#define CLK_ISP1_CORE 271 +#define CLK_ISP1_CORE_MARVIN 272 +#define CLK_ISP1_CORE_VICAP 273 +#define ACLK_ISP1 274 +#define HCLK_ISP1 275 +#define ACLK_NPU1 276 +#define HCLK_NPU1 277 +#define ACLK_NPU2 278 +#define HCLK_NPU2 279 +#define HCLK_NPU_CM0_ROOT 280 +#define FCLK_NPU_CM0_CORE 281 +#define CLK_NPU_CM0_RTC 282 +#define PCLK_NPU_PVTM 283 +#define PCLK_NPU_GRF 284 +#define CLK_NPU_PVTM 285 +#define CLK_CORE_NPU_PVTM 286 +#define ACLK_NPU0 287 +#define HCLK_NPU0 288 +#define HCLK_NPU_ROOT 289 +#define CLK_NPU_DSU0 290 +#define PCLK_NPU_ROOT 291 +#define PCLK_NPU_TIMER 292 +#define CLK_NPUTIMER_ROOT 293 +#define CLK_NPUTIMER0 294 +#define CLK_NPUTIMER1 295 +#define PCLK_NPU_WDT 296 +#define TCLK_NPU_WDT 297 +#define HCLK_EMMC 298 +#define ACLK_EMMC 299 +#define CCLK_EMMC 300 +#define BCLK_EMMC 301 +#define TMCLK_EMMC 302 +#define SCLK_SFC 303 +#define HCLK_SFC 304 +#define HCLK_SFC_XIP 305 +#define HCLK_NVM_ROOT 306 +#define ACLK_NVM_ROOT 307 +#define CLK_GMAC0_PTP_REF 308 +#define CLK_GMAC1_PTP_REF 309 +#define CLK_GMAC_125M 310 +#define CLK_GMAC_50M 311 +#define ACLK_PHP_GIC_ITS 312 +#define ACLK_MMU_PCIE 313 +#define ACLK_MMU_PHP 314 +#define ACLK_PCIE_4L_DBI 315 +#define ACLK_PCIE_2L_DBI 316 +#define ACLK_PCIE_1L0_DBI 317 +#define ACLK_PCIE_1L1_DBI 318 +#define ACLK_PCIE_1L2_DBI 319 +#define ACLK_PCIE_4L_MSTR 320 +#define ACLK_PCIE_2L_MSTR 321 +#define ACLK_PCIE_1L0_MSTR 322 +#define ACLK_PCIE_1L1_MSTR 323 +#define ACLK_PCIE_1L2_MSTR 324 +#define ACLK_PCIE_4L_SLV 325 +#define ACLK_PCIE_2L_SLV 326 +#define ACLK_PCIE_1L0_SLV 327 +#define ACLK_PCIE_1L1_SLV 328 +#define ACLK_PCIE_1L2_SLV 329 +#define PCLK_PCIE_4L 330 +#define PCLK_PCIE_2L 331 +#define PCLK_PCIE_1L0 332 +#define PCLK_PCIE_1L1 333 +#define PCLK_PCIE_1L2 334 +#define CLK_PCIE_AUX0 335 +#define CLK_PCIE_AUX1 336 +#define CLK_PCIE_AUX2 337 +#define CLK_PCIE_AUX3 338 +#define CLK_PCIE_AUX4 339 +#define CLK_PIPEPHY0_REF 340 +#define CLK_PIPEPHY1_REF 341 +#define CLK_PIPEPHY2_REF 342 +#define PCLK_PHP_ROOT 343 +#define PCLK_GMAC0 344 +#define PCLK_GMAC1 345 +#define ACLK_PCIE_ROOT 346 +#define ACLK_PHP_ROOT 347 +#define ACLK_PCIE_BRIDGE 348 +#define ACLK_GMAC0 349 +#define ACLK_GMAC1 350 +#define CLK_PMALIVE0 351 +#define CLK_PMALIVE1 352 +#define CLK_PMALIVE2 353 +#define ACLK_SATA0 354 +#define ACLK_SATA1 355 +#define ACLK_SATA2 356 +#define CLK_RXOOB0 357 +#define CLK_RXOOB1 358 +#define CLK_RXOOB2 359 +#define ACLK_USB3OTG2 360 +#define SUSPEND_CLK_USB3OTG2 361 +#define REF_CLK_USB3OTG2 362 +#define CLK_UTMI_OTG2 363 +#define CLK_PIPEPHY0_PIPE_G 364 +#define CLK_PIPEPHY1_PIPE_G 365 +#define CLK_PIPEPHY2_PIPE_G 366 +#define CLK_PIPEPHY0_PIPE_ASIC_G 367 +#define CLK_PIPEPHY1_PIPE_ASIC_G 368 +#define CLK_PIPEPHY2_PIPE_ASIC_G 369 +#define CLK_PIPEPHY2_PIPE_U3_G 370 +#define CLK_PCIE1L2_PIPE 371 +#define CLK_PCIE4L_PIPE 372 +#define CLK_PCIE2L_PIPE 373 +#define PCLK_PCIE_COMBO_PIPE_PHY0 374 +#define PCLK_PCIE_COMBO_PIPE_PHY1 375 +#define PCLK_PCIE_COMBO_PIPE_PHY2 376 +#define PCLK_PCIE_COMBO_PIPE_PHY 377 +#define HCLK_RGA3_1 378 +#define ACLK_RGA3_1 379 +#define CLK_RGA3_1_CORE 380 +#define ACLK_RGA3_ROOT 381 +#define HCLK_RGA3_ROOT 382 +#define ACLK_RKVDEC_CCU 383 +#define HCLK_RKVDEC0 384 +#define ACLK_RKVDEC0 385 +#define CLK_RKVDEC0_CA 386 +#define CLK_RKVDEC0_HEVC_CA 387 +#define CLK_RKVDEC0_CORE 388 +#define HCLK_RKVDEC1 389 +#define ACLK_RKVDEC1 390 +#define CLK_RKVDEC1_CA 391 +#define CLK_RKVDEC1_HEVC_CA 392 +#define CLK_RKVDEC1_CORE 393 +#define HCLK_SDIO 394 +#define CCLK_SRC_SDIO 395 +#define ACLK_USB_ROOT 396 +#define HCLK_USB_ROOT 397 +#define HCLK_HOST0 398 +#define HCLK_HOST_ARB0 399 +#define HCLK_HOST1 400 +#define HCLK_HOST_ARB1 401 +#define ACLK_USB3OTG0 402 +#define SUSPEND_CLK_USB3OTG0 403 +#define REF_CLK_USB3OTG0 404 +#define ACLK_USB3OTG1 405 +#define SUSPEND_CLK_USB3OTG1 406 +#define REF_CLK_USB3OTG1 407 +#define UTMI_OHCI_CLK48_HOST0 408 +#define UTMI_OHCI_CLK48_HOST1 409 +#define HCLK_IEP2P0 410 +#define ACLK_IEP2P0 411 +#define CLK_IEP2P0_CORE 412 +#define ACLK_JPEG_ENCODER0 413 +#define HCLK_JPEG_ENCODER0 414 +#define ACLK_JPEG_ENCODER1 415 +#define HCLK_JPEG_ENCODER1 416 +#define ACLK_JPEG_ENCODER2 417 +#define HCLK_JPEG_ENCODER2 418 +#define ACLK_JPEG_ENCODER3 419 +#define HCLK_JPEG_ENCODER3 420 +#define ACLK_JPEG_DECODER 421 +#define HCLK_JPEG_DECODER 422 +#define HCLK_RGA2 423 +#define ACLK_RGA2 424 +#define CLK_RGA2_CORE 425 +#define HCLK_RGA3_0 426 +#define ACLK_RGA3_0 427 +#define CLK_RGA3_0_CORE 428 +#define ACLK_VDPU_ROOT 429 +#define ACLK_VDPU_LOW_ROOT 430 +#define HCLK_VDPU_ROOT 431 +#define ACLK_JPEG_DECODER_ROOT 432 +#define ACLK_VPU 433 +#define HCLK_VPU 434 +#define HCLK_RKVENC0_ROOT 435 +#define ACLK_RKVENC0_ROOT 436 +#define HCLK_RKVENC0 437 +#define ACLK_RKVENC0 438 +#define CLK_RKVENC0_CORE 439 +#define HCLK_RKVENC1_ROOT 440 +#define ACLK_RKVENC1_ROOT 441 +#define HCLK_RKVENC1 442 +#define ACLK_RKVENC1 443 +#define CLK_RKVENC1_CORE 444 +#define ICLK_CSIHOST01 445 +#define ICLK_CSIHOST0 446 +#define ICLK_CSIHOST1 447 +#define PCLK_CSI_HOST_0 448 +#define PCLK_CSI_HOST_1 449 +#define PCLK_CSI_HOST_2 450 +#define PCLK_CSI_HOST_3 451 +#define PCLK_CSI_HOST_4 452 +#define PCLK_CSI_HOST_5 453 +#define ACLK_FISHEYE0 454 +#define HCLK_FISHEYE0 455 +#define CLK_FISHEYE0_CORE 456 +#define ACLK_FISHEYE1 457 +#define HCLK_FISHEYE1 458 +#define CLK_FISHEYE1_CORE 459 +#define CLK_ISP0_CORE 460 +#define CLK_ISP0_CORE_MARVIN 461 +#define CLK_ISP0_CORE_VICAP 462 +#define ACLK_ISP0 463 +#define HCLK_ISP0 464 +#define ACLK_VI_ROOT 465 +#define HCLK_VI_ROOT 466 +#define PCLK_VI_ROOT 467 +#define DCLK_VICAP 468 +#define ACLK_VICAP 469 +#define HCLK_VICAP 470 +#define PCLK_DP0 471 +#define PCLK_DP1 472 +#define PCLK_S_DP0 473 +#define PCLK_S_DP1 474 +#define CLK_DP0 475 +#define CLK_DP1 476 +#define HCLK_HDCP_KEY0 477 +#define ACLK_HDCP0 478 +#define HCLK_HDCP0 479 +#define PCLK_HDCP0 480 +#define HCLK_I2S4_8CH 481 +#define ACLK_TRNG0 482 +#define PCLK_TRNG0 483 +#define ACLK_VO0_ROOT 484 +#define HCLK_VO0_ROOT 485 +#define HCLK_VO0_S_ROOT 486 +#define PCLK_VO0_ROOT 487 +#define PCLK_VO0_S_ROOT 488 +#define PCLK_VO0GRF 489 +#define CLK_I2S4_8CH_TX_SRC 490 +#define CLK_I2S4_8CH_TX_FRAC 491 +#define MCLK_I2S4_8CH_TX 492 +#define CLK_I2S4_8CH_TX 493 +#define HCLK_I2S8_8CH 494 +#define CLK_I2S8_8CH_TX_SRC 495 +#define CLK_I2S8_8CH_TX_FRAC 496 +#define MCLK_I2S8_8CH_TX 497 +#define CLK_I2S8_8CH_TX 498 +#define HCLK_SPDIF2_DP0 499 +#define CLK_SPDIF2_DP0_SRC 500 +#define CLK_SPDIF2_DP0_FRAC 501 +#define MCLK_SPDIF2_DP0 502 +#define CLK_SPDIF2_DP0 503 +#define MCLK_SPDIF2 504 +#define HCLK_SPDIF5_DP1 505 +#define CLK_SPDIF5_DP1_SRC 506 +#define CLK_SPDIF5_DP1_FRAC 507 +#define MCLK_SPDIF5_DP1 508 +#define CLK_SPDIF5_DP1 509 +#define MCLK_SPDIF5 510 +#define PCLK_EDP0 511 +#define CLK_EDP0_24M 512 +#define CLK_EDP0_200M 513 +#define PCLK_EDP1 514 +#define CLK_EDP1_24M 515 +#define CLK_EDP1_200M 516 +#define HCLK_HDCP_KEY1 517 +#define ACLK_HDCP1 518 +#define HCLK_HDCP1 519 +#define PCLK_HDCP1 520 +#define ACLK_HDMIRX 521 +#define PCLK_HDMIRX 522 +#define CLK_HDMIRX_REF 523 +#define CLK_HDMIRX_AUD_SRC 524 +#define CLK_HDMIRX_AUD_FRAC 525 +#define CLK_HDMIRX_AUD 526 +#define CLK_HDMIRX_AUD_P_MUX 527 +#define PCLK_HDMITX0 528 +#define CLK_HDMITX0_EARC 529 +#define CLK_HDMITX0_REF 530 +#define PCLK_HDMITX1 531 +#define CLK_HDMITX1_EARC 532 +#define CLK_HDMITX1_REF 533 +#define CLK_HDMITRX_REFSRC 534 +#define ACLK_TRNG1 535 +#define PCLK_TRNG1 536 +#define ACLK_HDCP1_ROOT 537 +#define ACLK_HDMIRX_ROOT 538 +#define HCLK_VO1_ROOT 539 +#define HCLK_VO1_S_ROOT 540 +#define PCLK_VO1_ROOT 541 +#define PCLK_VO1_S_ROOT 542 +#define PCLK_S_EDP0 543 +#define PCLK_S_EDP1 544 +#define PCLK_S_HDMIRX 545 +#define HCLK_I2S10_8CH 546 +#define CLK_I2S10_8CH_RX_SRC 547 +#define CLK_I2S10_8CH_RX_FRAC 548 +#define CLK_I2S10_8CH_RX 549 +#define MCLK_I2S10_8CH_RX 550 +#define HCLK_I2S7_8CH 551 +#define CLK_I2S7_8CH_RX_SRC 552 +#define CLK_I2S7_8CH_RX_FRAC 553 +#define CLK_I2S7_8CH_RX 554 +#define MCLK_I2S7_8CH_RX 555 +#define HCLK_I2S9_8CH 556 +#define CLK_I2S9_8CH_RX_SRC 557 +#define CLK_I2S9_8CH_RX_FRAC 558 +#define CLK_I2S9_8CH_RX 559 +#define MCLK_I2S9_8CH_RX 560 +#define CLK_I2S5_8CH_TX_SRC 561 +#define CLK_I2S5_8CH_TX_FRAC 562 +#define CLK_I2S5_8CH_TX 563 +#define MCLK_I2S5_8CH_TX 564 +#define HCLK_I2S5_8CH 565 +#define CLK_I2S6_8CH_TX_SRC 566 +#define CLK_I2S6_8CH_TX_FRAC 567 +#define CLK_I2S6_8CH_TX 568 +#define MCLK_I2S6_8CH_TX 569 +#define CLK_I2S6_8CH_RX_SRC 570 +#define CLK_I2S6_8CH_RX_FRAC 571 +#define CLK_I2S6_8CH_RX 572 +#define MCLK_I2S6_8CH_RX 573 +#define I2S6_8CH_MCLKOUT 574 +#define HCLK_I2S6_8CH 575 +#define HCLK_SPDIF3 576 +#define CLK_SPDIF3_SRC 577 +#define CLK_SPDIF3_FRAC 578 +#define CLK_SPDIF3 579 +#define MCLK_SPDIF3 580 +#define HCLK_SPDIF4 581 +#define CLK_SPDIF4_SRC 582 +#define CLK_SPDIF4_FRAC 583 +#define CLK_SPDIF4 584 +#define MCLK_SPDIF4 585 +#define HCLK_SPDIFRX0 586 +#define MCLK_SPDIFRX0 587 +#define HCLK_SPDIFRX1 588 +#define MCLK_SPDIFRX1 589 +#define HCLK_SPDIFRX2 590 +#define MCLK_SPDIFRX2 591 +#define ACLK_VO1USB_TOP_ROOT 592 +#define HCLK_VO1USB_TOP_ROOT 593 +#define CLK_HDMIHDP0 594 +#define CLK_HDMIHDP1 595 +#define PCLK_HDPTX0 596 +#define PCLK_HDPTX1 597 +#define PCLK_USBDPPHY0 598 +#define PCLK_USBDPPHY1 599 +#define ACLK_VOP_ROOT 600 +#define ACLK_VOP_LOW_ROOT 601 +#define HCLK_VOP_ROOT 602 +#define PCLK_VOP_ROOT 603 +#define HCLK_VOP 604 +#define ACLK_VOP 605 +#define DCLK_VOP0_SRC 606 +#define DCLK_VOP1_SRC 607 +#define DCLK_VOP2_SRC 608 +#define DCLK_VOP0 609 +#define DCLK_VOP1 610 +#define DCLK_VOP2 611 +#define DCLK_VOP3 612 +#define PCLK_DSIHOST0 613 +#define PCLK_DSIHOST1 614 +#define CLK_DSIHOST0 615 +#define CLK_DSIHOST1 616 +#define CLK_VOP_PMU 617 +#define ACLK_VOP_DOBY 618 +#define ACLK_VOP_SUB_SRC 619 +#define CLK_USBDP_PHY0_IMMORTAL 620 +#define CLK_USBDP_PHY1_IMMORTAL 621 +#define CLK_PMU0 622 +#define PCLK_PMU0 623 +#define PCLK_PMU0IOC 624 +#define PCLK_GPIO0 625 +#define DBCLK_GPIO0 626 +#define PCLK_I2C0 627 +#define CLK_I2C0 628 +#define HCLK_I2S1_8CH 629 +#define CLK_I2S1_8CH_TX_SRC 630 +#define CLK_I2S1_8CH_TX_FRAC 631 +#define CLK_I2S1_8CH_TX 632 +#define MCLK_I2S1_8CH_TX 633 +#define CLK_I2S1_8CH_RX_SRC 634 +#define CLK_I2S1_8CH_RX_FRAC 635 +#define CLK_I2S1_8CH_RX 636 +#define MCLK_I2S1_8CH_RX 637 +#define I2S1_8CH_MCLKOUT 638 +#define CLK_PMU1_50M_SRC 639 +#define CLK_PMU1_100M_SRC 640 +#define CLK_PMU1_200M_SRC 641 +#define CLK_PMU1_300M_SRC 642 +#define CLK_PMU1_400M_SRC 643 +#define HCLK_PMU1_ROOT 644 +#define PCLK_PMU1_ROOT 645 +#define PCLK_PMU0_ROOT 646 +#define HCLK_PMU_CM0_ROOT 647 +#define PCLK_PMU1 648 +#define CLK_DDR_FAIL_SAFE 649 +#define CLK_PMU1 650 +#define HCLK_PDM0 651 +#define MCLK_PDM0 652 +#define HCLK_VAD 653 +#define FCLK_PMU_CM0_CORE 654 +#define CLK_PMU_CM0_RTC 655 +#define PCLK_PMU1_IOC 656 +#define PCLK_PMU1PWM 657 +#define CLK_PMU1PWM 658 +#define CLK_PMU1PWM_CAPTURE 659 +#define PCLK_PMU1TIMER 660 +#define CLK_PMU1TIMER_ROOT 661 +#define CLK_PMU1TIMER0 662 +#define CLK_PMU1TIMER1 663 +#define CLK_UART0_SRC 664 +#define CLK_UART0_FRAC 665 +#define CLK_UART0 666 +#define SCLK_UART0 667 +#define PCLK_UART0 668 +#define PCLK_PMU1WDT 669 +#define TCLK_PMU1WDT 670 +#define CLK_CR_PARA 671 +#define CLK_USB2PHY_HDPTXRXPHY_REF 672 +#define CLK_USBDPPHY_MIPIDCPPHY_REF 673 +#define CLK_REF_PIPE_PHY0_OSC_SRC 674 +#define CLK_REF_PIPE_PHY1_OSC_SRC 675 +#define CLK_REF_PIPE_PHY2_OSC_SRC 676 +#define CLK_REF_PIPE_PHY0_PLL_SRC 677 +#define CLK_REF_PIPE_PHY1_PLL_SRC 678 +#define CLK_REF_PIPE_PHY2_PLL_SRC 679 +#define CLK_REF_PIPE_PHY0 680 +#define CLK_REF_PIPE_PHY1 681 +#define CLK_REF_PIPE_PHY2 682 +#define SCLK_SDIO_DRV 683 +#define SCLK_SDIO_SAMPLE 684 +#define SCLK_SDMMC_DRV 685 +#define SCLK_SDMMC_SAMPLE 686 +#define CLK_PCIE1L0_PIPE 687 +#define CLK_PCIE1L1_PIPE 688 +#define CLK_BIGCORE0_PVTM 689 +#define CLK_CORE_BIGCORE0_PVTM 690 +#define CLK_BIGCORE1_PVTM 691 +#define CLK_CORE_BIGCORE1_PVTM 692 +#define CLK_LITCORE_PVTM 693 +#define CLK_CORE_LITCORE_PVTM 694 +#define CLK_AUX16M_0 695 +#define CLK_AUX16M_1 696 +#define CLK_PHY0_REF_ALT_P 697 +#define CLK_PHY0_REF_ALT_M 698 +#define CLK_PHY1_REF_ALT_P 699 +#define CLK_PHY1_REF_ALT_M 700 +#define ACLK_ISP1_PRE 701 +#define HCLK_ISP1_PRE 702 +#define HCLK_NVM 703 +#define ACLK_USB 704 +#define HCLK_USB 705 +#define ACLK_JPEG_DECODER_PRE 706 +#define ACLK_VDPU_LOW_PRE 707 +#define ACLK_RKVENC1_PRE 708 +#define HCLK_RKVENC1_PRE 709 +#define HCLK_RKVDEC0_PRE 710 +#define ACLK_RKVDEC0_PRE 711 +#define HCLK_RKVDEC1_PRE 712 +#define ACLK_RKVDEC1_PRE 713 +#define ACLK_HDCP0_PRE 714 +#define HCLK_VO0 715 +#define ACLK_HDCP1_PRE 716 +#define HCLK_VO1 717 +#define ACLK_AV1_PRE 718 +#define PCLK_AV1_PRE 719 +#define HCLK_SDIO_PRE 720 + +#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1) + +/* scmi-clocks indices */ + +#define SCMI_CLK_CPUL 0 +#define SCMI_CLK_DSU 1 +#define SCMI_CLK_CPUB01 2 +#define SCMI_CLK_CPUB23 3 +#define SCMI_CLK_DDR 4 +#define SCMI_CLK_GPU 5 +#define SCMI_CLK_NPU 6 +#define SCMI_CLK_SBUS 7 +#define SCMI_PCLK_SBUS 8 +#define SCMI_CCLK_SD 9 +#define SCMI_DCLK_SD 10 +#define SCMI_ACLK_SECURE_NS 11 +#define SCMI_HCLK_SECURE_NS 12 +#define SCMI_TCLK_WDT 13 +#define SCMI_KEYLADDER_CORE 14 +#define SCMI_KEYLADDER_RNG 15 +#define SCMI_ACLK_SECURE_S 16 +#define SCMI_HCLK_SECURE_S 17 +#define SCMI_PCLK_SECURE_S 18 +#define SCMI_CRYPTO_RNG 19 +#define SCMI_CRYPTO_CORE 20 +#define SCMI_CRYPTO_PKA 21 +#define SCMI_SPLL 22 +#define SCMI_HCLK_SD 23 + +#endif From 0a8eb7dae617a9537b9a64a6b14e63415c279eb5 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 18 Oct 2022 17:14:00 +0200 Subject: [PATCH 03/36] dt-bindings: reset: add rk3588 reset definitions Add reset ID defines for rk3588. Compared to the downstream bindings and previous rockchip generations this uses continous gapless reset IDs starting at 0 instead of register offsets as IDs. Thus all numbers are different between upstream and downstream, but I kept the names exactly the same. Co-Developed-by: Elaine Zhang Signed-off-by: Elaine Zhang Acked-by: Rob Herring Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-3-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- .../dt-bindings/reset/rockchip,rk3588-cru.h | 754 ++++++++++++++++++ 1 file changed, 754 insertions(+) create mode 100644 include/dt-bindings/reset/rockchip,rk3588-cru.h diff --git a/include/dt-bindings/reset/rockchip,rk3588-cru.h b/include/dt-bindings/reset/rockchip,rk3588-cru.h new file mode 100644 index 000000000000..738e56aead93 --- /dev/null +++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h @@ -0,0 +1,754 @@ +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +/* + * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Copyright (c) 2022 Collabora Ltd. + * + * Author: Elaine Zhang + * Author: Sebastian Reichel + */ + +#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H +#define _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H + +#define SRST_A_TOP_BIU 0 +#define SRST_P_TOP_BIU 1 +#define SRST_P_CSIPHY0 2 +#define SRST_CSIPHY0 3 +#define SRST_P_CSIPHY1 4 +#define SRST_CSIPHY1 5 +#define SRST_A_TOP_M500_BIU 6 + +#define SRST_A_TOP_M400_BIU 7 +#define SRST_A_TOP_S200_BIU 8 +#define SRST_A_TOP_S400_BIU 9 +#define SRST_A_TOP_M300_BIU 10 +#define SRST_USBDP_COMBO_PHY0_INIT 11 +#define SRST_USBDP_COMBO_PHY0_CMN 12 +#define SRST_USBDP_COMBO_PHY0_LANE 13 +#define SRST_USBDP_COMBO_PHY0_PCS 14 +#define SRST_USBDP_COMBO_PHY1_INIT 15 + +#define SRST_USBDP_COMBO_PHY1_CMN 16 +#define SRST_USBDP_COMBO_PHY1_LANE 17 +#define SRST_USBDP_COMBO_PHY1_PCS 18 +#define SRST_DCPHY0 19 +#define SRST_P_MIPI_DCPHY0 20 +#define SRST_P_MIPI_DCPHY0_GRF 21 + +#define SRST_DCPHY1 22 +#define SRST_P_MIPI_DCPHY1 23 +#define SRST_P_MIPI_DCPHY1_GRF 24 +#define SRST_P_APB2ASB_SLV_CDPHY 25 +#define SRST_P_APB2ASB_SLV_CSIPHY 26 +#define SRST_P_APB2ASB_SLV_VCCIO3_5 27 +#define SRST_P_APB2ASB_SLV_VCCIO6 28 +#define SRST_P_APB2ASB_SLV_EMMCIO 29 +#define SRST_P_APB2ASB_SLV_IOC_TOP 30 +#define SRST_P_APB2ASB_SLV_IOC_RIGHT 31 + +#define SRST_P_CRU 32 +#define SRST_A_CHANNEL_SECURE2VO1USB 33 +#define SRST_A_CHANNEL_SECURE2CENTER 34 +#define SRST_H_CHANNEL_SECURE2VO1USB 35 +#define SRST_H_CHANNEL_SECURE2CENTER 36 + +#define SRST_P_CHANNEL_SECURE2VO1USB 37 +#define SRST_P_CHANNEL_SECURE2CENTER 38 + +#define SRST_H_AUDIO_BIU 39 +#define SRST_P_AUDIO_BIU 40 +#define SRST_H_I2S0_8CH 41 +#define SRST_M_I2S0_8CH_TX 42 +#define SRST_M_I2S0_8CH_RX 43 +#define SRST_P_ACDCDIG 44 +#define SRST_H_I2S2_2CH 45 +#define SRST_H_I2S3_2CH 46 + +#define SRST_M_I2S2_2CH 47 +#define SRST_M_I2S3_2CH 48 +#define SRST_DAC_ACDCDIG 49 +#define SRST_H_SPDIF0 50 + +#define SRST_M_SPDIF0 51 +#define SRST_H_SPDIF1 52 +#define SRST_M_SPDIF1 53 +#define SRST_H_PDM1 54 +#define SRST_PDM1 55 + +#define SRST_A_BUS_BIU 56 +#define SRST_P_BUS_BIU 57 +#define SRST_A_GIC 58 +#define SRST_A_GIC_DBG 59 +#define SRST_A_DMAC0 60 +#define SRST_A_DMAC1 61 +#define SRST_A_DMAC2 62 +#define SRST_P_I2C1 63 +#define SRST_P_I2C2 64 +#define SRST_P_I2C3 65 +#define SRST_P_I2C4 66 +#define SRST_P_I2C5 67 +#define SRST_P_I2C6 68 +#define SRST_P_I2C7 69 +#define SRST_P_I2C8 70 + +#define SRST_I2C1 71 +#define SRST_I2C2 72 +#define SRST_I2C3 73 +#define SRST_I2C4 74 +#define SRST_I2C5 75 +#define SRST_I2C6 76 +#define SRST_I2C7 77 +#define SRST_I2C8 78 +#define SRST_P_CAN0 79 +#define SRST_CAN0 80 +#define SRST_P_CAN1 81 +#define SRST_CAN1 82 +#define SRST_P_CAN2 83 +#define SRST_CAN2 84 +#define SRST_P_SARADC 85 + +#define SRST_P_TSADC 86 +#define SRST_TSADC 87 +#define SRST_P_UART1 88 +#define SRST_P_UART2 89 +#define SRST_P_UART3 90 +#define SRST_P_UART4 91 +#define SRST_P_UART5 92 +#define SRST_P_UART6 93 +#define SRST_P_UART7 94 +#define SRST_P_UART8 95 +#define SRST_P_UART9 96 +#define SRST_S_UART1 97 + +#define SRST_S_UART2 98 +#define SRST_S_UART3 99 +#define SRST_S_UART4 100 +#define SRST_S_UART5 101 +#define SRST_S_UART6 102 +#define SRST_S_UART7 103 + +#define SRST_S_UART8 104 +#define SRST_S_UART9 105 +#define SRST_P_SPI0 106 +#define SRST_P_SPI1 107 +#define SRST_P_SPI2 108 +#define SRST_P_SPI3 109 +#define SRST_P_SPI4 110 +#define SRST_SPI0 111 +#define SRST_SPI1 112 +#define SRST_SPI2 113 +#define SRST_SPI3 114 +#define SRST_SPI4 115 + +#define SRST_P_WDT0 116 +#define SRST_T_WDT0 117 +#define SRST_P_SYS_GRF 118 +#define SRST_P_PWM1 119 +#define SRST_PWM1 120 +#define SRST_P_PWM2 121 +#define SRST_PWM2 122 +#define SRST_P_PWM3 123 +#define SRST_PWM3 124 +#define SRST_P_BUSTIMER0 125 +#define SRST_P_BUSTIMER1 126 +#define SRST_BUSTIMER0 127 + +#define SRST_BUSTIMER1 128 +#define SRST_BUSTIMER2 129 +#define SRST_BUSTIMER3 130 +#define SRST_BUSTIMER4 131 +#define SRST_BUSTIMER5 132 +#define SRST_BUSTIMER6 133 +#define SRST_BUSTIMER7 134 +#define SRST_BUSTIMER8 135 +#define SRST_BUSTIMER9 136 +#define SRST_BUSTIMER10 137 +#define SRST_BUSTIMER11 138 +#define SRST_P_MAILBOX0 139 +#define SRST_P_MAILBOX1 140 +#define SRST_P_MAILBOX2 141 +#define SRST_P_GPIO1 142 +#define SRST_GPIO1 143 + +#define SRST_P_GPIO2 144 +#define SRST_GPIO2 145 +#define SRST_P_GPIO3 146 +#define SRST_GPIO3 147 +#define SRST_P_GPIO4 148 +#define SRST_GPIO4 149 +#define SRST_A_DECOM 150 +#define SRST_P_DECOM 151 +#define SRST_D_DECOM 152 +#define SRST_P_TOP 153 +#define SRST_A_GICADB_GIC2CORE_BUS 154 +#define SRST_P_DFT2APB 155 +#define SRST_P_APB2ASB_MST_TOP 156 +#define SRST_P_APB2ASB_MST_CDPHY 157 +#define SRST_P_APB2ASB_MST_BOT_RIGHT 158 + +#define SRST_P_APB2ASB_MST_IOC_TOP 159 +#define SRST_P_APB2ASB_MST_IOC_RIGHT 160 +#define SRST_P_APB2ASB_MST_CSIPHY 161 +#define SRST_P_APB2ASB_MST_VCCIO3_5 162 +#define SRST_P_APB2ASB_MST_VCCIO6 163 +#define SRST_P_APB2ASB_MST_EMMCIO 164 +#define SRST_A_SPINLOCK 165 +#define SRST_P_OTPC_NS 166 +#define SRST_OTPC_NS 167 +#define SRST_OTPC_ARB 168 + +#define SRST_P_BUSIOC 169 +#define SRST_P_PMUCM0_INTMUX 170 +#define SRST_P_DDRCM0_INTMUX 171 + +#define SRST_P_DDR_DFICTL_CH0 172 +#define SRST_P_DDR_MON_CH0 173 +#define SRST_P_DDR_STANDBY_CH0 174 +#define SRST_P_DDR_UPCTL_CH0 175 +#define SRST_TM_DDR_MON_CH0 176 +#define SRST_P_DDR_GRF_CH01 177 +#define SRST_DFI_CH0 178 +#define SRST_SBR_CH0 179 +#define SRST_DDR_UPCTL_CH0 180 +#define SRST_DDR_DFICTL_CH0 181 +#define SRST_DDR_MON_CH0 182 +#define SRST_DDR_STANDBY_CH0 183 +#define SRST_A_DDR_UPCTL_CH0 184 +#define SRST_P_DDR_DFICTL_CH1 185 +#define SRST_P_DDR_MON_CH1 186 +#define SRST_P_DDR_STANDBY_CH1 187 + +#define SRST_P_DDR_UPCTL_CH1 188 +#define SRST_TM_DDR_MON_CH1 189 +#define SRST_DFI_CH1 190 +#define SRST_SBR_CH1 191 +#define SRST_DDR_UPCTL_CH1 192 +#define SRST_DDR_DFICTL_CH1 193 +#define SRST_DDR_MON_CH1 194 +#define SRST_DDR_STANDBY_CH1 195 +#define SRST_A_DDR_UPCTL_CH1 196 +#define SRST_A_DDR01_MSCH0 197 +#define SRST_A_DDR01_RS_MSCH0 198 +#define SRST_A_DDR01_FRS_MSCH0 199 + +#define SRST_A_DDR01_SCRAMBLE0 200 +#define SRST_A_DDR01_FRS_SCRAMBLE0 201 +#define SRST_A_DDR01_MSCH1 202 +#define SRST_A_DDR01_RS_MSCH1 203 +#define SRST_A_DDR01_FRS_MSCH1 204 +#define SRST_A_DDR01_SCRAMBLE1 205 +#define SRST_A_DDR01_FRS_SCRAMBLE1 206 +#define SRST_P_DDR01_MSCH0 207 +#define SRST_P_DDR01_MSCH1 208 + +#define SRST_P_DDR_DFICTL_CH2 209 +#define SRST_P_DDR_MON_CH2 210 +#define SRST_P_DDR_STANDBY_CH2 211 +#define SRST_P_DDR_UPCTL_CH2 212 +#define SRST_TM_DDR_MON_CH2 213 +#define SRST_P_DDR_GRF_CH23 214 +#define SRST_DFI_CH2 215 +#define SRST_SBR_CH2 216 +#define SRST_DDR_UPCTL_CH2 217 +#define SRST_DDR_DFICTL_CH2 218 +#define SRST_DDR_MON_CH2 219 +#define SRST_DDR_STANDBY_CH2 220 +#define SRST_A_DDR_UPCTL_CH2 221 +#define SRST_P_DDR_DFICTL_CH3 222 +#define SRST_P_DDR_MON_CH3 223 +#define SRST_P_DDR_STANDBY_CH3 224 + +#define SRST_P_DDR_UPCTL_CH3 225 +#define SRST_TM_DDR_MON_CH3 226 +#define SRST_DFI_CH3 227 +#define SRST_SBR_CH3 228 +#define SRST_DDR_UPCTL_CH3 229 +#define SRST_DDR_DFICTL_CH3 230 +#define SRST_DDR_MON_CH3 231 +#define SRST_DDR_STANDBY_CH3 232 +#define SRST_A_DDR_UPCTL_CH3 233 +#define SRST_A_DDR23_MSCH2 234 +#define SRST_A_DDR23_RS_MSCH2 235 +#define SRST_A_DDR23_FRS_MSCH2 236 + +#define SRST_A_DDR23_SCRAMBLE2 237 +#define SRST_A_DDR23_FRS_SCRAMBLE2 238 +#define SRST_A_DDR23_MSCH3 239 +#define SRST_A_DDR23_RS_MSCH3 240 +#define SRST_A_DDR23_FRS_MSCH3 241 +#define SRST_A_DDR23_SCRAMBLE3 242 +#define SRST_A_DDR23_FRS_SCRAMBLE3 243 +#define SRST_P_DDR23_MSCH2 244 +#define SRST_P_DDR23_MSCH3 245 + +#define SRST_ISP1 246 +#define SRST_ISP1_VICAP 247 +#define SRST_A_ISP1_BIU 248 +#define SRST_H_ISP1_BIU 249 + +#define SRST_A_RKNN1 250 +#define SRST_A_RKNN1_BIU 251 +#define SRST_H_RKNN1 252 +#define SRST_H_RKNN1_BIU 253 + +#define SRST_A_RKNN2 254 +#define SRST_A_RKNN2_BIU 255 +#define SRST_H_RKNN2 256 +#define SRST_H_RKNN2_BIU 257 + +#define SRST_A_RKNN_DSU0 258 +#define SRST_P_NPUTOP_BIU 259 +#define SRST_P_NPU_TIMER 260 +#define SRST_NPUTIMER0 261 +#define SRST_NPUTIMER1 262 +#define SRST_P_NPU_WDT 263 +#define SRST_T_NPU_WDT 264 +#define SRST_P_NPU_PVTM 265 +#define SRST_P_NPU_GRF 266 +#define SRST_NPU_PVTM 267 + +#define SRST_NPU_PVTPLL 268 +#define SRST_H_NPU_CM0_BIU 269 +#define SRST_F_NPU_CM0_CORE 270 +#define SRST_T_NPU_CM0_JTAG 271 +#define SRST_A_RKNN0 272 +#define SRST_A_RKNN0_BIU 273 +#define SRST_H_RKNN0 274 +#define SRST_H_RKNN0_BIU 275 + +#define SRST_H_NVM_BIU 276 +#define SRST_A_NVM_BIU 277 +#define SRST_H_EMMC 278 +#define SRST_A_EMMC 279 +#define SRST_C_EMMC 280 +#define SRST_B_EMMC 281 +#define SRST_T_EMMC 282 +#define SRST_S_SFC 283 +#define SRST_H_SFC 284 +#define SRST_H_SFC_XIP 285 + +#define SRST_P_GRF 286 +#define SRST_P_DEC_BIU 287 +#define SRST_P_PHP_BIU 288 +#define SRST_A_PCIE_GRIDGE 289 +#define SRST_A_PHP_BIU 290 +#define SRST_A_GMAC0 291 +#define SRST_A_GMAC1 292 +#define SRST_A_PCIE_BIU 293 +#define SRST_PCIE0_POWER_UP 294 +#define SRST_PCIE1_POWER_UP 295 +#define SRST_PCIE2_POWER_UP 296 + +#define SRST_PCIE3_POWER_UP 297 +#define SRST_PCIE4_POWER_UP 298 +#define SRST_P_PCIE0 299 +#define SRST_P_PCIE1 300 +#define SRST_P_PCIE2 301 +#define SRST_P_PCIE3 302 + +#define SRST_P_PCIE4 303 +#define SRST_A_PHP_GIC_ITS 304 +#define SRST_A_MMU_PCIE 305 +#define SRST_A_MMU_PHP 306 +#define SRST_A_MMU_BIU 307 + +#define SRST_A_USB3OTG2 308 + +#define SRST_PMALIVE0 309 +#define SRST_PMALIVE1 310 +#define SRST_PMALIVE2 311 +#define SRST_A_SATA0 312 +#define SRST_A_SATA1 313 +#define SRST_A_SATA2 314 +#define SRST_RXOOB0 315 +#define SRST_RXOOB1 316 +#define SRST_RXOOB2 317 +#define SRST_ASIC0 318 +#define SRST_ASIC1 319 +#define SRST_ASIC2 320 + +#define SRST_A_RKVDEC_CCU 321 +#define SRST_H_RKVDEC0 322 +#define SRST_A_RKVDEC0 323 +#define SRST_H_RKVDEC0_BIU 324 +#define SRST_A_RKVDEC0_BIU 325 +#define SRST_RKVDEC0_CA 326 +#define SRST_RKVDEC0_HEVC_CA 327 +#define SRST_RKVDEC0_CORE 328 + +#define SRST_H_RKVDEC1 329 +#define SRST_A_RKVDEC1 330 +#define SRST_H_RKVDEC1_BIU 331 +#define SRST_A_RKVDEC1_BIU 332 +#define SRST_RKVDEC1_CA 333 +#define SRST_RKVDEC1_HEVC_CA 334 +#define SRST_RKVDEC1_CORE 335 + +#define SRST_A_USB_BIU 336 +#define SRST_H_USB_BIU 337 +#define SRST_A_USB3OTG0 338 +#define SRST_A_USB3OTG1 339 +#define SRST_H_HOST0 340 +#define SRST_H_HOST_ARB0 341 +#define SRST_H_HOST1 342 +#define SRST_H_HOST_ARB1 343 +#define SRST_A_USB_GRF 344 +#define SRST_C_USB2P0_HOST0 345 + +#define SRST_C_USB2P0_HOST1 346 +#define SRST_HOST_UTMI0 347 +#define SRST_HOST_UTMI1 348 + +#define SRST_A_VDPU_BIU 349 +#define SRST_A_VDPU_LOW_BIU 350 +#define SRST_H_VDPU_BIU 351 +#define SRST_A_JPEG_DECODER_BIU 352 +#define SRST_A_VPU 353 +#define SRST_H_VPU 354 +#define SRST_A_JPEG_ENCODER0 355 +#define SRST_H_JPEG_ENCODER0 356 +#define SRST_A_JPEG_ENCODER1 357 +#define SRST_H_JPEG_ENCODER1 358 +#define SRST_A_JPEG_ENCODER2 359 +#define SRST_H_JPEG_ENCODER2 360 + +#define SRST_A_JPEG_ENCODER3 361 +#define SRST_H_JPEG_ENCODER3 362 +#define SRST_A_JPEG_DECODER 363 +#define SRST_H_JPEG_DECODER 364 +#define SRST_H_IEP2P0 365 +#define SRST_A_IEP2P0 366 +#define SRST_IEP2P0_CORE 367 +#define SRST_H_RGA2 368 +#define SRST_A_RGA2 369 +#define SRST_RGA2_CORE 370 +#define SRST_H_RGA3_0 371 +#define SRST_A_RGA3_0 372 +#define SRST_RGA3_0_CORE 373 + +#define SRST_H_RKVENC0_BIU 374 +#define SRST_A_RKVENC0_BIU 375 +#define SRST_H_RKVENC0 376 +#define SRST_A_RKVENC0 377 +#define SRST_RKVENC0_CORE 378 + +#define SRST_H_RKVENC1_BIU 379 +#define SRST_A_RKVENC1_BIU 380 +#define SRST_H_RKVENC1 381 +#define SRST_A_RKVENC1 382 +#define SRST_RKVENC1_CORE 383 + +#define SRST_A_VI_BIU 384 +#define SRST_H_VI_BIU 385 +#define SRST_P_VI_BIU 386 +#define SRST_D_VICAP 387 +#define SRST_A_VICAP 388 +#define SRST_H_VICAP 389 +#define SRST_ISP0 390 +#define SRST_ISP0_VICAP 391 + +#define SRST_FISHEYE0 392 +#define SRST_FISHEYE1 393 +#define SRST_P_CSI_HOST_0 394 +#define SRST_P_CSI_HOST_1 395 +#define SRST_P_CSI_HOST_2 396 +#define SRST_P_CSI_HOST_3 397 +#define SRST_P_CSI_HOST_4 398 +#define SRST_P_CSI_HOST_5 399 + +#define SRST_CSIHOST0_VICAP 400 +#define SRST_CSIHOST1_VICAP 401 +#define SRST_CSIHOST2_VICAP 402 +#define SRST_CSIHOST3_VICAP 403 +#define SRST_CSIHOST4_VICAP 404 +#define SRST_CSIHOST5_VICAP 405 +#define SRST_CIFIN 406 + +#define SRST_A_VOP_BIU 407 +#define SRST_A_VOP_LOW_BIU 408 +#define SRST_H_VOP_BIU 409 +#define SRST_P_VOP_BIU 410 +#define SRST_H_VOP 411 +#define SRST_A_VOP 412 +#define SRST_D_VOP0 413 +#define SRST_D_VOP2HDMI_BRIDGE0 414 +#define SRST_D_VOP2HDMI_BRIDGE1 415 + +#define SRST_D_VOP1 416 +#define SRST_D_VOP2 417 +#define SRST_D_VOP3 418 +#define SRST_P_VOPGRF 419 +#define SRST_P_DSIHOST0 420 +#define SRST_P_DSIHOST1 421 +#define SRST_DSIHOST0 422 +#define SRST_DSIHOST1 423 +#define SRST_VOP_PMU 424 +#define SRST_P_VOP_CHANNEL_BIU 425 + +#define SRST_H_VO0_BIU 426 +#define SRST_H_VO0_S_BIU 427 +#define SRST_P_VO0_BIU 428 +#define SRST_P_VO0_S_BIU 429 +#define SRST_A_HDCP0_BIU 430 +#define SRST_P_VO0GRF 431 +#define SRST_H_HDCP_KEY0 432 +#define SRST_A_HDCP0 433 +#define SRST_H_HDCP0 434 +#define SRST_HDCP0 435 + +#define SRST_P_TRNG0 436 +#define SRST_DP0 437 +#define SRST_DP1 438 +#define SRST_H_I2S4_8CH 439 +#define SRST_M_I2S4_8CH_TX 440 +#define SRST_H_I2S8_8CH 441 + +#define SRST_M_I2S8_8CH_TX 442 +#define SRST_H_SPDIF2_DP0 443 +#define SRST_M_SPDIF2_DP0 444 +#define SRST_H_SPDIF5_DP1 445 +#define SRST_M_SPDIF5_DP1 446 + +#define SRST_A_HDCP1_BIU 447 +#define SRST_A_VO1_BIU 448 +#define SRST_H_VOP1_BIU 449 +#define SRST_H_VOP1_S_BIU 450 +#define SRST_P_VOP1_BIU 451 +#define SRST_P_VO1GRF 452 +#define SRST_P_VO1_S_BIU 453 + +#define SRST_H_I2S7_8CH 454 +#define SRST_M_I2S7_8CH_RX 455 +#define SRST_H_HDCP_KEY1 456 +#define SRST_A_HDCP1 457 +#define SRST_H_HDCP1 458 +#define SRST_HDCP1 459 +#define SRST_P_TRNG1 460 +#define SRST_P_HDMITX0 461 + +#define SRST_HDMITX0_REF 462 +#define SRST_P_HDMITX1 463 +#define SRST_HDMITX1_REF 464 +#define SRST_A_HDMIRX 465 +#define SRST_P_HDMIRX 466 +#define SRST_HDMIRX_REF 467 + +#define SRST_P_EDP0 468 +#define SRST_EDP0_24M 469 +#define SRST_P_EDP1 470 +#define SRST_EDP1_24M 471 +#define SRST_M_I2S5_8CH_TX 472 +#define SRST_H_I2S5_8CH 473 +#define SRST_M_I2S6_8CH_TX 474 + +#define SRST_M_I2S6_8CH_RX 475 +#define SRST_H_I2S6_8CH 476 +#define SRST_H_SPDIF3 477 +#define SRST_M_SPDIF3 478 +#define SRST_H_SPDIF4 479 +#define SRST_M_SPDIF4 480 +#define SRST_H_SPDIFRX0 481 +#define SRST_M_SPDIFRX0 482 +#define SRST_H_SPDIFRX1 483 +#define SRST_M_SPDIFRX1 484 + +#define SRST_H_SPDIFRX2 485 +#define SRST_M_SPDIFRX2 486 +#define SRST_LINKSYM_HDMITXPHY0 487 +#define SRST_LINKSYM_HDMITXPHY1 488 +#define SRST_VO1_BRIDGE0 489 +#define SRST_VO1_BRIDGE1 490 + +#define SRST_H_I2S9_8CH 491 +#define SRST_M_I2S9_8CH_RX 492 +#define SRST_H_I2S10_8CH 493 +#define SRST_M_I2S10_8CH_RX 494 +#define SRST_P_S_HDMIRX 495 + +#define SRST_GPU 496 +#define SRST_SYS_GPU 497 +#define SRST_A_S_GPU_BIU 498 +#define SRST_A_M0_GPU_BIU 499 +#define SRST_A_M1_GPU_BIU 500 +#define SRST_A_M2_GPU_BIU 501 +#define SRST_A_M3_GPU_BIU 502 +#define SRST_P_GPU_BIU 503 +#define SRST_P_GPU_PVTM 504 + +#define SRST_GPU_PVTM 505 +#define SRST_P_GPU_GRF 506 +#define SRST_GPU_PVTPLL 507 +#define SRST_GPU_JTAG 508 + +#define SRST_A_AV1_BIU 509 +#define SRST_A_AV1 510 +#define SRST_P_AV1_BIU 511 +#define SRST_P_AV1 512 + +#define SRST_A_DDR_BIU 513 +#define SRST_A_DMA2DDR 514 +#define SRST_A_DDR_SHAREMEM 515 +#define SRST_A_DDR_SHAREMEM_BIU 516 +#define SRST_A_CENTER_S200_BIU 517 +#define SRST_A_CENTER_S400_BIU 518 +#define SRST_H_AHB2APB 519 +#define SRST_H_CENTER_BIU 520 +#define SRST_F_DDR_CM0_CORE 521 + +#define SRST_DDR_TIMER0 522 +#define SRST_DDR_TIMER1 523 +#define SRST_T_WDT_DDR 524 +#define SRST_T_DDR_CM0_JTAG 525 +#define SRST_P_CENTER_GRF 526 +#define SRST_P_AHB2APB 527 +#define SRST_P_WDT 528 +#define SRST_P_TIMER 529 +#define SRST_P_DMA2DDR 530 +#define SRST_P_SHAREMEM 531 +#define SRST_P_CENTER_BIU 532 +#define SRST_P_CENTER_CHANNEL_BIU 533 + +#define SRST_P_USBDPGRF0 534 +#define SRST_P_USBDPPHY0 535 +#define SRST_P_USBDPGRF1 536 +#define SRST_P_USBDPPHY1 537 +#define SRST_P_HDPTX0 538 +#define SRST_P_HDPTX1 539 +#define SRST_P_APB2ASB_SLV_BOT_RIGHT 540 +#define SRST_P_USB2PHY_U3_0_GRF0 541 +#define SRST_P_USB2PHY_U3_1_GRF0 542 +#define SRST_P_USB2PHY_U2_0_GRF0 543 +#define SRST_P_USB2PHY_U2_1_GRF0 544 +#define SRST_HDPTX0_ROPLL 545 +#define SRST_HDPTX0_LCPLL 546 +#define SRST_HDPTX0 547 +#define SRST_HDPTX1_ROPLL 548 + +#define SRST_HDPTX1_LCPLL 549 +#define SRST_HDPTX1 550 +#define SRST_HDPTX0_HDMIRXPHY_SET 551 +#define SRST_USBDP_COMBO_PHY0 552 +#define SRST_USBDP_COMBO_PHY0_LCPLL 553 +#define SRST_USBDP_COMBO_PHY0_ROPLL 554 +#define SRST_USBDP_COMBO_PHY0_PCS_HS 555 +#define SRST_USBDP_COMBO_PHY1 556 +#define SRST_USBDP_COMBO_PHY1_LCPLL 557 +#define SRST_USBDP_COMBO_PHY1_ROPLL 558 +#define SRST_USBDP_COMBO_PHY1_PCS_HS 559 +#define SRST_HDMIHDP0 560 +#define SRST_HDMIHDP1 561 + +#define SRST_A_VO1USB_TOP_BIU 562 +#define SRST_H_VO1USB_TOP_BIU 563 + +#define SRST_H_SDIO_BIU 564 +#define SRST_H_SDIO 565 +#define SRST_SDIO 566 + +#define SRST_H_RGA3_BIU 567 +#define SRST_A_RGA3_BIU 568 +#define SRST_H_RGA3_1 569 +#define SRST_A_RGA3_1 570 +#define SRST_RGA3_1_CORE 571 + +#define SRST_REF_PIPE_PHY0 572 +#define SRST_REF_PIPE_PHY1 573 +#define SRST_REF_PIPE_PHY2 574 + +#define SRST_P_PHPTOP_CRU 575 +#define SRST_P_PCIE2_GRF0 576 +#define SRST_P_PCIE2_GRF1 577 +#define SRST_P_PCIE2_GRF2 578 +#define SRST_P_PCIE2_PHY0 579 +#define SRST_P_PCIE2_PHY1 580 +#define SRST_P_PCIE2_PHY2 581 +#define SRST_P_PCIE3_PHY 582 +#define SRST_P_APB2ASB_SLV_CHIP_TOP 583 +#define SRST_PCIE30_PHY 584 + +#define SRST_H_PMU1_BIU 585 +#define SRST_P_PMU1_BIU 586 +#define SRST_H_PMU_CM0_BIU 587 +#define SRST_F_PMU_CM0_CORE 588 +#define SRST_T_PMU1_CM0_JTAG 589 + +#define SRST_DDR_FAIL_SAFE 590 +#define SRST_P_CRU_PMU1 591 +#define SRST_P_PMU1_GRF 592 +#define SRST_P_PMU1_IOC 593 +#define SRST_P_PMU1WDT 594 +#define SRST_T_PMU1WDT 595 +#define SRST_P_PMU1TIMER 596 +#define SRST_PMU1TIMER0 597 +#define SRST_PMU1TIMER1 598 +#define SRST_P_PMU1PWM 599 +#define SRST_PMU1PWM 600 + +#define SRST_P_I2C0 601 +#define SRST_I2C0 602 +#define SRST_S_UART0 603 +#define SRST_P_UART0 604 +#define SRST_H_I2S1_8CH 605 +#define SRST_M_I2S1_8CH_TX 606 +#define SRST_M_I2S1_8CH_RX 607 +#define SRST_H_PDM0 608 +#define SRST_PDM0 609 + +#define SRST_H_VAD 610 +#define SRST_HDPTX0_INIT 611 +#define SRST_HDPTX0_CMN 612 +#define SRST_HDPTX0_LANE 613 +#define SRST_HDPTX1_INIT 614 + +#define SRST_HDPTX1_CMN 615 +#define SRST_HDPTX1_LANE 616 +#define SRST_M_MIPI_DCPHY0 617 +#define SRST_S_MIPI_DCPHY0 618 +#define SRST_M_MIPI_DCPHY1 619 +#define SRST_S_MIPI_DCPHY1 620 +#define SRST_OTGPHY_U3_0 621 +#define SRST_OTGPHY_U3_1 622 +#define SRST_OTGPHY_U2_0 623 +#define SRST_OTGPHY_U2_1 624 + +#define SRST_P_PMU0GRF 625 +#define SRST_P_PMU0IOC 626 +#define SRST_P_GPIO0 627 +#define SRST_GPIO0 628 + +#define SRST_A_SECURE_NS_BIU 629 +#define SRST_H_SECURE_NS_BIU 630 +#define SRST_A_SECURE_S_BIU 631 +#define SRST_H_SECURE_S_BIU 632 +#define SRST_P_SECURE_S_BIU 633 +#define SRST_CRYPTO_CORE 634 + +#define SRST_CRYPTO_PKA 635 +#define SRST_CRYPTO_RNG 636 +#define SRST_A_CRYPTO 637 +#define SRST_H_CRYPTO 638 +#define SRST_KEYLADDER_CORE 639 +#define SRST_KEYLADDER_RNG 640 +#define SRST_A_KEYLADDER 641 +#define SRST_H_KEYLADDER 642 +#define SRST_P_OTPC_S 643 +#define SRST_OTPC_S 644 +#define SRST_WDT_S 645 + +#define SRST_T_WDT_S 646 +#define SRST_H_BOOTROM 647 +#define SRST_A_DCF 648 +#define SRST_P_DCF 649 +#define SRST_H_BOOTROM_NS 650 +#define SRST_P_KEYLADDER 651 +#define SRST_H_TRNG_S 652 + +#define SRST_H_TRNG_NS 653 +#define SRST_D_SDMMC_BUFFER 654 +#define SRST_H_SDMMC 655 +#define SRST_H_SDMMC_BUFFER 656 +#define SRST_SDMMC 657 +#define SRST_P_TRNG_CHK 658 +#define SRST_TRNG_S 659 + +#endif From 4f5ca304f202938a07eb0c2e20551795286d817d Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 18 Oct 2022 17:14:01 +0200 Subject: [PATCH 04/36] dt-bindings: clock: add rk3588 cru bindings Document the device tree bindings of the rockchip rk3588 SoC clock and reset unit. Signed-off-by: Elaine Zhang Reviewed-by: Rob Herring Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-4-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- .../bindings/clock/rockchip,rk3588-cru.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml new file mode 100644 index 000000000000..74cd3f3f229a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3588-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip rk3588 Family Clock and Reset Control Module + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +description: | + The RK3588 clock controller generates the clock and also implements a reset + controller for SoC peripherals. For example it provides SCLK_UART2 and + PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART + module. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clock and reset IDs + are defined as preprocessor macros in dt-binding headers. + +properties: + compatible: + enum: + - rockchip,rk3588-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: xin24m + - const: xin32k + + assigned-clocks: true + + assigned-clock-rates: true + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: > + phandle to the syscon managing the "general register files". It is used + for GRF muxes, if missing any muxes present in the GRF will not be + available. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@fd7c0000 { + compatible = "rockchip,rk3588-cru"; + reg = <0xfd7c0000 0x5c000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; From cf87691f143e6cc5727767b02ec2be3725534a5d Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 18 Oct 2022 17:14:02 +0200 Subject: [PATCH 05/36] clk: rockchip: add register offset of the cores select parent The cores select parent register is special on RK3588. Signed-off-by: Elaine Zhang Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-5-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-cpu.c | 28 ++++++++++++++++++++-------- drivers/clk/rockchip/clk.h | 3 +++ 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index 47288197c9d7..11aa2259b532 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -166,10 +166,16 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, } } /* select alternate parent */ - writel(HIWORD_UPDATE(reg_data->mux_core_alt, - reg_data->mux_core_mask, - reg_data->mux_core_shift), - cpuclk->reg_base + reg_data->core_reg[0]); + if (reg_data->mux_core_reg) + writel(HIWORD_UPDATE(reg_data->mux_core_alt, + reg_data->mux_core_mask, + reg_data->mux_core_shift), + cpuclk->reg_base + reg_data->mux_core_reg); + else + writel(HIWORD_UPDATE(reg_data->mux_core_alt, + reg_data->mux_core_mask, + reg_data->mux_core_shift), + cpuclk->reg_base + reg_data->core_reg[0]); spin_unlock_irqrestore(cpuclk->lock, flags); return 0; @@ -202,10 +208,16 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk, * primary parent by the extra dividers that were needed for the alt. */ - writel(HIWORD_UPDATE(reg_data->mux_core_main, - reg_data->mux_core_mask, - reg_data->mux_core_shift), - cpuclk->reg_base + reg_data->core_reg[0]); + if (reg_data->mux_core_reg) + writel(HIWORD_UPDATE(reg_data->mux_core_main, + reg_data->mux_core_mask, + reg_data->mux_core_shift), + cpuclk->reg_base + reg_data->mux_core_reg); + else + writel(HIWORD_UPDATE(reg_data->mux_core_main, + reg_data->mux_core_mask, + reg_data->mux_core_shift), + cpuclk->reg_base + reg_data->core_reg[0]); /* remove dividers */ for (i = 0; i < reg_data->num_cores; i++) { diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index ee01739e4a7c..43a37a43b6f3 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -389,6 +389,8 @@ struct rockchip_cpuclk_rate_table { * @div_core_shift[]: cores divider offset used to divide the pll value * @div_core_mask[]: cores divider mask * @num_cores: number of cpu cores + * @mux_core_reg: register offset of the cores select parent + * @mux_core_alt: mux value to select alternate parent * @mux_core_main: mux value to select main parent of core * @mux_core_shift: offset of the core multiplexer * @mux_core_mask: core multiplexer mask @@ -398,6 +400,7 @@ struct rockchip_cpuclk_reg_data { u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES]; u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES]; int num_cores; + int mux_core_reg; u8 mux_core_alt; u8 mux_core_main; u8 mux_core_shift; From 8f6594494b1cb0ad14493795b436413cfe64a0f8 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 18 Oct 2022 17:14:03 +0200 Subject: [PATCH 06/36] clk: rockchip: add pll type for RK3588 Add RK3588 PLL support fully relying on lookup tables like the other upstream supported rockchip platforms. Signed-off-by: Elaine Zhang [rebase and modify code to avoid PLL parameter calculation] Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-6-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-pll.c | 218 ++++++++++++++++++++++++++++++++- drivers/clk/rockchip/clk.h | 18 +++ 2 files changed, 235 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index f7827b3b7fc1..4b9840994295 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -842,6 +842,213 @@ static const struct clk_ops rockchip_rk3399_pll_clk_ops = { .init = rockchip_rk3399_pll_init, }; +/* + * PLL used in RK3588 + */ + +#define RK3588_PLLCON(i) (i * 0x4) +#define RK3588_PLLCON0_M_MASK 0x3ff +#define RK3588_PLLCON0_M_SHIFT 0 +#define RK3588_PLLCON1_P_MASK 0x3f +#define RK3588_PLLCON1_P_SHIFT 0 +#define RK3588_PLLCON1_S_MASK 0x7 +#define RK3588_PLLCON1_S_SHIFT 6 +#define RK3588_PLLCON2_K_MASK 0xffff +#define RK3588_PLLCON2_K_SHIFT 0 +#define RK3588_PLLCON1_PWRDOWN BIT(13) +#define RK3588_PLLCON6_LOCK_STATUS BIT(15) + +static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll) +{ + u32 pllcon; + int ret; + + /* + * Lock time typical 250, max 500 input clock cycles @24MHz + * So define a very safe maximum of 1000us, meaning 24000 cycles. + */ + ret = readl_relaxed_poll_timeout(pll->reg_base + RK3588_PLLCON(6), + pllcon, + pllcon & RK3588_PLLCON6_LOCK_STATUS, + 0, 1000); + if (ret) + pr_err("%s: timeout waiting for pll to lock\n", __func__); + + return ret; +} + +static void rockchip_rk3588_pll_get_params(struct rockchip_clk_pll *pll, + struct rockchip_pll_rate_table *rate) +{ + u32 pllcon; + + pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(0)); + rate->m = ((pllcon >> RK3588_PLLCON0_M_SHIFT) & RK3588_PLLCON0_M_MASK); + + pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(1)); + rate->p = ((pllcon >> RK3588_PLLCON1_P_SHIFT) & RK3588_PLLCON1_P_MASK); + rate->s = ((pllcon >> RK3588_PLLCON1_S_SHIFT) & RK3588_PLLCON1_S_MASK); + + pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(2)); + rate->k = ((pllcon >> RK3588_PLLCON2_K_SHIFT) & RK3588_PLLCON2_K_MASK); +} + +static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + struct rockchip_pll_rate_table cur; + u64 rate64 = prate, postdiv; + + rockchip_rk3588_pll_get_params(pll, &cur); + + rate64 *= cur.m; + do_div(rate64, cur.p); + + if (cur.k) { + /* fractional mode */ + u64 frac_rate64 = prate * cur.k; + + postdiv = cur.p * 65535; + do_div(frac_rate64, postdiv); + rate64 += frac_rate64; + } + rate64 = rate64 >> cur.s; + + return (unsigned long)rate64; +} + +static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll, + const struct rockchip_pll_rate_table *rate) +{ + const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; + struct clk_mux *pll_mux = &pll->pll_mux; + struct rockchip_pll_rate_table cur; + int rate_change_remuxed = 0; + int cur_parent; + int ret; + + pr_debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n", + __func__, rate->rate, rate->p, rate->m, rate->s, rate->k); + + rockchip_rk3588_pll_get_params(pll, &cur); + cur.rate = 0; + + if (pll->type == pll_rk3588) { + cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); + if (cur_parent == PLL_MODE_NORM) { + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); + rate_change_remuxed = 1; + } + } + + /* set pll power down */ + writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN, + RK3588_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3399_PLLCON(1)); + + /* update pll values */ + writel_relaxed(HIWORD_UPDATE(rate->m, RK3588_PLLCON0_M_MASK, RK3588_PLLCON0_M_SHIFT), + pll->reg_base + RK3399_PLLCON(0)); + + writel_relaxed(HIWORD_UPDATE(rate->p, RK3588_PLLCON1_P_MASK, RK3588_PLLCON1_P_SHIFT) | + HIWORD_UPDATE(rate->s, RK3588_PLLCON1_S_MASK, RK3588_PLLCON1_S_SHIFT), + pll->reg_base + RK3399_PLLCON(1)); + + writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, RK3588_PLLCON2_K_SHIFT), + pll->reg_base + RK3399_PLLCON(2)); + + /* set pll power up */ + writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3588_PLLCON(1)); + + /* wait for the pll to lock */ + ret = rockchip_rk3588_pll_wait_lock(pll); + if (ret) { + pr_warn("%s: pll update unsuccessful, trying to restore old params\n", + __func__); + rockchip_rk3588_pll_set_params(pll, &cur); + } + + if ((pll->type == pll_rk3588) && rate_change_remuxed) + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); + + return ret; +} + +static int rockchip_rk3588_pll_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; + + pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", + __func__, __clk_get_name(hw->clk), drate, prate); + + /* Get required rate settings from table */ + rate = rockchip_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + return rockchip_rk3588_pll_set_params(pll, rate); +} + +static int rockchip_rk3588_pll_enable(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + + writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3588_PLLCON(1)); + rockchip_rk3588_pll_wait_lock(pll); + + return 0; +} + +static void rockchip_rk3588_pll_disable(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + + writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN, RK3588_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3588_PLLCON(1)); +} + +static int rockchip_rk3588_pll_is_enabled(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + u32 pllcon = readl(pll->reg_base + RK3588_PLLCON(1)); + + return !(pllcon & RK3588_PLLCON1_PWRDOWN); +} + +static int rockchip_rk3588_pll_init(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + + if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) + return 0; + + return 0; +} + +static const struct clk_ops rockchip_rk3588_pll_clk_norate_ops = { + .recalc_rate = rockchip_rk3588_pll_recalc_rate, + .enable = rockchip_rk3588_pll_enable, + .disable = rockchip_rk3588_pll_disable, + .is_enabled = rockchip_rk3588_pll_is_enabled, +}; + +static const struct clk_ops rockchip_rk3588_pll_clk_ops = { + .recalc_rate = rockchip_rk3588_pll_recalc_rate, + .round_rate = rockchip_pll_round_rate, + .set_rate = rockchip_rk3588_pll_set_rate, + .enable = rockchip_rk3588_pll_enable, + .disable = rockchip_rk3588_pll_disable, + .is_enabled = rockchip_rk3588_pll_is_enabled, + .init = rockchip_rk3588_pll_init, +}; + /* * Common registering of pll clocks */ @@ -890,7 +1097,8 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, if (pll_type == pll_rk3036 || pll_type == pll_rk3066 || pll_type == pll_rk3328 || - pll_type == pll_rk3399) + pll_type == pll_rk3399 || + pll_type == pll_rk3588) pll_mux->flags |= CLK_MUX_HIWORD_MASK; /* the actual muxing is xin24m, pll-output, xin32k */ @@ -957,6 +1165,14 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, else init.ops = &rockchip_rk3399_pll_clk_ops; break; + case pll_rk3588: + case pll_rk3588_core: + if (!pll->rate_table) + init.ops = &rockchip_rk3588_pll_clk_norate_ops; + else + init.ops = &rockchip_rk3588_pll_clk_ops; + init.flags = flags; + break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, name); diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 43a37a43b6f3..6eb31d36c4cd 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -240,6 +240,8 @@ enum rockchip_pll_type { pll_rk3066, pll_rk3328, pll_rk3399, + pll_rk3588, + pll_rk3588_core, }; #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ @@ -272,6 +274,15 @@ enum rockchip_pll_type { .nb = _nb, \ } +#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \ +{ \ + .rate = _rate##U, \ + .p = _p, \ + .m = _m, \ + .s = _s, \ + .k = _k, \ +} + /** * struct rockchip_clk_provider - information about clock provider * @reg_base: virtual address for the register base. @@ -307,6 +318,13 @@ struct rockchip_pll_rate_table { unsigned int dsmpd; unsigned int frac; }; + struct { + /* for RK3588 */ + unsigned int m; + unsigned int p; + unsigned int s; + unsigned int k; + }; }; }; From 2004b7b1803719eaaaee5fa6b089b1699a65d31d Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 18 Oct 2022 17:14:04 +0200 Subject: [PATCH 07/36] clk: rockchip: allow additional mux options for cpu-clock frequency changes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order to improve the main frequency of CPU, the clock path of CPU is simplified as follows: |--\ | \ |--\ --apll--|\ | \ | \ | |--apll_core--| \ | \ --24M---|/ |mux1 |--[gate]--|mux2|---clk_core | / | / --gpll--|\ | / |------| / | |--gpll_core--| / | |--/ --24M---|/ |--/ | | -------apll_directly--------------| When the CPU requests high frequency, we want to use MUX2 select the "apll_directly". At low frequencies use MUX1 to select “apll_core" and then MUX2 to select "apll_core_gate". However, in this way, the CPU frequency conversion needs to be in the following order: 1. MUX2 select to "apll_core_gate", MUX1 select "gpll_core" 2. Apll sets slow_mode, sets APLL parameters, locks APLL, and then APLL sets normal_mode 3. MUX1 select "apll_core", MUX2 select "apll_directly" So add pre_mux and post_mux options to cover this special requirements. Signed-off-by: Elaine Zhang [rebase] Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-7-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-cpu.c | 41 ++++++++++++++++++++++++++++++++++ drivers/clk/rockchip/clk.h | 2 ++ 2 files changed, 43 insertions(+) diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index 11aa2259b532..6ea7fba9f9e5 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -113,6 +113,42 @@ static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk, } } +static void rockchip_cpuclk_set_pre_muxs(struct rockchip_cpuclk *cpuclk, + const struct rockchip_cpuclk_rate_table *rate) +{ + int i; + + /* alternate parent is active now. set the pre_muxs */ + for (i = 0; i < ARRAY_SIZE(rate->pre_muxs); i++) { + const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i]; + + if (!clksel->reg) + break; + + pr_debug("%s: setting reg 0x%x to 0x%x\n", + __func__, clksel->reg, clksel->val); + writel(clksel->val, cpuclk->reg_base + clksel->reg); + } +} + +static void rockchip_cpuclk_set_post_muxs(struct rockchip_cpuclk *cpuclk, + const struct rockchip_cpuclk_rate_table *rate) +{ + int i; + + /* alternate parent is active now. set the muxs */ + for (i = 0; i < ARRAY_SIZE(rate->post_muxs); i++) { + const struct rockchip_cpuclk_clksel *clksel = &rate->post_muxs[i]; + + if (!clksel->reg) + break; + + pr_debug("%s: setting reg 0x%x to 0x%x\n", + __func__, clksel->reg, clksel->val); + writel(clksel->val, cpuclk->reg_base + clksel->reg); + } +} + static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, struct clk_notifier_data *ndata) { @@ -165,6 +201,9 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, cpuclk->reg_base + reg_data->core_reg[i]); } } + + rockchip_cpuclk_set_pre_muxs(cpuclk, rate); + /* select alternate parent */ if (reg_data->mux_core_reg) writel(HIWORD_UPDATE(reg_data->mux_core_alt, @@ -219,6 +258,8 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk, reg_data->mux_core_shift), cpuclk->reg_base + reg_data->core_reg[0]); + rockchip_cpuclk_set_post_muxs(cpuclk, rate); + /* remove dividers */ for (i = 0; i < reg_data->num_cores; i++) { writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i], diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 6eb31d36c4cd..24d3e56d3f71 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -399,6 +399,8 @@ struct rockchip_cpuclk_clksel { struct rockchip_cpuclk_rate_table { unsigned long prate; struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; + struct rockchip_cpuclk_clksel pre_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; + struct rockchip_cpuclk_clksel post_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; }; /** From ff94c8660dac444081f2f650fae36a283c55b117 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 18 Oct 2022 17:14:05 +0200 Subject: [PATCH 08/36] clk: rockchip: simplify rockchip_clk_add_lookup rockchip_clk_add_lookup is only called from within the file, so it can be made static. The additional checks are removed with the following reasoning: 1. The data structure is initialized by rockchip_clk_init(), which is called by all rockchip platforms before the clocks are registered. Not doing so would result in an incomplete clock tree at the moment, which is a fatal error. In other parts of the kernel these kind of checks are usually omitted, so this was done here. The alternative is adding a pr_err to inform the kernel programmer adding a new platform about his incorrect code. Apart from that we are also not checking if the clock id is within the array boundings. 2. While not used so far by any rockchip platform, 0 is a valid clock identifier. To align rockchip closer to other ARM platforms we will start using it with rk3588. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-8-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk.c | 14 ++++++-------- drivers/clk/rockchip/clk.h | 2 -- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index e63d4f20b479..1aed6f254ccd 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -198,6 +198,12 @@ static void rockchip_fractional_approximation(struct clk_hw *hw, clk_fractional_divider_general_approximation(hw, rate, parent_rate, m, n); } +static void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, + struct clk *clk, unsigned int id) +{ + ctx->clk_data.clks[id] = clk; +} + static struct clk *rockchip_clk_register_frac_branch( struct rockchip_clk_provider *ctx, const char *name, const char *const *parent_names, u8 num_parents, @@ -401,14 +407,6 @@ void rockchip_clk_of_add_provider(struct device_node *np, } EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider); -void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, - struct clk *clk, unsigned int id) -{ - if (ctx->clk_data.clks && id) - ctx->clk_data.clks[id] = clk; -} -EXPORT_SYMBOL_GPL(rockchip_clk_add_lookup); - void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, struct rockchip_pll_clock *list, unsigned int nr_pll, int grf_lock_offset) diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 24d3e56d3f71..6e84ab85b372 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -928,8 +928,6 @@ struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, void __iomem *base, unsigned long nr_clks); void rockchip_clk_of_add_provider(struct device_node *np, struct rockchip_clk_provider *ctx); -void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, - struct clk *clk, unsigned int id); void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, struct rockchip_clk_branch *list, unsigned int nr_clk); From ada8f95ba04e8fe07289b7de157ae99bb96bc8cb Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 18 Oct 2022 17:14:06 +0200 Subject: [PATCH 09/36] clk: rockchip: add lookup table support Add support for mapping reset IDs to register offsets to support gapless continous platform reset IDs. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-9-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk.h | 21 +++++++++++++++------ drivers/clk/rockchip/softrst.c | 34 +++++++++++++++++++++++++--------- 2 files changed, 40 insertions(+), 15 deletions(-) diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 6e84ab85b372..7ee231d9585d 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -958,15 +958,24 @@ struct clk *rockchip_clk_register_halfdiv(const char *name, spinlock_t *lock); #ifdef CONFIG_RESET_CONTROLLER -void rockchip_register_softrst(struct device_node *np, - unsigned int num_regs, - void __iomem *base, u8 flags); +void rockchip_register_softrst_lut(struct device_node *np, + const int *lookup_table, + unsigned int num_regs, + void __iomem *base, u8 flags); #else -static inline void rockchip_register_softrst(struct device_node *np, - unsigned int num_regs, - void __iomem *base, u8 flags) +static inline void rockchip_register_softrst_lut(struct device_node *np, + const int *lookup_table, + unsigned int num_regs, + void __iomem *base, u8 flags) { } #endif +static inline void rockchip_register_softrst(struct device_node *np, + unsigned int num_regs, + void __iomem *base, u8 flags) +{ + return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags); +} + #endif diff --git a/drivers/clk/rockchip/softrst.c b/drivers/clk/rockchip/softrst.c index 5d07266745b8..fd56aaefe6d1 100644 --- a/drivers/clk/rockchip/softrst.c +++ b/drivers/clk/rockchip/softrst.c @@ -12,6 +12,7 @@ struct rockchip_softrst { struct reset_controller_dev rcdev; + const int *lut; void __iomem *reg_base; int num_regs; int num_per_reg; @@ -25,8 +26,13 @@ static int rockchip_softrst_assert(struct reset_controller_dev *rcdev, struct rockchip_softrst *softrst = container_of(rcdev, struct rockchip_softrst, rcdev); - int bank = id / softrst->num_per_reg; - int offset = id % softrst->num_per_reg; + int bank, offset; + + if (softrst->lut) + id = softrst->lut[id]; + + bank = id / softrst->num_per_reg; + offset = id % softrst->num_per_reg; if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) { writel(BIT(offset) | (BIT(offset) << 16), @@ -52,8 +58,13 @@ static int rockchip_softrst_deassert(struct reset_controller_dev *rcdev, struct rockchip_softrst *softrst = container_of(rcdev, struct rockchip_softrst, rcdev); - int bank = id / softrst->num_per_reg; - int offset = id % softrst->num_per_reg; + int bank, offset; + + if (softrst->lut) + id = softrst->lut[id]; + + bank = id / softrst->num_per_reg; + offset = id % softrst->num_per_reg; if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) { writel((BIT(offset) << 16), softrst->reg_base + (bank * 4)); @@ -77,9 +88,10 @@ static const struct reset_control_ops rockchip_softrst_ops = { .deassert = rockchip_softrst_deassert, }; -void rockchip_register_softrst(struct device_node *np, - unsigned int num_regs, - void __iomem *base, u8 flags) +void rockchip_register_softrst_lut(struct device_node *np, + const int *lookup_table, + unsigned int num_regs, + void __iomem *base, u8 flags) { struct rockchip_softrst *softrst; int ret; @@ -91,13 +103,17 @@ void rockchip_register_softrst(struct device_node *np, spin_lock_init(&softrst->lock); softrst->reg_base = base; + softrst->lut = lookup_table; softrst->flags = flags; softrst->num_regs = num_regs; softrst->num_per_reg = (flags & ROCKCHIP_SOFTRST_HIWORD_MASK) ? 16 : 32; softrst->rcdev.owner = THIS_MODULE; - softrst->rcdev.nr_resets = num_regs * softrst->num_per_reg; + if (lookup_table) + softrst->rcdev.nr_resets = num_regs; + else + softrst->rcdev.nr_resets = num_regs * softrst->num_per_reg; softrst->rcdev.ops = &rockchip_softrst_ops; softrst->rcdev.of_node = np; ret = reset_controller_register(&softrst->rcdev); @@ -107,4 +123,4 @@ void rockchip_register_softrst(struct device_node *np, kfree(softrst); } }; -EXPORT_SYMBOL_GPL(rockchip_register_softrst); +EXPORT_SYMBOL_GPL(rockchip_register_softrst_lut); From f1c506d152ff235ad621d3c25d061cb16da67214 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 18 Oct 2022 17:14:07 +0200 Subject: [PATCH 10/36] clk: rockchip: add clock controller for the RK3588 Add full clock controller support RK3588. [rebase, integrate fixes from Wyon and Finley, add missing frequencies to PLL lookup table, update commit message, add GATE_LINK clocks which downstream handles in its own driver with one DT node per clock] Signed-off-by: Wyon Bi Signed-off-by: Finley Xiao Signed-off-by: Elaine Zhang Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-10-sebastian.reichel@collabora.com [dropped module stuff after talking to Sebastian] Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/Kconfig | 8 + drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-rk3588.c | 2533 +++++++++++++++++++++++++++++ drivers/clk/rockchip/clk.h | 49 +- drivers/clk/rockchip/rst-rk3588.c | 857 ++++++++++ 5 files changed, 3447 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/rockchip/clk-rk3588.c create mode 100644 drivers/clk/rockchip/rst-rk3588.c diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index 345a5d2a457c..9aad86925cd2 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -99,4 +99,12 @@ config CLK_RK3568 default y help Build the driver for RK3568 Clock Driver. + +config CLK_RK3588 + bool "Rockchip RK3588 clock controller support" + depends on ARM64 || COMPILE_TEST + default y + help + Build the driver for RK3588 Clock Driver. + endif diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index e8543876c056..36894f6a7022 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -28,3 +28,4 @@ obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o +obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c new file mode 100644 index 000000000000..b7ce3fbd6fa6 --- /dev/null +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -0,0 +1,2533 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang + */ + +#include +#include +#include +#include +#include +#include +#include "clk.h" + +/* + * GATE with additional linked clock. Downstream enables the linked clock + * (via runtime PM) whenever the gate is enabled. The downstream implementation + * does this via separate clock nodes for each of the linked gate clocks, + * which leaks parts of the clock tree into DT. It is unclear why this is + * actually needed and things work without it for simple use cases. Thus + * the linked clock is ignored for now. + */ +#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \ + GATE(_id, cname, pname, f, o, b, gf) + + +#define RK3588_GRF_SOC_STATUS0 0x600 +#define RK3588_PHYREF_ALT_GATE 0xc38 + +enum rk3588_plls { + b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll, +}; + +static struct rockchip_pll_rate_table rk3588_pll_rates[] = { + /* _mhz, _p, _m, _s, _k */ + RK3588_PLL_RATE(2520000000, 2, 210, 0, 0), + RK3588_PLL_RATE(2496000000, 2, 208, 0, 0), + RK3588_PLL_RATE(2472000000, 2, 206, 0, 0), + RK3588_PLL_RATE(2448000000, 2, 204, 0, 0), + RK3588_PLL_RATE(2424000000, 2, 202, 0, 0), + RK3588_PLL_RATE(2400000000, 2, 200, 0, 0), + RK3588_PLL_RATE(2376000000, 2, 198, 0, 0), + RK3588_PLL_RATE(2352000000, 2, 196, 0, 0), + RK3588_PLL_RATE(2328000000, 2, 194, 0, 0), + RK3588_PLL_RATE(2304000000, 2, 192, 0, 0), + RK3588_PLL_RATE(2280000000, 2, 190, 0, 0), + RK3588_PLL_RATE(2256000000, 2, 376, 1, 0), + RK3588_PLL_RATE(2232000000, 2, 372, 1, 0), + RK3588_PLL_RATE(2208000000, 2, 368, 1, 0), + RK3588_PLL_RATE(2184000000, 2, 364, 1, 0), + RK3588_PLL_RATE(2160000000, 2, 360, 1, 0), + RK3588_PLL_RATE(2136000000, 2, 356, 1, 0), + RK3588_PLL_RATE(2112000000, 2, 352, 1, 0), + RK3588_PLL_RATE(2088000000, 2, 348, 1, 0), + RK3588_PLL_RATE(2064000000, 2, 344, 1, 0), + RK3588_PLL_RATE(2040000000, 2, 340, 1, 0), + RK3588_PLL_RATE(2016000000, 2, 336, 1, 0), + RK3588_PLL_RATE(1992000000, 2, 332, 1, 0), + RK3588_PLL_RATE(1968000000, 2, 328, 1, 0), + RK3588_PLL_RATE(1944000000, 2, 324, 1, 0), + RK3588_PLL_RATE(1920000000, 2, 320, 1, 0), + RK3588_PLL_RATE(1896000000, 2, 316, 1, 0), + RK3588_PLL_RATE(1872000000, 2, 312, 1, 0), + RK3588_PLL_RATE(1848000000, 2, 308, 1, 0), + RK3588_PLL_RATE(1824000000, 2, 304, 1, 0), + RK3588_PLL_RATE(1800000000, 2, 300, 1, 0), + RK3588_PLL_RATE(1776000000, 2, 296, 1, 0), + RK3588_PLL_RATE(1752000000, 2, 292, 1, 0), + RK3588_PLL_RATE(1728000000, 2, 288, 1, 0), + RK3588_PLL_RATE(1704000000, 2, 284, 1, 0), + RK3588_PLL_RATE(1680000000, 2, 280, 1, 0), + RK3588_PLL_RATE(1656000000, 2, 276, 1, 0), + RK3588_PLL_RATE(1632000000, 2, 272, 1, 0), + RK3588_PLL_RATE(1608000000, 2, 268, 1, 0), + RK3588_PLL_RATE(1584000000, 2, 264, 1, 0), + RK3588_PLL_RATE(1560000000, 2, 260, 1, 0), + RK3588_PLL_RATE(1536000000, 2, 256, 1, 0), + RK3588_PLL_RATE(1512000000, 2, 252, 1, 0), + RK3588_PLL_RATE(1488000000, 2, 248, 1, 0), + RK3588_PLL_RATE(1464000000, 2, 244, 1, 0), + RK3588_PLL_RATE(1440000000, 2, 240, 1, 0), + RK3588_PLL_RATE(1416000000, 2, 236, 1, 0), + RK3588_PLL_RATE(1392000000, 2, 232, 1, 0), + RK3588_PLL_RATE(1320000000, 2, 220, 1, 0), + RK3588_PLL_RATE(1200000000, 2, 200, 1, 0), + RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), + RK3588_PLL_RATE(1100000000, 3, 550, 2, 0), + RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), + RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), + RK3588_PLL_RATE(983040000, 4, 655, 2, 23592), + RK3588_PLL_RATE(955520000, 3, 477, 2, 49806), + RK3588_PLL_RATE(903168000, 6, 903, 2, 11009), + RK3588_PLL_RATE(900000000, 2, 300, 2, 0), + RK3588_PLL_RATE(850000000, 3, 425, 2, 0), + RK3588_PLL_RATE(816000000, 2, 272, 2, 0), + RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), + RK3588_PLL_RATE(786000000, 1, 131, 2, 0), + RK3588_PLL_RATE(785560000, 3, 392, 2, 51117), + RK3588_PLL_RATE(722534400, 8, 963, 2, 24850), + RK3588_PLL_RATE(600000000, 2, 200, 2, 0), + RK3588_PLL_RATE(594000000, 2, 198, 2, 0), + RK3588_PLL_RATE(408000000, 2, 272, 3, 0), + RK3588_PLL_RATE(312000000, 2, 208, 3, 0), + RK3588_PLL_RATE(216000000, 2, 288, 4, 0), + RK3588_PLL_RATE(100000000, 3, 400, 5, 0), + RK3588_PLL_RATE(96000000, 2, 256, 5, 0), + { /* sentinel */ }, +}; + +#define RK3588_CLK_CORE_B0_SEL_CLEAN_MASK 0x3 +#define RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT 13 +#define RK3588_CLK_CORE_B1_SEL_CLEAN_MASK 0x3 +#define RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT 5 +#define RK3588_CLK_CORE_B0_GPLL_DIV_MASK 0x1f +#define RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT 1 +#define RK3588_CLK_CORE_L_SEL_CLEAN_MASK 0x3 +#define RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT 12 +#define RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT 5 +#define RK3588_CLK_DSU_SEL_DF_MASK 0x1 +#define RK3588_CLK_DSU_SEL_DF_SHIFT 15 +#define RK3588_CLK_DSU_DF_SRC_MASK 0x3 +#define RK3588_CLK_DSU_DF_SRC_SHIFT 12 +#define RK3588_CLK_DSU_DF_DIV_MASK 0x1f +#define RK3588_CLK_DSU_DF_DIV_SHIFT 7 +#define RK3588_ACLKM_DSU_DIV_MASK 0x1f +#define RK3588_ACLKM_DSU_DIV_SHIFT 1 +#define RK3588_ACLKS_DSU_DIV_MASK 0x1f +#define RK3588_ACLKS_DSU_DIV_SHIFT 6 +#define RK3588_ACLKMP_DSU_DIV_MASK 0x1f +#define RK3588_ACLKMP_DSU_DIV_SHIFT 11 +#define RK3588_PERIPH_DSU_DIV_MASK 0x1f +#define RK3588_PERIPH_DSU_DIV_SHIFT 0 +#define RK3588_ATCLK_DSU_DIV_MASK 0x1f +#define RK3588_ATCLK_DSU_DIV_SHIFT 0 +#define RK3588_GICCLK_DSU_DIV_MASK 0x1f +#define RK3588_GICCLK_DSU_DIV_SHIFT 5 + +#define RK3588_CORE_B0_SEL(_apllcore) \ +{ \ + .reg = RK3588_BIGCORE0_CLKSEL_CON(0), \ + .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \ + RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \ + HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \ + RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \ +} + +#define RK3588_CORE_B1_SEL(_apllcore) \ +{ \ + .reg = RK3588_BIGCORE0_CLKSEL_CON(1), \ + .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \ + RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \ +} + +#define RK3588_CORE_B2_SEL(_apllcore) \ +{ \ + .reg = RK3588_BIGCORE1_CLKSEL_CON(0), \ + .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \ + RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \ + HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \ + RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \ +} + +#define RK3588_CORE_B3_SEL(_apllcore) \ +{ \ + .reg = RK3588_BIGCORE1_CLKSEL_CON(1), \ + .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \ + RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \ +} + +#define RK3588_CORE_L_SEL0(_offs, _apllcore) \ +{ \ + .reg = RK3588_DSU_CLKSEL_CON(6 + _offs), \ + .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \ + RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT) | \ + HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \ + RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT), \ +} + +#define RK3588_CORE_L_SEL1(_seldsu, _divdsu) \ +{ \ + .reg = RK3588_DSU_CLKSEL_CON(0), \ + .val = HIWORD_UPDATE(_seldsu, RK3588_CLK_DSU_DF_SRC_MASK, \ + RK3588_CLK_DSU_DF_SRC_SHIFT) | \ + HIWORD_UPDATE(_divdsu - 1, RK3588_CLK_DSU_DF_DIV_MASK, \ + RK3588_CLK_DSU_DF_DIV_SHIFT), \ +} + +#define RK3588_CORE_L_SEL2(_aclkm, _aclkmp, _aclks) \ +{ \ + .reg = RK3588_DSU_CLKSEL_CON(1), \ + .val = HIWORD_UPDATE(_aclkm - 1, RK3588_ACLKM_DSU_DIV_MASK, \ + RK3588_ACLKM_DSU_DIV_SHIFT) | \ + HIWORD_UPDATE(_aclkmp - 1, RK3588_ACLKMP_DSU_DIV_MASK, \ + RK3588_ACLKMP_DSU_DIV_SHIFT) | \ + HIWORD_UPDATE(_aclks - 1, RK3588_ACLKS_DSU_DIV_MASK, \ + RK3588_ACLKS_DSU_DIV_SHIFT), \ +} + +#define RK3588_CORE_L_SEL3(_periph) \ +{ \ + .reg = RK3588_DSU_CLKSEL_CON(2), \ + .val = HIWORD_UPDATE(_periph - 1, RK3588_PERIPH_DSU_DIV_MASK, \ + RK3588_PERIPH_DSU_DIV_SHIFT), \ +} + +#define RK3588_CORE_L_SEL4(_gicclk, _atclk) \ +{ \ + .reg = RK3588_DSU_CLKSEL_CON(3), \ + .val = HIWORD_UPDATE(_gicclk - 1, RK3588_GICCLK_DSU_DIV_MASK, \ + RK3588_GICCLK_DSU_DIV_SHIFT) | \ + HIWORD_UPDATE(_atclk - 1, RK3588_ATCLK_DSU_DIV_MASK, \ + RK3588_ATCLK_DSU_DIV_SHIFT), \ +} + +#define RK3588_CPUB01CLK_RATE(_prate, _apllcore) \ +{ \ + .prate = _prate##U, \ + .pre_muxs = { \ + RK3588_CORE_B0_SEL(0), \ + RK3588_CORE_B1_SEL(0), \ + }, \ + .post_muxs = { \ + RK3588_CORE_B0_SEL(_apllcore), \ + RK3588_CORE_B1_SEL(_apllcore), \ + }, \ +} + +#define RK3588_CPUB23CLK_RATE(_prate, _apllcore) \ +{ \ + .prate = _prate##U, \ + .pre_muxs = { \ + RK3588_CORE_B2_SEL(0), \ + RK3588_CORE_B3_SEL(0), \ + }, \ + .post_muxs = { \ + RK3588_CORE_B2_SEL(_apllcore), \ + RK3588_CORE_B3_SEL(_apllcore), \ + }, \ +} + +#define RK3588_CPULCLK_RATE(_prate, _apllcore, _seldsu, _divdsu) \ +{ \ + .prate = _prate##U, \ + .pre_muxs = { \ + RK3588_CORE_L_SEL0(0, 0), \ + RK3588_CORE_L_SEL0(1, 0), \ + RK3588_CORE_L_SEL1(3, 2), \ + RK3588_CORE_L_SEL2(2, 3, 3), \ + RK3588_CORE_L_SEL3(4), \ + RK3588_CORE_L_SEL4(4, 4), \ + }, \ + .post_muxs = { \ + RK3588_CORE_L_SEL0(0, _apllcore), \ + RK3588_CORE_L_SEL0(1, _apllcore), \ + RK3588_CORE_L_SEL1(_seldsu, _divdsu), \ + }, \ +} + +static struct rockchip_cpuclk_rate_table rk3588_cpub0clk_rates[] __initdata = { + RK3588_CPUB01CLK_RATE(2496000000, 1), + RK3588_CPUB01CLK_RATE(2400000000, 1), + RK3588_CPUB01CLK_RATE(2304000000, 1), + RK3588_CPUB01CLK_RATE(2208000000, 1), + RK3588_CPUB01CLK_RATE(2184000000, 1), + RK3588_CPUB01CLK_RATE(2088000000, 1), + RK3588_CPUB01CLK_RATE(2040000000, 1), + RK3588_CPUB01CLK_RATE(2016000000, 1), + RK3588_CPUB01CLK_RATE(1992000000, 1), + RK3588_CPUB01CLK_RATE(1896000000, 1), + RK3588_CPUB01CLK_RATE(1800000000, 1), + RK3588_CPUB01CLK_RATE(1704000000, 0), + RK3588_CPUB01CLK_RATE(1608000000, 0), + RK3588_CPUB01CLK_RATE(1584000000, 0), + RK3588_CPUB01CLK_RATE(1560000000, 0), + RK3588_CPUB01CLK_RATE(1536000000, 0), + RK3588_CPUB01CLK_RATE(1512000000, 0), + RK3588_CPUB01CLK_RATE(1488000000, 0), + RK3588_CPUB01CLK_RATE(1464000000, 0), + RK3588_CPUB01CLK_RATE(1440000000, 0), + RK3588_CPUB01CLK_RATE(1416000000, 0), + RK3588_CPUB01CLK_RATE(1392000000, 0), + RK3588_CPUB01CLK_RATE(1368000000, 0), + RK3588_CPUB01CLK_RATE(1344000000, 0), + RK3588_CPUB01CLK_RATE(1320000000, 0), + RK3588_CPUB01CLK_RATE(1296000000, 0), + RK3588_CPUB01CLK_RATE(1272000000, 0), + RK3588_CPUB01CLK_RATE(1248000000, 0), + RK3588_CPUB01CLK_RATE(1224000000, 0), + RK3588_CPUB01CLK_RATE(1200000000, 0), + RK3588_CPUB01CLK_RATE(1104000000, 0), + RK3588_CPUB01CLK_RATE(1008000000, 0), + RK3588_CPUB01CLK_RATE(912000000, 0), + RK3588_CPUB01CLK_RATE(816000000, 0), + RK3588_CPUB01CLK_RATE(696000000, 0), + RK3588_CPUB01CLK_RATE(600000000, 0), + RK3588_CPUB01CLK_RATE(408000000, 0), + RK3588_CPUB01CLK_RATE(312000000, 0), + RK3588_CPUB01CLK_RATE(216000000, 0), + RK3588_CPUB01CLK_RATE(96000000, 0), +}; + +static const struct rockchip_cpuclk_reg_data rk3588_cpub0clk_data = { + .core_reg[0] = RK3588_BIGCORE0_CLKSEL_CON(0), + .div_core_shift[0] = 8, + .div_core_mask[0] = 0x1f, + .core_reg[1] = RK3588_BIGCORE0_CLKSEL_CON(1), + .div_core_shift[1] = 0, + .div_core_mask[1] = 0x1f, + .num_cores = 2, + .mux_core_alt = 1, + .mux_core_main = 2, + .mux_core_shift = 6, + .mux_core_mask = 0x3, +}; + +static struct rockchip_cpuclk_rate_table rk3588_cpub1clk_rates[] __initdata = { + RK3588_CPUB23CLK_RATE(2496000000, 1), + RK3588_CPUB23CLK_RATE(2400000000, 1), + RK3588_CPUB23CLK_RATE(2304000000, 1), + RK3588_CPUB23CLK_RATE(2208000000, 1), + RK3588_CPUB23CLK_RATE(2184000000, 1), + RK3588_CPUB23CLK_RATE(2088000000, 1), + RK3588_CPUB23CLK_RATE(2040000000, 1), + RK3588_CPUB23CLK_RATE(2016000000, 1), + RK3588_CPUB23CLK_RATE(1992000000, 1), + RK3588_CPUB23CLK_RATE(1896000000, 1), + RK3588_CPUB23CLK_RATE(1800000000, 1), + RK3588_CPUB23CLK_RATE(1704000000, 0), + RK3588_CPUB23CLK_RATE(1608000000, 0), + RK3588_CPUB23CLK_RATE(1584000000, 0), + RK3588_CPUB23CLK_RATE(1560000000, 0), + RK3588_CPUB23CLK_RATE(1536000000, 0), + RK3588_CPUB23CLK_RATE(1512000000, 0), + RK3588_CPUB23CLK_RATE(1488000000, 0), + RK3588_CPUB23CLK_RATE(1464000000, 0), + RK3588_CPUB23CLK_RATE(1440000000, 0), + RK3588_CPUB23CLK_RATE(1416000000, 0), + RK3588_CPUB23CLK_RATE(1392000000, 0), + RK3588_CPUB23CLK_RATE(1368000000, 0), + RK3588_CPUB23CLK_RATE(1344000000, 0), + RK3588_CPUB23CLK_RATE(1320000000, 0), + RK3588_CPUB23CLK_RATE(1296000000, 0), + RK3588_CPUB23CLK_RATE(1272000000, 0), + RK3588_CPUB23CLK_RATE(1248000000, 0), + RK3588_CPUB23CLK_RATE(1224000000, 0), + RK3588_CPUB23CLK_RATE(1200000000, 0), + RK3588_CPUB23CLK_RATE(1104000000, 0), + RK3588_CPUB23CLK_RATE(1008000000, 0), + RK3588_CPUB23CLK_RATE(912000000, 0), + RK3588_CPUB23CLK_RATE(816000000, 0), + RK3588_CPUB23CLK_RATE(696000000, 0), + RK3588_CPUB23CLK_RATE(600000000, 0), + RK3588_CPUB23CLK_RATE(408000000, 0), + RK3588_CPUB23CLK_RATE(312000000, 0), + RK3588_CPUB23CLK_RATE(216000000, 0), + RK3588_CPUB23CLK_RATE(96000000, 0), +}; + +static const struct rockchip_cpuclk_reg_data rk3588_cpub1clk_data = { + .core_reg[0] = RK3588_BIGCORE1_CLKSEL_CON(0), + .div_core_shift[0] = 8, + .div_core_mask[0] = 0x1f, + .core_reg[1] = RK3588_BIGCORE1_CLKSEL_CON(1), + .div_core_shift[1] = 0, + .div_core_mask[1] = 0x1f, + .num_cores = 2, + .mux_core_alt = 1, + .mux_core_main = 2, + .mux_core_shift = 6, + .mux_core_mask = 0x3, +}; + +static struct rockchip_cpuclk_rate_table rk3588_cpulclk_rates[] __initdata = { + RK3588_CPULCLK_RATE(2208000000, 1, 3, 1), + RK3588_CPULCLK_RATE(2184000000, 1, 3, 1), + RK3588_CPULCLK_RATE(2088000000, 1, 3, 1), + RK3588_CPULCLK_RATE(2040000000, 1, 3, 1), + RK3588_CPULCLK_RATE(2016000000, 1, 3, 1), + RK3588_CPULCLK_RATE(1992000000, 1, 3, 1), + RK3588_CPULCLK_RATE(1896000000, 1, 3, 1), + RK3588_CPULCLK_RATE(1800000000, 1, 3, 1), + RK3588_CPULCLK_RATE(1704000000, 0, 3, 1), + RK3588_CPULCLK_RATE(1608000000, 0, 3, 1), + RK3588_CPULCLK_RATE(1584000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1560000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1536000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1512000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1488000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1464000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1440000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1416000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1392000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1368000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1344000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1320000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1296000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1272000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1248000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1224000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1200000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1104000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1008000000, 0, 2, 1), + RK3588_CPULCLK_RATE(912000000, 0, 2, 1), + RK3588_CPULCLK_RATE(816000000, 0, 2, 1), + RK3588_CPULCLK_RATE(696000000, 0, 2, 1), + RK3588_CPULCLK_RATE(600000000, 0, 2, 1), + RK3588_CPULCLK_RATE(408000000, 0, 2, 1), + RK3588_CPULCLK_RATE(312000000, 0, 2, 1), + RK3588_CPULCLK_RATE(216000000, 0, 2, 1), + RK3588_CPULCLK_RATE(96000000, 0, 2, 1), +}; + +static const struct rockchip_cpuclk_reg_data rk3588_cpulclk_data = { + .core_reg[0] = RK3588_DSU_CLKSEL_CON(6), + .div_core_shift[0] = 0, + .div_core_mask[0] = 0x1f, + .core_reg[1] = RK3588_DSU_CLKSEL_CON(6), + .div_core_shift[1] = 7, + .div_core_mask[1] = 0x1f, + .core_reg[2] = RK3588_DSU_CLKSEL_CON(7), + .div_core_shift[2] = 0, + .div_core_mask[2] = 0x1f, + .core_reg[3] = RK3588_DSU_CLKSEL_CON(7), + .div_core_shift[3] = 7, + .div_core_mask[3] = 0x1f, + .num_cores = 4, + .mux_core_reg = RK3588_DSU_CLKSEL_CON(5), + .mux_core_alt = 1, + .mux_core_main = 2, + .mux_core_shift = 14, + .mux_core_mask = 0x3, +}; + +PNAME(mux_pll_p) = { "xin24m", "xin32k" }; +PNAME(mux_armclkl_p) = { "xin24m", "gpll", "lpll" }; +PNAME(mux_armclkb01_p) = { "xin24m", "gpll", "b0pll",}; +PNAME(mux_armclkb23_p) = { "xin24m", "gpll", "b1pll",}; +PNAME(b0pll_b1pll_lpll_gpll_p) = { "b0pll", "b1pll", "lpll", "gpll" }; +PNAME(gpll_24m_p) = { "gpll", "xin24m" }; +PNAME(gpll_aupll_p) = { "gpll", "aupll" }; +PNAME(gpll_lpll_p) = { "gpll", "lpll" }; +PNAME(gpll_cpll_p) = { "gpll", "cpll" }; +PNAME(gpll_spll_p) = { "gpll", "spll" }; +PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m"}; +PNAME(gpll_cpll_aupll_p) = { "gpll", "cpll", "aupll"}; +PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll"}; +PNAME(gpll_cpll_npll_v0pll_p) = { "gpll", "cpll", "npll", "v0pll"}; +PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" }; +PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" }; +PNAME(gpll_cpll_aupll_npll_p) = { "gpll", "cpll", "aupll", "npll" }; +PNAME(gpll_cpll_v0pll_aupll_p) = { "gpll", "cpll", "v0pll", "aupll" }; +PNAME(gpll_cpll_v0pll_spll_p) = { "gpll", "cpll", "v0pll", "spll" }; +PNAME(gpll_cpll_aupll_npll_spll_p) = { "gpll", "cpll", "aupll", "npll", "spll" }; +PNAME(gpll_cpll_dmyaupll_npll_spll_p) = { "gpll", "cpll", "dummy_aupll", "npll", "spll" }; +PNAME(gpll_cpll_npll_aupll_spll_p) = { "gpll", "cpll", "npll", "aupll", "spll" }; +PNAME(gpll_cpll_npll_1000m_p) = { "gpll", "cpll", "npll", "clk_1000m_src" }; +PNAME(mux_24m_spll_gpll_cpll_p) = { "xin24m", "spll", "gpll", "cpll" }; +PNAME(mux_24m_32k_p) = { "xin24m", "xin32k" }; +PNAME(mux_24m_100m_p) = { "xin24m", "clk_100m_src" }; +PNAME(mux_200m_100m_p) = { "clk_200m_src", "clk_100m_src" }; +PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" }; +PNAME(mux_150m_50m_24m_p) = { "clk_150m_src", "clk_50m_src", "xin24m" }; +PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", "xin24m" }; +PNAME(mux_200m_150m_24m_p) = { "clk_200m_src", "clk_150m_src", "xin24m" }; +PNAME(mux_150m_100m_50m_24m_p) = { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" }; +PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" }; +PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" }; +PNAME(mux_700m_400m_200m_24m_p) = { "clk_700m_src", "clk_400m_src", "clk_200m_src", "xin24m" }; +PNAME(mux_500m_250m_100m_24m_p) = { "clk_500m_src", "clk_250m_src", "clk_100m_src", "xin24m" }; +PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" }; +PNAME(mux_400m_200m_100m_24m_p) = { "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" }; +PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin12m" }; +PNAME(i2s2_2ch_mclkout_p) = { "mclk_i2s2_2ch", "xin12m" }; +PNAME(clk_i2s3_2ch_p) = { "clk_i2s3_2ch_src", "clk_i2s3_2ch_frac", "i2s3_mclkin", "xin12m" }; +PNAME(i2s3_2ch_mclkout_p) = { "mclk_i2s3_2ch", "xin12m" }; +PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin12m" }; +PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin12m" }; +PNAME(i2s0_8ch_mclkout_p) = { "mclk_i2s0_8ch_tx", "mclk_i2s0_8ch_rx", "xin12m" }; +PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin12m" }; +PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin12m" }; +PNAME(i2s1_8ch_mclkout_p) = { "mclk_i2s1_8ch_tx", "mclk_i2s1_8ch_rx", "xin12m" }; +PNAME(clk_i2s4_8ch_tx_p) = { "clk_i2s4_8ch_tx_src", "clk_i2s4_8ch_tx_frac", "i2s4_mclkin", "xin12m" }; +PNAME(clk_i2s5_8ch_tx_p) = { "clk_i2s5_8ch_tx_src", "clk_i2s5_8ch_tx_frac", "i2s5_mclkin", "xin12m" }; +PNAME(clk_i2s6_8ch_tx_p) = { "clk_i2s6_8ch_tx_src", "clk_i2s6_8ch_tx_frac", "i2s6_mclkin", "xin12m" }; +PNAME(clk_i2s6_8ch_rx_p) = { "clk_i2s6_8ch_rx_src", "clk_i2s6_8ch_rx_frac", "i2s6_mclkin", "xin12m" }; +PNAME(i2s6_8ch_mclkout_p) = { "mclk_i2s6_8ch_tx", "mclk_i2s6_8ch_rx", "xin12m" }; +PNAME(clk_i2s7_8ch_rx_p) = { "clk_i2s7_8ch_rx_src", "clk_i2s7_8ch_rx_frac", "i2s7_mclkin", "xin12m" }; +PNAME(clk_i2s8_8ch_tx_p) = { "clk_i2s8_8ch_tx_src", "clk_i2s8_8ch_tx_frac", "i2s8_mclkin", "xin12m" }; +PNAME(clk_i2s9_8ch_rx_p) = { "clk_i2s9_8ch_rx_src", "clk_i2s9_8ch_rx_frac", "i2s9_mclkin", "xin12m" }; +PNAME(clk_i2s10_8ch_rx_p) = { "clk_i2s10_8ch_rx_src", "clk_i2s10_8ch_rx_frac", "i2s10_mclkin", "xin12m" }; +PNAME(clk_spdif0_p) = { "clk_spdif0_src", "clk_spdif0_frac", "xin12m" }; +PNAME(clk_spdif1_p) = { "clk_spdif1_src", "clk_spdif1_frac", "xin12m" }; +PNAME(clk_spdif2_dp0_p) = { "clk_spdif2_dp0_src", "clk_spdif2_dp0_frac", "xin12m" }; +PNAME(clk_spdif3_p) = { "clk_spdif3_src", "clk_spdif3_frac", "xin12m" }; +PNAME(clk_spdif4_p) = { "clk_spdif4_src", "clk_spdif4_frac", "xin12m" }; +PNAME(clk_spdif5_dp1_p) = { "clk_spdif5_dp1_src", "clk_spdif5_dp1_frac", "xin12m" }; +PNAME(clk_uart0_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" }; +PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; +PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; +PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; +PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; +PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; +PNAME(clk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; +PNAME(clk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; +PNAME(clk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; +PNAME(clk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; +PNAME(clk_gmac0_ptp_ref_p) = { "cpll", "clk_gmac0_ptpref_io" }; +PNAME(clk_gmac1_ptp_ref_p) = { "cpll", "clk_gmac1_ptpref_io" }; +PNAME(clk_hdmirx_aud_p) = { "clk_hdmirx_aud_src", "clk_hdmirx_aud_frac" }; +PNAME(aclk_hdcp1_root_p) = { "gpll", "cpll", "clk_hdmitrx_refsrc" }; +PNAME(aclk_vop_sub_src_p) = { "aclk_vop_root", "aclk_vop_div2_src" }; +PNAME(dclk_vop0_p) = { "dclk_vop0_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; +PNAME(dclk_vop1_p) = { "dclk_vop1_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; +PNAME(dclk_vop2_p) = { "dclk_vop2_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; +PNAME(pmu_200m_100m_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src" }; +PNAME(pmu_300m_24m_p) = { "clk_300m_src", "xin24m" }; +PNAME(pmu_400m_24m_p) = { "clk_400m_src", "xin24m" }; +PNAME(pmu_100m_50m_24m_src_p) = { "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" }; +PNAME(pmu_24m_32k_100m_src_p) = { "xin24m", "32k", "clk_pmu1_100m_src" }; +PNAME(hclk_pmu1_root_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" }; +PNAME(hclk_pmu_cm0_root_p) = { "clk_pmu1_400m_src", "clk_pmu1_200m_src", "clk_pmu1_100m_src", "xin24m" }; +PNAME(mclk_pdm0_p) = { "clk_pmu1_300m_src", "clk_pmu1_200m_src" }; +PNAME(mux_24m_ppll_spll_p) = { "xin24m", "ppll", "spll" }; +PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" }; +PNAME(clk_ref_pipe_phy0_p) = { "clk_ref_pipe_phy0_osc_src", "clk_ref_pipe_phy0_pll_src" }; +PNAME(clk_ref_pipe_phy1_p) = { "clk_ref_pipe_phy1_osc_src", "clk_ref_pipe_phy1_pll_src" }; +PNAME(clk_ref_pipe_phy2_p) = { "clk_ref_pipe_phy2_osc_src", "clk_ref_pipe_phy2_pll_src" }; + +#define MFLAGS CLK_MUX_HIWORD_MASK +#define DFLAGS CLK_DIVIDER_HIWORD_MASK +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) + +static struct rockchip_clk_branch rk3588_i2s0_8ch_tx_fracmux __initdata = + MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(26), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s0_8ch_rx_fracmux __initdata = + MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(28), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s1_8ch_tx_fracmux __initdata = + MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(7), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s1_8ch_rx_fracmux __initdata = + MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(9), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s2_2ch_fracmux __initdata = + MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(30), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s3_2ch_fracmux __initdata = + MUX(CLK_I2S3_2CH, "clk_i2s3_2ch", clk_i2s3_2ch_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(32), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s4_8ch_tx_fracmux __initdata = + MUX(CLK_I2S4_8CH_TX, "clk_i2s4_8ch_tx", clk_i2s4_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(120), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s5_8ch_tx_fracmux __initdata = + MUX(CLK_I2S5_8CH_TX, "clk_i2s5_8ch_tx", clk_i2s5_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(142), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s6_8ch_tx_fracmux __initdata = + MUX(CLK_I2S6_8CH_TX, "clk_i2s6_8ch_tx", clk_i2s6_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(146), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s6_8ch_rx_fracmux __initdata = + MUX(CLK_I2S6_8CH_RX, "clk_i2s6_8ch_rx", clk_i2s6_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(148), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s7_8ch_rx_fracmux __initdata = + MUX(CLK_I2S7_8CH_RX, "clk_i2s7_8ch_rx", clk_i2s7_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(131), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s8_8ch_tx_fracmux __initdata = + MUX(CLK_I2S8_8CH_TX, "clk_i2s8_8ch_tx", clk_i2s8_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(122), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s9_8ch_rx_fracmux __initdata = + MUX(CLK_I2S9_8CH_RX, "clk_i2s9_8ch_rx", clk_i2s9_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(155), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s10_8ch_rx_fracmux __initdata = + MUX(CLK_I2S10_8CH_RX, "clk_i2s10_8ch_rx", clk_i2s10_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(157), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_spdif0_fracmux __initdata = + MUX(CLK_SPDIF0, "clk_spdif0", clk_spdif0_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(34), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_spdif1_fracmux __initdata = + MUX(CLK_SPDIF1, "clk_spdif1", clk_spdif1_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(36), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_spdif2_dp0_fracmux __initdata = + MUX(CLK_SPDIF2_DP0, "clk_spdif2_dp0", clk_spdif2_dp0_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(124), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_spdif3_fracmux __initdata = + MUX(CLK_SPDIF3, "clk_spdif3", clk_spdif3_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(150), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_spdif4_fracmux __initdata = + MUX(CLK_SPDIF4, "clk_spdif4", clk_spdif4_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(152), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_spdif5_dp1_fracmux __initdata = + MUX(CLK_SPDIF5_DP1, "clk_spdif5_dp1", clk_spdif5_dp1_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(126), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart0_fracmux __initdata = + MUX(CLK_UART0, "clk_uart0", clk_uart0_p, CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(5), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart1_fracmux __initdata = + MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(43), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart2_fracmux __initdata = + MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(45), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart3_fracmux __initdata = + MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(47), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart4_fracmux __initdata = + MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(49), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart5_fracmux __initdata = + MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(51), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart6_fracmux __initdata = + MUX(CLK_UART6, "clk_uart6", clk_uart6_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(53), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart7_fracmux __initdata = + MUX(CLK_UART7, "clk_uart7", clk_uart7_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(55), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart8_fracmux __initdata = + MUX(CLK_UART8, "clk_uart8", clk_uart8_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(57), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart9_fracmux __initdata = + MUX(CLK_UART9, "clk_uart9", clk_uart9_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(59), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_hdmirx_aud_fracmux __initdata = + MUX(CLK_HDMIRX_AUD_P_MUX, "clk_hdmirx_aud_mux", clk_hdmirx_aud_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(140), 0, 1, MFLAGS); + +static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = { + [b0pll] = PLL(pll_rk3588_core, PLL_B0PLL, "b0pll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3588_B0_PLL_CON(0), + RK3588_B0_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), + [b1pll] = PLL(pll_rk3588_core, PLL_B1PLL, "b1pll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3588_B1_PLL_CON(8), + RK3588_B1_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), + [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3588_LPLL_CON(16), + RK3588_LPLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), + [v0pll] = PLL(pll_rk3588, PLL_V0PLL, "v0pll", mux_pll_p, + 0, RK3588_PLL_CON(88), + RK3588_MODE_CON0, 4, 15, 0, rk3588_pll_rates), + [aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_pll_p, + 0, RK3588_PLL_CON(96), + RK3588_MODE_CON0, 6, 15, 0, rk3588_pll_rates), + [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3588_PLL_CON(104), + RK3588_MODE_CON0, 8, 15, 0, rk3588_pll_rates), + [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3588_PLL_CON(112), + RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates), + [npll] = PLL(pll_rk3588, PLL_NPLL, "npll", mux_pll_p, + 0, RK3588_PLL_CON(120), + RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates), + [ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3588_PMU_PLL_CON(128), + RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates), +}; + +static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { + /* + * CRU Clock-Architecture + */ + /* fixed */ + FACTOR(0, "xin12m", "xin24m", 0, 1, 2), + + /* top */ + COMPOSITE(CLK_50M_SRC, "clk_50m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 0, GFLAGS), + COMPOSITE(CLK_100M_SRC, "clk_100m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE(CLK_150M_SRC, "clk_150m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 2, GFLAGS), + COMPOSITE(CLK_200M_SRC, "clk_200m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE(CLK_250M_SRC, "clk_250m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE(CLK_300M_SRC, "clk_300m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 5, GFLAGS), + COMPOSITE(CLK_350M_SRC, "clk_350m_src", gpll_spll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 6, GFLAGS), + COMPOSITE(CLK_400M_SRC, "clk_400m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 7, GFLAGS), + COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE(CLK_500M_SRC, "clk_500m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 9, GFLAGS), + COMPOSITE(CLK_600M_SRC, "clk_600m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 10, GFLAGS), + COMPOSITE(CLK_650M_SRC, "clk_650m_src", gpll_lpll_p, 0, + RK3588_CLKSEL_CON(5), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 11, GFLAGS), + COMPOSITE(CLK_700M_SRC, "clk_700m_src", gpll_spll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(6), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 12, GFLAGS), + COMPOSITE(CLK_800M_SRC, "clk_800m_src", gpll_aupll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(6), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 13, GFLAGS), + COMPOSITE_HALFDIV(CLK_1000M_SRC, "clk_1000m_src", gpll_cpll_npll_v0pll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(7), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 14, GFLAGS), + COMPOSITE(CLK_1200M_SRC, "clk_1200m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(7), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 15, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_M300_ROOT, "aclk_top_m300_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 10, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_M500_ROOT, "aclk_top_m500_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 2, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 11, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_M400_ROOT, "aclk_top_m400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 4, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 12, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_S200_ROOT, "aclk_top_s200_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 6, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 13, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_S400_ROOT, "aclk_top_s400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 14, GFLAGS), + COMPOSITE(ACLK_TOP_ROOT, "aclk_top_root", gpll_cpll_aupll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(8), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(8), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE(ACLK_LOW_TOP_ROOT, "aclk_low_top_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(8), 14, 1, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(1), 2, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M0, "clk_mipi_camaraout_m0", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 9, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M1, "clk_mipi_camaraout_m1", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 10, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M2, "clk_mipi_camaraout_m2", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 11, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M3, "clk_mipi_camaraout_m3", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 12, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M4, "clk_mipi_camaraout_m4", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(22), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 13, GFLAGS), + COMPOSITE(MCLK_GMAC0_OUT, "mclk_gmac0_out", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(5), 3, GFLAGS), + COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(15), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3588_CLKGATE_CON(5), 4, GFLAGS), + COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(5), 5, GFLAGS), + COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0, + RK3588_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 6, GFLAGS), + GATE(PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(3), 14, GFLAGS), + GATE(PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(4), 3, GFLAGS), + GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(1), 6, GFLAGS), + GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(1), 8, GFLAGS), + GATE(PCLK_CRU, "pclk_cru", "pclk_top_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(5), 0, GFLAGS), + + /* bigcore0 */ + COMPOSITE_NODIV(PCLK_BIGCORE0_ROOT, "pclk_bigcore0_root", mux_100m_50m_24m_p, + CLK_IS_CRITICAL, + RK3588_BIGCORE0_CLKSEL_CON(2), 0, 2, MFLAGS, + RK3588_BIGCORE0_CLKGATE_CON(0), 14, GFLAGS), + GATE(PCLK_BIGCORE0_PVTM, "pclk_bigcore0_pvtm", "pclk_bigcore0_root", 0, + RK3588_BIGCORE0_CLKGATE_CON(1), 0, GFLAGS), + GATE(CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m", 0, + RK3588_BIGCORE0_CLKGATE_CON(0), 12, GFLAGS), + GATE(CLK_CORE_BIGCORE0_PVTM, "clk_core_bigcore0_pvtm", "armclk_b01", 0, + RK3588_BIGCORE0_CLKGATE_CON(0), 13, GFLAGS), + + /* bigcore1 */ + COMPOSITE_NODIV(PCLK_BIGCORE1_ROOT, "pclk_bigcore1_root", mux_100m_50m_24m_p, + CLK_IS_CRITICAL, + RK3588_BIGCORE1_CLKSEL_CON(2), 0, 2, MFLAGS, + RK3588_BIGCORE1_CLKGATE_CON(0), 14, GFLAGS), + GATE(PCLK_BIGCORE1_PVTM, "pclk_bigcore1_pvtm", "pclk_bigcore1_root", 0, + RK3588_BIGCORE1_CLKGATE_CON(1), 0, GFLAGS), + GATE(CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m", 0, + RK3588_BIGCORE1_CLKGATE_CON(0), 12, GFLAGS), + GATE(CLK_CORE_BIGCORE1_PVTM, "clk_core_bigcore1_pvtm", "armclk_b23", 0, + RK3588_BIGCORE1_CLKGATE_CON(0), 13, GFLAGS), + + /* dsu */ + COMPOSITE(0, "sclk_dsu", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(0), 12, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_DSU_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE_NOMUX(0, "atclk_dsu", "sclk_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE_NOMUX(0, "gicclk_dsu", "sclk_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(3), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE_NOMUX(0, "aclkmp_dsu", "sclk_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(1), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(0), 12, GFLAGS), + COMPOSITE_NOMUX(0, "aclkm_dsu", "sclk_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(1), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE_NOMUX(0, "aclks_dsu", "sclk_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(1), 6, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(0), 9, GFLAGS), + COMPOSITE_NOMUX(0, "periph_dsu", "sclk_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(2), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(0), 13, GFLAGS), + COMPOSITE_NOMUX(0, "cntclk_dsu", "periph_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(2), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(0), 14, GFLAGS), + COMPOSITE_NOMUX(0, "tsclk_dsu", "periph_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(2), 10, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(0), 15, GFLAGS), + COMPOSITE_NODIV(PCLK_DSU_S_ROOT, "pclk_dsu_s_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(4), 11, 2, MFLAGS, + RK3588_DSU_CLKGATE_CON(2), 2, GFLAGS), + COMPOSITE(PCLK_DSU_ROOT, "pclk_dsu_root", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(4), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_DSU_CLKGATE_CON(1), 3, GFLAGS), + COMPOSITE_NODIV(PCLK_DSU_NS_ROOT, "pclk_dsu_ns_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(4), 7, 2, MFLAGS, + RK3588_DSU_CLKGATE_CON(1), 4, GFLAGS), + GATE(PCLK_LITCORE_PVTM, "pclk_litcore_pvtm", "pclk_dsu_ns_root", 0, + RK3588_DSU_CLKGATE_CON(2), 6, GFLAGS), + GATE(PCLK_DBG, "pclk_dbg", "pclk_dsu_root", CLK_IS_CRITICAL, + RK3588_DSU_CLKGATE_CON(1), 7, GFLAGS), + GATE(PCLK_DSU, "pclk_dsu", "pclk_dsu_root", CLK_IS_CRITICAL, + RK3588_DSU_CLKGATE_CON(1), 6, GFLAGS), + GATE(PCLK_S_DAPLITE, "pclk_s_daplite", "pclk_dsu_ns_root", CLK_IGNORE_UNUSED, + RK3588_DSU_CLKGATE_CON(1), 8, GFLAGS), + GATE(PCLK_M_DAPLITE, "pclk_m_daplite", "pclk_dsu_root", CLK_IGNORE_UNUSED, + RK3588_DSU_CLKGATE_CON(1), 9, GFLAGS), + GATE(CLK_LITCORE_PVTM, "clk_litcore_pvtm", "xin24m", 0, + RK3588_DSU_CLKGATE_CON(2), 0, GFLAGS), + GATE(CLK_CORE_LITCORE_PVTM, "clk_core_litcore_pvtm", "armclk_l", 0, + RK3588_DSU_CLKGATE_CON(2), 1, GFLAGS), + + /* audio */ + COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(24), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(7), 0, GFLAGS), + COMPOSITE_NODIV(PCLK_AUDIO_ROOT, "pclk_audio_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(24), 2, 2, MFLAGS, + RK3588_CLKGATE_CON(7), 1, GFLAGS), + GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_audio_root", 0, + RK3588_CLKGATE_CON(7), 12, GFLAGS), + GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_audio_root", 0, + RK3588_CLKGATE_CON(7), 13, GFLAGS), + COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(28), 9, 1, MFLAGS, 4, 5, DFLAGS, + RK3588_CLKGATE_CON(7), 14, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(29), 0, + RK3588_CLKGATE_CON(7), 15, GFLAGS, + &rk3588_i2s2_2ch_fracmux), + GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0, + RK3588_CLKGATE_CON(8), 0, GFLAGS), + MUX(I2S2_2CH_MCLKOUT, "i2s2_2ch_mclkout", i2s2_2ch_mclkout_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(30), 2, 1, MFLAGS), + + COMPOSITE(CLK_I2S3_2CH_SRC, "clk_i2s3_2ch_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(30), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(8), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S3_2CH_FRAC, "clk_i2s3_2ch_frac", "clk_i2s3_2ch_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(31), 0, + RK3588_CLKGATE_CON(8), 2, GFLAGS, + &rk3588_i2s3_2ch_fracmux), + GATE(MCLK_I2S3_2CH, "mclk_i2s3_2ch", "clk_i2s3_2ch", 0, + RK3588_CLKGATE_CON(8), 3, GFLAGS), + GATE(CLK_DAC_ACDCDIG, "clk_dac_acdcdig", "mclk_i2s3_2ch", 0, + RK3588_CLKGATE_CON(8), 4, GFLAGS), + MUX(I2S3_2CH_MCLKOUT, "i2s3_2ch_mclkout", i2s3_2ch_mclkout_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(32), 2, 1, MFLAGS), + GATE(PCLK_ACDCDIG, "pclk_acdcdig", "pclk_audio_root", 0, + RK3588_CLKGATE_CON(7), 11, GFLAGS), + GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_root", 0, + RK3588_CLKGATE_CON(7), 4, GFLAGS), + + COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(24), 9, 1, MFLAGS, 4, 5, DFLAGS, + RK3588_CLKGATE_CON(7), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(25), 0, + RK3588_CLKGATE_CON(7), 6, GFLAGS, + &rk3588_i2s0_8ch_tx_fracmux), + GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0, + RK3588_CLKGATE_CON(7), 7, GFLAGS), + + COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(26), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(7), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(27), 0, + RK3588_CLKGATE_CON(7), 9, GFLAGS, + &rk3588_i2s0_8ch_rx_fracmux), + GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0, + RK3588_CLKGATE_CON(7), 10, GFLAGS), + MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(28), 2, 2, MFLAGS), + + GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0, + RK3588_CLKGATE_CON(9), 6, GFLAGS), + COMPOSITE(MCLK_PDM1, "mclk_pdm1", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(36), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(9), 7, GFLAGS), + + GATE(HCLK_SPDIF0, "hclk_spdif0", "hclk_audio_root", 0, + RK3588_CLKGATE_CON(8), 14, GFLAGS), + COMPOSITE(CLK_SPDIF0_SRC, "clk_spdif0_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(32), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(8), 15, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF0_FRAC, "clk_spdif0_frac", "clk_spdif0_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(33), 0, + RK3588_CLKGATE_CON(9), 0, GFLAGS, + &rk3588_spdif0_fracmux), + GATE(MCLK_SPDIF0, "mclk_spdif0", "clk_spdif0", 0, + RK3588_CLKGATE_CON(9), 1, GFLAGS), + + GATE(HCLK_SPDIF1, "hclk_spdif1", "hclk_audio_root", 0, + RK3588_CLKGATE_CON(9), 2, GFLAGS), + COMPOSITE(CLK_SPDIF1_SRC, "clk_spdif1_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(34), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(9), 3, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF1_FRAC, "clk_spdif1_frac", "clk_spdif1_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(35), 0, + RK3588_CLKGATE_CON(9), 4, GFLAGS, + &rk3588_spdif1_fracmux), + GATE(MCLK_SPDIF1, "mclk_spdif1", "clk_spdif1", 0, + RK3588_CLKGATE_CON(9), 5, GFLAGS), + + COMPOSITE(ACLK_AV1_ROOT, "aclk_av1_root", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(163), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(68), 0, GFLAGS), + COMPOSITE_NODIV(PCLK_AV1_ROOT, "pclk_av1_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(163), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(68), 3, GFLAGS), + + /* bus */ + COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(10), 0, GFLAGS), + + GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(16), 11, GFLAGS), + GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(16), 12, GFLAGS), + GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(16), 13, GFLAGS), + GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(19), 3, GFLAGS), + GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(19), 4, GFLAGS), + GATE(PCLK_DDRCM0_INTMUX, "pclk_ddrcm0_intmux", "pclk_top_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(19), 5, GFLAGS), + + GATE(PCLK_PWM1, "pclk_pwm1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(15), 3, GFLAGS), + COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(59), 12, 2, MFLAGS, + RK3588_CLKGATE_CON(15), 4, GFLAGS), + GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0, + RK3588_CLKGATE_CON(15), 5, GFLAGS), + GATE(PCLK_PWM2, "pclk_pwm2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(15), 6, GFLAGS), + COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(59), 14, 2, MFLAGS, + RK3588_CLKGATE_CON(15), 7, GFLAGS), + GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0, + RK3588_CLKGATE_CON(15), 8, GFLAGS), + GATE(PCLK_PWM3, "pclk_pwm3", "pclk_top_root", 0, + RK3588_CLKGATE_CON(15), 9, GFLAGS), + COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(60), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(15), 10, GFLAGS), + GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0, + RK3588_CLKGATE_CON(15), 11, GFLAGS), + + GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(15), 12, GFLAGS), + GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(15), 13, GFLAGS), + COMPOSITE_NODIV(CLK_BUS_TIMER_ROOT, "clk_bus_timer_root", mux_24m_100m_p, 0, + RK3588_CLKSEL_CON(60), 2, 1, MFLAGS, + RK3588_CLKGATE_CON(15), 14, GFLAGS), + GATE(CLK_BUSTIMER0, "clk_bustimer0", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(15), 15, GFLAGS), + GATE(CLK_BUSTIMER1, "clk_bustimer1", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 0, GFLAGS), + GATE(CLK_BUSTIMER2, "clk_bustimer2", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 1, GFLAGS), + GATE(CLK_BUSTIMER3, "clk_bustimer3", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 2, GFLAGS), + GATE(CLK_BUSTIMER4, "clk_bustimer4", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 3, GFLAGS), + GATE(CLK_BUSTIMER5, "clk_bustimer5", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 4, GFLAGS), + GATE(CLK_BUSTIMER6, "clk_bustimer6", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 5, GFLAGS), + GATE(CLK_BUSTIMER7, "clk_bustimer7", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 6, GFLAGS), + GATE(CLK_BUSTIMER8, "clk_bustimer8", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 7, GFLAGS), + GATE(CLK_BUSTIMER9, "clk_bustimer9", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 8, GFLAGS), + GATE(CLK_BUSTIMER10, "clk_bustimer10", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 9, GFLAGS), + GATE(CLK_BUSTIMER11, "clk_bustimer11", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 10, GFLAGS), + + GATE(PCLK_WDT0, "pclk_wdt0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(15), 0, GFLAGS), + GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0, + RK3588_CLKGATE_CON(15), 1, GFLAGS), + + GATE(PCLK_CAN0, "pclk_can0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(11), 8, GFLAGS), + COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(39), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(11), 9, GFLAGS), + GATE(PCLK_CAN1, "pclk_can1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(11), 10, GFLAGS), + COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(39), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(11), 11, GFLAGS), + GATE(PCLK_CAN2, "pclk_can2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(11), 12, GFLAGS), + COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(40), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(11), 13, GFLAGS), + + GATE(ACLK_DECOM, "aclk_decom", "aclk_bus_root", 0, + RK3588_CLKGATE_CON(17), 6, GFLAGS), + GATE(PCLK_DECOM, "pclk_decom", "pclk_top_root", 0, + RK3588_CLKGATE_CON(17), 7, GFLAGS), + COMPOSITE(DCLK_DECOM, "dclk_decom", gpll_spll_p, 0, + RK3588_CLKSEL_CON(62), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(17), 8, GFLAGS), + GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0, + RK3588_CLKGATE_CON(10), 5, GFLAGS), + GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0, + RK3588_CLKGATE_CON(10), 6, GFLAGS), + GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0, + RK3588_CLKGATE_CON(10), 7, GFLAGS), + GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(10), 3, GFLAGS), + + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(16), 14, GFLAGS), + COMPOSITE(DBCLK_GPIO1, "dbclk_gpio1", mux_24m_32k_p, 0, + RK3588_CLKSEL_CON(60), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(16), 15, GFLAGS), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(17), 0, GFLAGS), + COMPOSITE(DBCLK_GPIO2, "dbclk_gpio2", mux_24m_32k_p, 0, + RK3588_CLKSEL_CON(60), 14, 1, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(17), 1, GFLAGS), + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_top_root", 0, + RK3588_CLKGATE_CON(17), 2, GFLAGS), + COMPOSITE(DBCLK_GPIO3, "dbclk_gpio3", mux_24m_32k_p, 0, + RK3588_CLKSEL_CON(61), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(17), 3, GFLAGS), + GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_top_root", 0, + RK3588_CLKGATE_CON(17), 4, GFLAGS), + COMPOSITE(DBCLK_GPIO4, "dbclk_gpio4", mux_24m_32k_p, 0, + RK3588_CLKSEL_CON(61), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(17), 5, GFLAGS), + + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 8, GFLAGS), + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 9, GFLAGS), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 10, GFLAGS), + GATE(PCLK_I2C4, "pclk_i2c4", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 11, GFLAGS), + GATE(PCLK_I2C5, "pclk_i2c5", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 12, GFLAGS), + GATE(PCLK_I2C6, "pclk_i2c6", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 13, GFLAGS), + GATE(PCLK_I2C7, "pclk_i2c7", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 14, GFLAGS), + GATE(PCLK_I2C8, "pclk_i2c8", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 15, GFLAGS), + COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 6, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 0, GFLAGS), + COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 7, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 1, GFLAGS), + COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 8, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 2, GFLAGS), + COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 9, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 3, GFLAGS), + COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 10, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 4, GFLAGS), + COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 11, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 5, GFLAGS), + COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 12, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 6, GFLAGS), + COMPOSITE_NODIV(CLK_I2C8, "clk_i2c8", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 13, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 7, GFLAGS), + + GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_top_root", 0, + RK3588_CLKGATE_CON(18), 9, GFLAGS), + GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0, + RK3588_CLKGATE_CON(18), 10, GFLAGS), + GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0, + RK3588_CLKGATE_CON(18), 11, GFLAGS), + GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0, + RK3588_CLKGATE_CON(18), 13, GFLAGS), + GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0, + RK3588_CLKGATE_CON(18), 12, GFLAGS), + + GATE(PCLK_SARADC, "pclk_saradc", "pclk_top_root", 0, + RK3588_CLKGATE_CON(11), 14, GFLAGS), + COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_p, 0, + RK3588_CLKSEL_CON(40), 14, 1, MFLAGS, 6, 8, DFLAGS, + RK3588_CLKGATE_CON(11), 15, GFLAGS), + + GATE(PCLK_SPI0, "pclk_spi0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(14), 6, GFLAGS), + GATE(PCLK_SPI1, "pclk_spi1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(14), 7, GFLAGS), + GATE(PCLK_SPI2, "pclk_spi2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(14), 8, GFLAGS), + GATE(PCLK_SPI3, "pclk_spi3", "pclk_top_root", 0, + RK3588_CLKGATE_CON(14), 9, GFLAGS), + GATE(PCLK_SPI4, "pclk_spi4", "pclk_top_root", 0, + RK3588_CLKGATE_CON(14), 10, GFLAGS), + COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_150m_24m_p, 0, + RK3588_CLKSEL_CON(59), 2, 2, MFLAGS, + RK3588_CLKGATE_CON(14), 11, GFLAGS), + COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_150m_24m_p, 0, + RK3588_CLKSEL_CON(59), 4, 2, MFLAGS, + RK3588_CLKGATE_CON(14), 12, GFLAGS), + COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_150m_24m_p, 0, + RK3588_CLKSEL_CON(59), 6, 2, MFLAGS, + RK3588_CLKGATE_CON(14), 13, GFLAGS), + COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_150m_24m_p, 0, + RK3588_CLKSEL_CON(59), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(14), 14, GFLAGS), + COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_150m_24m_p, 0, + RK3588_CLKSEL_CON(59), 10, 2, MFLAGS, + RK3588_CLKGATE_CON(14), 15, GFLAGS), + + GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(18), 6, GFLAGS), + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 0, GFLAGS), + COMPOSITE(CLK_TSADC, "clk_tsadc", gpll_24m_p, 0, + RK3588_CLKSEL_CON(41), 8, 1, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(12), 1, GFLAGS), + + GATE(PCLK_UART1, "pclk_uart1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 2, GFLAGS), + GATE(PCLK_UART2, "pclk_uart2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 3, GFLAGS), + GATE(PCLK_UART3, "pclk_uart3", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 4, GFLAGS), + GATE(PCLK_UART4, "pclk_uart4", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 5, GFLAGS), + GATE(PCLK_UART5, "pclk_uart5", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 6, GFLAGS), + GATE(PCLK_UART6, "pclk_uart6", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 7, GFLAGS), + GATE(PCLK_UART7, "pclk_uart7", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 8, GFLAGS), + GATE(PCLK_UART8, "pclk_uart8", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 9, GFLAGS), + GATE(PCLK_UART9, "pclk_uart9", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 10, GFLAGS), + + COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(41), 14, 1, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(12), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(42), 0, + RK3588_CLKGATE_CON(12), 12, GFLAGS, + &rk3588_uart1_fracmux), + GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0, + RK3588_CLKGATE_CON(12), 13, GFLAGS), + COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(43), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(12), 14, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(44), 0, + RK3588_CLKGATE_CON(12), 15, GFLAGS, + &rk3588_uart2_fracmux), + GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0, + RK3588_CLKGATE_CON(13), 0, GFLAGS), + COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(45), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(13), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(46), 0, + RK3588_CLKGATE_CON(13), 2, GFLAGS, + &rk3588_uart3_fracmux), + GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0, + RK3588_CLKGATE_CON(13), 3, GFLAGS), + COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(47), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(13), 4, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(48), 0, + RK3588_CLKGATE_CON(13), 5, GFLAGS, + &rk3588_uart4_fracmux), + GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0, + RK3588_CLKGATE_CON(13), 6, GFLAGS), + COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(49), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(13), 7, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(50), 0, + RK3588_CLKGATE_CON(13), 8, GFLAGS, + &rk3588_uart5_fracmux), + GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0, + RK3588_CLKGATE_CON(13), 9, GFLAGS), + COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(51), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(13), 10, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(52), 0, + RK3588_CLKGATE_CON(13), 11, GFLAGS, + &rk3588_uart6_fracmux), + GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0, + RK3588_CLKGATE_CON(13), 12, GFLAGS), + COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(53), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(13), 13, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(54), 0, + RK3588_CLKGATE_CON(13), 14, GFLAGS, + &rk3588_uart7_fracmux), + GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0, + RK3588_CLKGATE_CON(13), 15, GFLAGS), + COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(55), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(14), 0, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(56), 0, + RK3588_CLKGATE_CON(14), 1, GFLAGS, + &rk3588_uart8_fracmux), + GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0, + RK3588_CLKGATE_CON(14), 2, GFLAGS), + COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(57), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(14), 3, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(58), 0, + RK3588_CLKGATE_CON(14), 4, GFLAGS, + &rk3588_uart9_fracmux), + GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0, + RK3588_CLKGATE_CON(14), 5, GFLAGS), + + /* center */ + COMPOSITE_NODIV(ACLK_CENTER_ROOT, "aclk_center_root", mux_700m_400m_200m_24m_p, + CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(165), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(69), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_CENTER_LOW_ROOT, "aclk_center_low_root", mux_500m_250m_100m_24m_p, + CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(165), 2, 2, MFLAGS, + RK3588_CLKGATE_CON(69), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_CENTER_ROOT, "hclk_center_root", mux_400m_200m_100m_24m_p, + CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(165), 4, 2, MFLAGS, + RK3588_CLKGATE_CON(69), 2, GFLAGS), + COMPOSITE_NODIV(PCLK_CENTER_ROOT, "pclk_center_root", mux_200m_100m_50m_24m_p, + CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(165), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, + RK3588_CLKGATE_CON(69), 3, GFLAGS), + GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(69), 5, GFLAGS), + GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(69), 6, GFLAGS), + COMPOSITE_NODIV(ACLK_CENTER_S200_ROOT, "aclk_center_s200_root", mux_200m_100m_50m_24m_p, + CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(165), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(69), 8, GFLAGS), + COMPOSITE_NODIV(ACLK_CENTER_S400_ROOT, "aclk_center_s400_root", mux_400m_200m_100m_24m_p, + CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(165), 10, 2, MFLAGS, + RK3588_CLKGATE_CON(69), 9, GFLAGS), + GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_center_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(69), 14, GFLAGS), + COMPOSITE_NODIV(CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root", mux_24m_100m_p, CLK_IGNORE_UNUSED, + RK3588_CLKSEL_CON(165), 12, 1, MFLAGS, + RK3588_CLKGATE_CON(69), 15, GFLAGS), + GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 0, + RK3588_CLKGATE_CON(70), 0, GFLAGS), + GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 0, + RK3588_CLKGATE_CON(70), 1, GFLAGS), + GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0, + RK3588_CLKGATE_CON(70), 2, GFLAGS), + COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(166), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(70), 4, GFLAGS), + GATE(PCLK_WDT, "pclk_wdt", "pclk_center_root", 0, + RK3588_CLKGATE_CON(70), 7, GFLAGS), + GATE(PCLK_TIMER, "pclk_timer", "pclk_center_root", 0, + RK3588_CLKGATE_CON(70), 8, GFLAGS), + GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(70), 9, GFLAGS), + GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(70), 10, GFLAGS), + + /* gpu */ + COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", gpll_cpll_aupll_npll_spll_p, 0, + RK3588_CLKSEL_CON(158), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(66), 1, GFLAGS), + GATE(CLK_GPU, "clk_gpu", "clk_gpu_src", 0, + RK3588_CLKGATE_CON(66), 4, GFLAGS), + GATE(CLK_GPU_COREGROUP, "clk_gpu_coregroup", "clk_gpu_src", 0, + RK3588_CLKGATE_CON(66), 6, GFLAGS), + COMPOSITE_NOMUX(CLK_GPU_STACKS, "clk_gpu_stacks", "clk_gpu_src", 0, + RK3588_CLKSEL_CON(159), 0, 5, DFLAGS, + RK3588_CLKGATE_CON(66), 7, GFLAGS), + GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0, + RK3588_CLKGATE_CON(67), 0, GFLAGS), + GATE(CLK_CORE_GPU_PVTM, "clk_core_gpu_pvtm", "clk_gpu_src", 0, + RK3588_CLKGATE_CON(67), 1, GFLAGS), + + /* isp1 */ + COMPOSITE(ACLK_ISP1_ROOT, "aclk_isp1_root", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(67), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(26), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_ISP1_ROOT, "hclk_isp1_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(67), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(26), 1, GFLAGS), + COMPOSITE(CLK_ISP1_CORE, "clk_isp1_core", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(67), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(26), 2, GFLAGS), + GATE(CLK_ISP1_CORE_MARVIN, "clk_isp1_core_marvin", "clk_isp1_core", 0, + RK3588_CLKGATE_CON(26), 3, GFLAGS), + GATE(CLK_ISP1_CORE_VICAP, "clk_isp1_core_vicap", "clk_isp1_core", 0, + RK3588_CLKGATE_CON(26), 4, GFLAGS), + + /* npu */ + COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(73), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(29), 0, GFLAGS), + COMPOSITE(CLK_NPU_DSU0, "clk_npu_dsu0", gpll_cpll_aupll_npll_spll_p, 0, + RK3588_CLKSEL_CON(73), 7, 3, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(29), 1, GFLAGS), + COMPOSITE_NODIV(PCLK_NPU_ROOT, "pclk_npu_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(74), 1, 2, MFLAGS, + RK3588_CLKGATE_CON(29), 4, GFLAGS), + GATE(ACLK_NPU1, "aclk_npu1", "clk_npu_dsu0", 0, + RK3588_CLKGATE_CON(27), 0, GFLAGS), + GATE(HCLK_NPU1, "hclk_npu1", "hclk_npu_root", 0, + RK3588_CLKGATE_CON(27), 2, GFLAGS), + GATE(ACLK_NPU2, "aclk_npu2", "clk_npu_dsu0", 0, + RK3588_CLKGATE_CON(28), 0, GFLAGS), + GATE(HCLK_NPU2, "hclk_npu2", "hclk_npu_root", 0, + RK3588_CLKGATE_CON(28), 2, GFLAGS), + COMPOSITE_NODIV(HCLK_NPU_CM0_ROOT, "hclk_npu_cm0_root", mux_400m_200m_100m_24m_p, 0, + RK3588_CLKSEL_CON(74), 5, 2, MFLAGS, + RK3588_CLKGATE_CON(30), 1, GFLAGS), + GATE(FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", "hclk_npu_cm0_root", 0, + RK3588_CLKGATE_CON(30), 3, GFLAGS), + COMPOSITE(CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc", mux_24m_32k_p, 0, + RK3588_CLKSEL_CON(74), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(30), 5, GFLAGS), + GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_root", 0, + RK3588_CLKGATE_CON(29), 12, GFLAGS), + GATE(PCLK_NPU_GRF, "pclk_npu_grf", "pclk_npu_root", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(29), 13, GFLAGS), + GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0, + RK3588_CLKGATE_CON(29), 14, GFLAGS), + GATE(CLK_CORE_NPU_PVTM, "clk_core_npu_pvtm", "clk_npu_dsu0", 0, + RK3588_CLKGATE_CON(29), 15, GFLAGS), + GATE(ACLK_NPU0, "aclk_npu0", "clk_npu_dsu0", 0, + RK3588_CLKGATE_CON(30), 6, GFLAGS), + GATE(HCLK_NPU0, "hclk_npu0", "hclk_npu_root", 0, + RK3588_CLKGATE_CON(30), 8, GFLAGS), + GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_npu_root", 0, + RK3588_CLKGATE_CON(29), 6, GFLAGS), + COMPOSITE_NODIV(CLK_NPUTIMER_ROOT, "clk_nputimer_root", mux_24m_100m_p, 0, + RK3588_CLKSEL_CON(74), 3, 1, MFLAGS, + RK3588_CLKGATE_CON(29), 7, GFLAGS), + GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0, + RK3588_CLKGATE_CON(29), 8, GFLAGS), + GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0, + RK3588_CLKGATE_CON(29), 9, GFLAGS), + GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_npu_root", 0, + RK3588_CLKGATE_CON(29), 10, GFLAGS), + GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0, + RK3588_CLKGATE_CON(29), 11, GFLAGS), + + /* nvm */ + COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(77), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(31), 0, GFLAGS), + COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(31), 1, GFLAGS), + GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, + RK3588_CLKGATE_CON(31), 5, GFLAGS), + COMPOSITE(CCLK_EMMC, "cclk_emmc", gpll_cpll_24m_p, 0, + RK3588_CLKSEL_CON(77), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3588_CLKGATE_CON(31), 6, GFLAGS), + COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(78), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(31), 7, GFLAGS), + GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0, + RK3588_CLKGATE_CON(31), 8, GFLAGS), + + COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_24m_p, 0, + RK3588_CLKSEL_CON(78), 12, 2, MFLAGS, 6, 6, DFLAGS, + RK3588_CLKGATE_CON(31), 9, GFLAGS), + + /* php */ + COMPOSITE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac0_ptp_ref_p, 0, + RK3588_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS, + RK3588_CLKGATE_CON(34), 10, GFLAGS), + COMPOSITE(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac1_ptp_ref_p, 0, + RK3588_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS, + RK3588_CLKGATE_CON(34), 11, GFLAGS), + COMPOSITE(CLK_GMAC_125M, "clk_gmac_125m", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(83), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3588_CLKGATE_CON(35), 5, GFLAGS), + COMPOSITE(CLK_GMAC_50M, "clk_gmac_50m", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(84), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(35), 6, GFLAGS), + + COMPOSITE(ACLK_PCIE_ROOT, "aclk_pcie_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(80), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(32), 6, GFLAGS), + COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(80), 13, 1, MFLAGS, 8, 5, DFLAGS, + RK3588_CLKGATE_CON(32), 7, GFLAGS), + COMPOSITE_NODIV(PCLK_PHP_ROOT, "pclk_php_root", mux_150m_50m_24m_p, 0, + RK3588_CLKSEL_CON(80), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(32), 0, GFLAGS), + GATE(ACLK_PHP_GIC_ITS, "aclk_php_gic_its", "aclk_pcie_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(34), 6, GFLAGS), + GATE(ACLK_PCIE_BRIDGE, "aclk_pcie_bridge", "aclk_pcie_root", 0, + RK3588_CLKGATE_CON(32), 8, GFLAGS), + GATE(ACLK_MMU_PCIE, "aclk_mmu_pcie", "aclk_pcie_bridge", 0, + RK3588_CLKGATE_CON(34), 7, GFLAGS), + GATE(ACLK_MMU_PHP, "aclk_mmu_php", "aclk_php_root", 0, + RK3588_CLKGATE_CON(34), 8, GFLAGS), + GATE(ACLK_PCIE_4L_DBI, "aclk_pcie_4l_dbi", "aclk_php_root", 0, + RK3588_CLKGATE_CON(32), 13, GFLAGS), + GATE(ACLK_PCIE_2L_DBI, "aclk_pcie_2l_dbi", "aclk_php_root", 0, + RK3588_CLKGATE_CON(32), 14, GFLAGS), + GATE(ACLK_PCIE_1L0_DBI, "aclk_pcie_1l0_dbi", "aclk_php_root", 0, + RK3588_CLKGATE_CON(32), 15, GFLAGS), + GATE(ACLK_PCIE_1L1_DBI, "aclk_pcie_1l1_dbi", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 0, GFLAGS), + GATE(ACLK_PCIE_1L2_DBI, "aclk_pcie_1l2_dbi", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 1, GFLAGS), + GATE(ACLK_PCIE_4L_MSTR, "aclk_pcie_4l_mstr", "aclk_mmu_pcie", 0, + RK3588_CLKGATE_CON(33), 2, GFLAGS), + GATE(ACLK_PCIE_2L_MSTR, "aclk_pcie_2l_mstr", "aclk_mmu_pcie", 0, + RK3588_CLKGATE_CON(33), 3, GFLAGS), + GATE(ACLK_PCIE_1L0_MSTR, "aclk_pcie_1l0_mstr", "aclk_mmu_pcie", 0, + RK3588_CLKGATE_CON(33), 4, GFLAGS), + GATE(ACLK_PCIE_1L1_MSTR, "aclk_pcie_1l1_mstr", "aclk_mmu_pcie", 0, + RK3588_CLKGATE_CON(33), 5, GFLAGS), + GATE(ACLK_PCIE_1L2_MSTR, "aclk_pcie_1l2_mstr", "aclk_mmu_pcie", 0, + RK3588_CLKGATE_CON(33), 6, GFLAGS), + GATE(ACLK_PCIE_4L_SLV, "aclk_pcie_4l_slv", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 7, GFLAGS), + GATE(ACLK_PCIE_2L_SLV, "aclk_pcie_2l_slv", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 8, GFLAGS), + GATE(ACLK_PCIE_1L0_SLV, "aclk_pcie_1l0_slv", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 9, GFLAGS), + GATE(ACLK_PCIE_1L1_SLV, "aclk_pcie_1l1_slv", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 10, GFLAGS), + GATE(ACLK_PCIE_1L2_SLV, "aclk_pcie_1l2_slv", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 11, GFLAGS), + GATE(PCLK_PCIE_4L, "pclk_pcie_4l", "pclk_php_root", 0, + RK3588_CLKGATE_CON(33), 12, GFLAGS), + GATE(PCLK_PCIE_2L, "pclk_pcie_2l", "pclk_php_root", 0, + RK3588_CLKGATE_CON(33), 13, GFLAGS), + GATE(PCLK_PCIE_1L0, "pclk_pcie_1l0", "pclk_php_root", 0, + RK3588_CLKGATE_CON(33), 14, GFLAGS), + GATE(PCLK_PCIE_1L1, "pclk_pcie_1l1", "pclk_php_root", 0, + RK3588_CLKGATE_CON(33), 15, GFLAGS), + GATE(PCLK_PCIE_1L2, "pclk_pcie_1l2", "pclk_php_root", 0, + RK3588_CLKGATE_CON(34), 0, GFLAGS), + GATE(CLK_PCIE_AUX0, "clk_pcie_aux0", "xin24m", 0, + RK3588_CLKGATE_CON(34), 1, GFLAGS), + GATE(CLK_PCIE_AUX1, "clk_pcie_aux1", "xin24m", 0, + RK3588_CLKGATE_CON(34), 2, GFLAGS), + GATE(CLK_PCIE_AUX2, "clk_pcie_aux2", "xin24m", 0, + RK3588_CLKGATE_CON(34), 3, GFLAGS), + GATE(CLK_PCIE_AUX3, "clk_pcie_aux3", "xin24m", 0, + RK3588_CLKGATE_CON(34), 4, GFLAGS), + GATE(CLK_PCIE_AUX4, "clk_pcie_aux4", "xin24m", 0, + RK3588_CLKGATE_CON(34), 5, GFLAGS), + GATE(CLK_PIPEPHY0_REF, "clk_pipephy0_ref", "xin24m", 0, + RK3588_CLKGATE_CON(37), 0, GFLAGS), + GATE(CLK_PIPEPHY1_REF, "clk_pipephy1_ref", "xin24m", 0, + RK3588_CLKGATE_CON(37), 1, GFLAGS), + GATE(CLK_PIPEPHY2_REF, "clk_pipephy2_ref", "xin24m", 0, + RK3588_CLKGATE_CON(37), 2, GFLAGS), + GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php_root", 0, + RK3588_CLKGATE_CON(32), 3, GFLAGS), + GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_php_root", 0, + RK3588_CLKGATE_CON(32), 4, GFLAGS), + GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_mmu_php", 0, + RK3588_CLKGATE_CON(32), 10, GFLAGS), + GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_mmu_php", 0, + RK3588_CLKGATE_CON(32), 11, GFLAGS), + GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", 0, + RK3588_CLKGATE_CON(37), 4, GFLAGS), + GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", 0, + RK3588_CLKGATE_CON(37), 5, GFLAGS), + GATE(CLK_PMALIVE2, "clk_pmalive2", "xin24m", 0, + RK3588_CLKGATE_CON(37), 6, GFLAGS), + GATE(ACLK_SATA0, "aclk_sata0", "aclk_mmu_php", 0, + RK3588_CLKGATE_CON(37), 7, GFLAGS), + GATE(ACLK_SATA1, "aclk_sata1", "aclk_mmu_php", 0, + RK3588_CLKGATE_CON(37), 8, GFLAGS), + GATE(ACLK_SATA2, "aclk_sata2", "aclk_mmu_php", 0, + RK3588_CLKGATE_CON(37), 9, GFLAGS), + COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(82), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(37), 10, GFLAGS), + COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(82), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3588_CLKGATE_CON(37), 11, GFLAGS), + COMPOSITE(CLK_RXOOB2, "clk_rxoob2", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(83), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(37), 12, GFLAGS), + GATE(ACLK_USB3OTG2, "aclk_usb3otg2", "aclk_mmu_php", 0, + RK3588_CLKGATE_CON(35), 7, GFLAGS), + GATE(SUSPEND_CLK_USB3OTG2, "suspend_clk_usb3otg2", "xin24m", 0, + RK3588_CLKGATE_CON(35), 8, GFLAGS), + GATE(REF_CLK_USB3OTG2, "ref_clk_usb3otg2", "xin24m", 0, + RK3588_CLKGATE_CON(35), 9, GFLAGS), + COMPOSITE(CLK_UTMI_OTG2, "clk_utmi_otg2", mux_150m_50m_24m_p, 0, + RK3588_CLKSEL_CON(84), 12, 2, MFLAGS, 8, 4, DFLAGS, + RK3588_CLKGATE_CON(35), 10, GFLAGS), + GATE(PCLK_PCIE_COMBO_PIPE_PHY0, "pclk_pcie_combo_pipe_phy0", "pclk_top_root", 0, + RK3588_PHP_CLKGATE_CON(0), 5, GFLAGS), + GATE(PCLK_PCIE_COMBO_PIPE_PHY1, "pclk_pcie_combo_pipe_phy1", "pclk_top_root", 0, + RK3588_PHP_CLKGATE_CON(0), 6, GFLAGS), + GATE(PCLK_PCIE_COMBO_PIPE_PHY2, "pclk_pcie_combo_pipe_phy2", "pclk_top_root", 0, + RK3588_PHP_CLKGATE_CON(0), 7, GFLAGS), + GATE(PCLK_PCIE_COMBO_PIPE_PHY, "pclk_pcie_combo_pipe_phy", "pclk_top_root", 0, + RK3588_PHP_CLKGATE_CON(0), 8, GFLAGS), + + /* rga */ + COMPOSITE(CLK_RGA3_1_CORE, "clk_rga3_1_core", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(174), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(76), 6, GFLAGS), + COMPOSITE(ACLK_RGA3_ROOT, "aclk_rga3_root", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(174), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(76), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_RGA3_ROOT, "hclk_rga3_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(174), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(76), 1, GFLAGS), + GATE(HCLK_RGA3_1, "hclk_rga3_1", "hclk_rga3_root", 0, + RK3588_CLKGATE_CON(76), 4, GFLAGS), + GATE(ACLK_RGA3_1, "aclk_rga3_1", "aclk_rga3_root", 0, + RK3588_CLKGATE_CON(76), 5, GFLAGS), + + /* vdec */ + COMPOSITE_NODIV(0, "hclk_rkvdec0_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(89), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(40), 0, GFLAGS), + COMPOSITE(0, "aclk_rkvdec0_root", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(89), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(40), 1, GFLAGS), + COMPOSITE(ACLK_RKVDEC_CCU, "aclk_rkvdec_ccu", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(89), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(40), 2, GFLAGS), + COMPOSITE(CLK_RKVDEC0_CA, "clk_rkvdec0_ca", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(90), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(40), 7, GFLAGS), + COMPOSITE(CLK_RKVDEC0_HEVC_CA, "clk_rkvdec0_hevc_ca", gpll_cpll_npll_1000m_p, 0, + RK3588_CLKSEL_CON(90), 11, 2, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(40), 8, GFLAGS), + COMPOSITE(CLK_RKVDEC0_CORE, "clk_rkvdec0_core", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(91), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(40), 9, GFLAGS), + COMPOSITE_NODIV(0, "hclk_rkvdec1_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(93), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(41), 0, GFLAGS), + COMPOSITE(0, "aclk_rkvdec1_root", gpll_cpll_aupll_npll_p, 0, + RK3588_CLKSEL_CON(93), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(41), 1, GFLAGS), + COMPOSITE(CLK_RKVDEC1_CA, "clk_rkvdec1_ca", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(93), 14, 1, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(41), 6, GFLAGS), + COMPOSITE(CLK_RKVDEC1_HEVC_CA, "clk_rkvdec1_hevc_ca", gpll_cpll_npll_1000m_p, 0, + RK3588_CLKSEL_CON(94), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(41), 7, GFLAGS), + COMPOSITE(CLK_RKVDEC1_CORE, "clk_rkvdec1_core", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(94), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(41), 8, GFLAGS), + + /* sdio */ + COMPOSITE_NODIV(0, "hclk_sdio_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(172), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(75), 0, GFLAGS), + COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", gpll_cpll_24m_p, 0, + RK3588_CLKSEL_CON(172), 8, 2, MFLAGS, 2, 6, DFLAGS, + RK3588_CLKGATE_CON(75), 3, GFLAGS), + MMC(SCLK_SDIO_DRV, "sdio_drv", "cclk_src_sdio", RK3588_SDIO_CON0, 1), + MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio", RK3588_SDIO_CON1, 1), + + /* usb */ + COMPOSITE(ACLK_USB_ROOT, "aclk_usb_root", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(96), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(42), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_USB_ROOT, "hclk_usb_root", mux_150m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(96), 6, 2, MFLAGS, + RK3588_CLKGATE_CON(42), 1, GFLAGS), + GATE(SUSPEND_CLK_USB3OTG0, "suspend_clk_usb3otg0", "xin24m", 0, + RK3588_CLKGATE_CON(42), 5, GFLAGS), + GATE(REF_CLK_USB3OTG0, "ref_clk_usb3otg0", "xin24m", 0, + RK3588_CLKGATE_CON(42), 6, GFLAGS), + GATE(SUSPEND_CLK_USB3OTG1, "suspend_clk_usb3otg1", "xin24m", 0, + RK3588_CLKGATE_CON(42), 8, GFLAGS), + GATE(REF_CLK_USB3OTG1, "ref_clk_usb3otg1", "xin24m", 0, + RK3588_CLKGATE_CON(42), 9, GFLAGS), + + /* vdpu */ + COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(44), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0, + RK3588_CLKSEL_CON(98), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(44), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(98), 9, 2, MFLAGS, + RK3588_CLKGATE_CON(44), 2, GFLAGS), + COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(99), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(44), 3, GFLAGS), + GATE(HCLK_IEP2P0, "hclk_iep2p0", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 4, GFLAGS), + COMPOSITE(CLK_IEP2P0_CORE, "clk_iep2p0_core", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(99), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(45), 6, GFLAGS), + GATE(HCLK_JPEG_ENCODER0, "hclk_jpeg_encoder0", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(44), 11, GFLAGS), + GATE(HCLK_JPEG_ENCODER1, "hclk_jpeg_encoder1", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(44), 13, GFLAGS), + GATE(HCLK_JPEG_ENCODER2, "hclk_jpeg_encoder2", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(44), 15, GFLAGS), + GATE(HCLK_JPEG_ENCODER3, "hclk_jpeg_encoder3", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 1, GFLAGS), + GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 3, GFLAGS), + GATE(HCLK_RGA2, "hclk_rga2", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 7, GFLAGS), + GATE(ACLK_RGA2, "aclk_rga2", "aclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 8, GFLAGS), + COMPOSITE(CLK_RGA2_CORE, "clk_rga2_core", gpll_cpll_npll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(100), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(45), 9, GFLAGS), + GATE(HCLK_RGA3_0, "hclk_rga3_0", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 10, GFLAGS), + GATE(ACLK_RGA3_0, "aclk_rga3_0", "aclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 11, GFLAGS), + COMPOSITE(CLK_RGA3_0_CORE, "clk_rga3_0_core", gpll_cpll_npll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(100), 13, 3, MFLAGS, 8, 5, DFLAGS, + RK3588_CLKGATE_CON(45), 12, GFLAGS), + GATE(HCLK_VPU, "hclk_vpu", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(44), 9, GFLAGS), + + /* venc */ + COMPOSITE_NODIV(HCLK_RKVENC1_ROOT, "hclk_rkvenc1_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(104), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(48), 0, GFLAGS), + COMPOSITE(ACLK_RKVENC1_ROOT, "aclk_rkvenc1_root", gpll_cpll_npll_p, 0, + RK3588_CLKSEL_CON(104), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(48), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_RKVENC0_ROOT, "hclk_rkvenc0_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(102), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(47), 0, GFLAGS), + COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0, + RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(47), 1, GFLAGS), + GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0, + RK3588_CLKGATE_CON(47), 4, GFLAGS), + GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0, + RK3588_CLKGATE_CON(47), 5, GFLAGS), + COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0, + RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(47), 6, GFLAGS), + COMPOSITE(CLK_RKVENC1_CORE, "clk_rkvenc1_core", gpll_cpll_aupll_npll_p, 0, + RK3588_CLKSEL_CON(104), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(48), 6, GFLAGS), + + /* vi */ + COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(49), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(106), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(49), 1, GFLAGS), + COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(106), 10, 2, MFLAGS, + RK3588_CLKGATE_CON(49), 2, GFLAGS), + COMPOSITE_NODIV(ICLK_CSIHOST01, "iclk_csihost01", mux_400m_200m_100m_24m_p, 0, + RK3588_CLKSEL_CON(108), 14, 2, MFLAGS, + RK3588_CLKGATE_CON(51), 10, GFLAGS), + GATE(ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 0, + RK3588_CLKGATE_CON(51), 11, GFLAGS), + GATE(ICLK_CSIHOST1, "iclk_csihost1", "iclk_csihost01", 0, + RK3588_CLKGATE_CON(51), 12, GFLAGS), + GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 4, GFLAGS), + GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 5, GFLAGS), + GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 6, GFLAGS), + GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 7, GFLAGS), + GATE(PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 8, GFLAGS), + GATE(PCLK_CSI_HOST_5, "pclk_csi_host_5", "pclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 9, GFLAGS), + GATE(ACLK_FISHEYE0, "aclk_fisheye0", "aclk_vi_root", 0, + RK3588_CLKGATE_CON(49), 14, GFLAGS), + GATE(HCLK_FISHEYE0, "hclk_fisheye0", "hclk_vi_root", 0, + RK3588_CLKGATE_CON(49), 15, GFLAGS), + COMPOSITE(CLK_FISHEYE0_CORE, "clk_fisheye0_core", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(108), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(50), 0, GFLAGS), + GATE(ACLK_FISHEYE1, "aclk_fisheye1", "aclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 1, GFLAGS), + GATE(HCLK_FISHEYE1, "hclk_fisheye1", "hclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 2, GFLAGS), + COMPOSITE(CLK_FISHEYE1_CORE, "clk_fisheye1_core", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(108), 12, 2, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(50), 3, GFLAGS), + COMPOSITE(CLK_ISP0_CORE, "clk_isp0_core", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(107), 11, 2, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(49), 9, GFLAGS), + GATE(CLK_ISP0_CORE_MARVIN, "clk_isp0_core_marvin", "clk_isp0_core", 0, + RK3588_CLKGATE_CON(49), 10, GFLAGS), + GATE(CLK_ISP0_CORE_VICAP, "clk_isp0_core_vicap", "clk_isp0_core", 0, + RK3588_CLKGATE_CON(49), 11, GFLAGS), + GATE(ACLK_ISP0, "aclk_isp0", "aclk_vi_root", 0, + RK3588_CLKGATE_CON(49), 12, GFLAGS), + GATE(HCLK_ISP0, "hclk_isp0", "hclk_vi_root", 0, + RK3588_CLKGATE_CON(49), 13, GFLAGS), + COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(107), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(49), 6, GFLAGS), + GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0, + RK3588_CLKGATE_CON(49), 7, GFLAGS), + GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0, + RK3588_CLKGATE_CON(49), 8, GFLAGS), + + /* vo0 */ + COMPOSITE(ACLK_VO0_ROOT, "aclk_vo0_root", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(116), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(55), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_VO0_ROOT, "hclk_vo0_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(116), 6, 2, MFLAGS, + RK3588_CLKGATE_CON(55), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_VO0_S_ROOT, "hclk_vo0_s_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(116), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(55), 2, GFLAGS), + COMPOSITE_NODIV(PCLK_VO0_ROOT, "pclk_vo0_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(116), 10, 2, MFLAGS, + RK3588_CLKGATE_CON(55), 3, GFLAGS), + COMPOSITE_NODIV(PCLK_VO0_S_ROOT, "pclk_vo0_s_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(116), 12, 2, MFLAGS, + RK3588_CLKGATE_CON(55), 4, GFLAGS), + GATE(PCLK_DP0, "pclk_dp0", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 4, GFLAGS), + GATE(PCLK_DP1, "pclk_dp1", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 5, GFLAGS), + GATE(PCLK_S_DP0, "pclk_s_dp0", "pclk_vo0_s_root", 0, + RK3588_CLKGATE_CON(56), 6, GFLAGS), + GATE(PCLK_S_DP1, "pclk_s_dp1", "pclk_vo0_s_root", 0, + RK3588_CLKGATE_CON(56), 7, GFLAGS), + GATE(CLK_DP0, "clk_dp0", "aclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 8, GFLAGS), + GATE(CLK_DP1, "clk_dp1", "aclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 9, GFLAGS), + GATE(HCLK_HDCP_KEY0, "hclk_hdcp_key0", "hclk_vo0_s_root", 0, + RK3588_CLKGATE_CON(55), 11, GFLAGS), + GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(55), 14, GFLAGS), + GATE(ACLK_TRNG0, "aclk_trng0", "aclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 0, GFLAGS), + GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 1, GFLAGS), + GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(55), 10, GFLAGS), + COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(56), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S4_8CH_TX_FRAC, "clk_i2s4_8ch_tx_frac", "clk_i2s4_8ch_tx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(119), 0, + RK3588_CLKGATE_CON(56), 12, GFLAGS, + &rk3588_i2s4_8ch_tx_fracmux), + GATE(MCLK_I2S4_8CH_TX, "mclk_i2s4_8ch_tx", "clk_i2s4_8ch_tx", 0, + RK3588_CLKGATE_CON(56), 13, GFLAGS), + COMPOSITE(CLK_I2S8_8CH_TX_SRC, "clk_i2s8_8ch_tx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(120), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(56), 15, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S8_8CH_TX_FRAC, "clk_i2s8_8ch_tx_frac", "clk_i2s8_8ch_tx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(121), 0, + RK3588_CLKGATE_CON(57), 0, GFLAGS, + &rk3588_i2s8_8ch_tx_fracmux), + GATE(MCLK_I2S8_8CH_TX, "mclk_i2s8_8ch_tx", "clk_i2s8_8ch_tx", 0, + RK3588_CLKGATE_CON(57), 1, GFLAGS), + COMPOSITE(CLK_SPDIF2_DP0_SRC, "clk_spdif2_dp0_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(122), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(57), 3, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF2_DP0_FRAC, "clk_spdif2_dp0_frac", "clk_spdif2_dp0_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(123), 0, + RK3588_CLKGATE_CON(57), 4, GFLAGS, + &rk3588_spdif2_dp0_fracmux), + GATE(MCLK_SPDIF2_DP0, "mclk_spdif2_dp0", "clk_spdif2_dp0", 0, + RK3588_CLKGATE_CON(57), 5, GFLAGS), + GATE(MCLK_SPDIF2, "mclk_spdif2", "clk_spdif2_dp0", 0, + RK3588_CLKGATE_CON(57), 6, GFLAGS), + COMPOSITE(CLK_SPDIF5_DP1_SRC, "clk_spdif5_dp1_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(57), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF5_DP1_FRAC, "clk_spdif5_dp1_frac", "clk_spdif5_dp1_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(125), 0, + RK3588_CLKGATE_CON(57), 9, GFLAGS, + &rk3588_spdif5_dp1_fracmux), + GATE(MCLK_SPDIF5_DP1, "mclk_spdif5_dp1", "clk_spdif5_dp1", 0, + RK3588_CLKGATE_CON(57), 10, GFLAGS), + GATE(MCLK_SPDIF5, "mclk_spdif5", "clk_spdif5_dp1", 0, + RK3588_CLKGATE_CON(57), 11, GFLAGS), + COMPOSITE_NOMUX(CLK_AUX16M_0, "clk_aux16m_0", "gpll", 0, + RK3588_CLKSEL_CON(117), 0, 8, DFLAGS, + RK3588_CLKGATE_CON(56), 2, GFLAGS), + COMPOSITE_NOMUX(CLK_AUX16M_1, "clk_aux16m_1", "gpll", 0, + RK3588_CLKSEL_CON(117), 8, 8, DFLAGS, + RK3588_CLKGATE_CON(56), 3, GFLAGS), + + /* vo1 */ + COMPOSITE_HALFDIV(CLK_HDMITRX_REFSRC, "clk_hdmitrx_refsrc", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(157), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(65), 9, GFLAGS), + COMPOSITE(ACLK_HDCP1_ROOT, "aclk_hdcp1_root", aclk_hdcp1_root_p, 0, + RK3588_CLKSEL_CON(128), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(59), 0, GFLAGS), + COMPOSITE(ACLK_HDMIRX_ROOT, "aclk_hdmirx_root", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(128), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(59), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_VO1_ROOT, "hclk_vo1_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(128), 13, 2, MFLAGS, + RK3588_CLKGATE_CON(59), 2, GFLAGS), + COMPOSITE_NODIV(HCLK_VO1_S_ROOT, "hclk_vo1_s_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(129), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(59), 3, GFLAGS), + COMPOSITE_NODIV(PCLK_VO1_ROOT, "pclk_vo1_root", mux_150m_100m_24m_p, 0, + RK3588_CLKSEL_CON(129), 2, 2, MFLAGS, + RK3588_CLKGATE_CON(59), 4, GFLAGS), + COMPOSITE_NODIV(PCLK_VO1_S_ROOT, "pclk_vo1_s_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(129), 4, 2, MFLAGS, + RK3588_CLKGATE_CON(59), 5, GFLAGS), + COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0, + RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(52), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0, + RK3588_CLKSEL_CON(110), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(52), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(110), 10, 2, MFLAGS, + RK3588_CLKGATE_CON(52), 2, GFLAGS), + COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(110), 12, 2, MFLAGS, + RK3588_CLKGATE_CON(52), 3, GFLAGS), + COMPOSITE(ACLK_VO1USB_TOP_ROOT, "aclk_vo1usb_top_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(170), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(74), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_VO1USB_TOP_ROOT, "hclk_vo1usb_top_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(170), 6, 2, MFLAGS, + RK3588_CLKGATE_CON(74), 2, GFLAGS), + MUX(ACLK_VOP_SUB_SRC, "aclk_vop_sub_src", aclk_vop_sub_src_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(115), 9, 1, MFLAGS), + GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(62), 0, GFLAGS), + GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0, + RK3588_CLKGATE_CON(62), 1, GFLAGS), + COMPOSITE_NODIV(CLK_EDP0_200M, "clk_edp0_200m", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(140), 1, 2, MFLAGS, + RK3588_CLKGATE_CON(62), 2, GFLAGS), + GATE(PCLK_EDP1, "pclk_edp1", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(62), 3, GFLAGS), + GATE(CLK_EDP1_24M, "clk_edp1_24m", "xin24m", 0, + RK3588_CLKGATE_CON(62), 4, GFLAGS), + COMPOSITE_NODIV(CLK_EDP1_200M, "clk_edp1_200m", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(140), 3, 2, MFLAGS, + RK3588_CLKGATE_CON(62), 5, GFLAGS), + GATE(HCLK_HDCP_KEY1, "hclk_hdcp_key1", "hclk_vo1_s_root", 0, + RK3588_CLKGATE_CON(60), 4, GFLAGS), + GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(60), 7, GFLAGS), + GATE(ACLK_HDMIRX, "aclk_hdmirx", "aclk_hdmirx_root", 0, + RK3588_CLKGATE_CON(61), 9, GFLAGS), + GATE(PCLK_HDMIRX, "pclk_hdmirx", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(61), 10, GFLAGS), + GATE(CLK_HDMIRX_REF, "clk_hdmirx_ref", "aclk_hdcp1_root", 0, + RK3588_CLKGATE_CON(61), 11, GFLAGS), + COMPOSITE(CLK_HDMIRX_AUD_SRC, "clk_hdmirx_aud_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(138), 8, 1, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(61), 12, GFLAGS), + COMPOSITE_FRACMUX(CLK_HDMIRX_AUD_FRAC, "clk_hdmirx_aud_frac", "clk_hdmirx_aud_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(139), 0, + RK3588_CLKGATE_CON(61), 13, GFLAGS, + &rk3588_hdmirx_aud_fracmux), + GATE(CLK_HDMIRX_AUD, "clk_hdmirx_aud", "clk_hdmirx_aud_mux", 0, + RK3588_CLKGATE_CON(61), 14, GFLAGS), + GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(60), 11, GFLAGS), + COMPOSITE(CLK_HDMITX0_EARC, "clk_hdmitx0_earc", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(133), 6, 1, MFLAGS, 1, 5, DFLAGS, + RK3588_CLKGATE_CON(60), 15, GFLAGS), + GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_hdcp1_root", 0, + RK3588_CLKGATE_CON(61), 0, GFLAGS), + GATE(PCLK_HDMITX1, "pclk_hdmitx1", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(61), 2, GFLAGS), + COMPOSITE(CLK_HDMITX1_EARC, "clk_hdmitx1_earc", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(136), 6, 1, MFLAGS, 1, 5, DFLAGS, + RK3588_CLKGATE_CON(61), 6, GFLAGS), + GATE(CLK_HDMITX1_REF, "clk_hdmitx1_ref", "aclk_hdcp1_root", 0, + RK3588_CLKGATE_CON(61), 7, GFLAGS), + GATE(ACLK_TRNG1, "aclk_trng1", "aclk_hdcp1_root", 0, + RK3588_CLKGATE_CON(60), 9, GFLAGS), + GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(60), 10, GFLAGS), + GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(59), 12, GFLAGS), + GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0, + RK3588_CLKGATE_CON(59), 14, GFLAGS), + GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0, + RK3588_CLKGATE_CON(59), 15, GFLAGS), + GATE(PCLK_S_HDMIRX, "pclk_s_hdmirx", "pclk_vo1_s_root", 0, + RK3588_CLKGATE_CON(65), 8, GFLAGS), + COMPOSITE(CLK_I2S10_8CH_RX_SRC, "clk_i2s10_8ch_rx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(155), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(65), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S10_8CH_RX_FRAC, "clk_i2s10_8ch_rx_frac", "clk_i2s10_8ch_rx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(156), 0, + RK3588_CLKGATE_CON(65), 6, GFLAGS, + &rk3588_i2s10_8ch_rx_fracmux), + GATE(MCLK_I2S10_8CH_RX, "mclk_i2s10_8ch_rx", "clk_i2s10_8ch_rx", 0, + RK3588_CLKGATE_CON(65), 7, GFLAGS), + COMPOSITE(CLK_I2S7_8CH_RX_SRC, "clk_i2s7_8ch_rx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(129), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(60), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S7_8CH_RX_FRAC, "clk_i2s7_8ch_rx_frac", "clk_i2s7_8ch_rx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(130), 0, + RK3588_CLKGATE_CON(60), 2, GFLAGS, + &rk3588_i2s7_8ch_rx_fracmux), + GATE(MCLK_I2S7_8CH_RX, "mclk_i2s7_8ch_rx", "clk_i2s7_8ch_rx", 0, + RK3588_CLKGATE_CON(60), 3, GFLAGS), + COMPOSITE(CLK_I2S9_8CH_RX_SRC, "clk_i2s9_8ch_rx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(153), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(65), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S9_8CH_RX_FRAC, "clk_i2s9_8ch_rx_frac", "clk_i2s9_8ch_rx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(154), 0, + RK3588_CLKGATE_CON(65), 2, GFLAGS, + &rk3588_i2s9_8ch_rx_fracmux), + GATE(MCLK_I2S9_8CH_RX, "mclk_i2s9_8ch_rx", "clk_i2s9_8ch_rx", 0, + RK3588_CLKGATE_CON(65), 3, GFLAGS), + COMPOSITE(CLK_I2S5_8CH_TX_SRC, "clk_i2s5_8ch_tx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(140), 10, 1, MFLAGS, 5, 5, DFLAGS, + RK3588_CLKGATE_CON(62), 6, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac", "clk_i2s5_8ch_tx_src", 0, + RK3588_CLKSEL_CON(141), 0, + RK3588_CLKGATE_CON(62), 7, GFLAGS, + &rk3588_i2s5_8ch_tx_fracmux), + GATE(MCLK_I2S5_8CH_TX, "mclk_i2s5_8ch_tx", "clk_i2s5_8ch_tx", 0, + RK3588_CLKGATE_CON(62), 8, GFLAGS), + COMPOSITE(CLK_I2S6_8CH_TX_SRC, "clk_i2s6_8ch_tx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(144), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(62), 13, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S6_8CH_TX_FRAC, "clk_i2s6_8ch_tx_frac", "clk_i2s6_8ch_tx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(145), 0, + RK3588_CLKGATE_CON(62), 14, GFLAGS, + &rk3588_i2s6_8ch_tx_fracmux), + GATE(MCLK_I2S6_8CH_TX, "mclk_i2s6_8ch_tx", "clk_i2s6_8ch_tx", 0, + RK3588_CLKGATE_CON(62), 15, GFLAGS), + COMPOSITE(CLK_I2S6_8CH_RX_SRC, "clk_i2s6_8ch_rx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(146), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(63), 0, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S6_8CH_RX_FRAC, "clk_i2s6_8ch_rx_frac", "clk_i2s6_8ch_rx_src", 0, + RK3588_CLKSEL_CON(147), 0, + RK3588_CLKGATE_CON(63), 1, GFLAGS, + &rk3588_i2s6_8ch_rx_fracmux), + GATE(MCLK_I2S6_8CH_RX, "mclk_i2s6_8ch_rx", "clk_i2s6_8ch_rx", 0, + RK3588_CLKGATE_CON(63), 2, GFLAGS), + MUX(I2S6_8CH_MCLKOUT, "i2s6_8ch_mclkout", i2s6_8ch_mclkout_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(148), 2, 2, MFLAGS), + COMPOSITE(CLK_SPDIF3_SRC, "clk_spdif3_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(148), 9, 1, MFLAGS, 4, 5, DFLAGS, + RK3588_CLKGATE_CON(63), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF3_FRAC, "clk_spdif3_frac", "clk_spdif3_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(149), 0, + RK3588_CLKGATE_CON(63), 6, GFLAGS, + &rk3588_spdif3_fracmux), + GATE(MCLK_SPDIF3, "mclk_spdif3", "clk_spdif3", 0, + RK3588_CLKGATE_CON(63), 7, GFLAGS), + COMPOSITE(CLK_SPDIF4_SRC, "clk_spdif4_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(150), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(63), 9, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF4_FRAC, "clk_spdif4_frac", "clk_spdif4_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(151), 0, + RK3588_CLKGATE_CON(63), 10, GFLAGS, + &rk3588_spdif4_fracmux), + GATE(MCLK_SPDIF4, "mclk_spdif4", "clk_spdif4", 0, + RK3588_CLKGATE_CON(63), 11, GFLAGS), + COMPOSITE(MCLK_SPDIFRX0, "mclk_spdifrx0", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(152), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(63), 13, GFLAGS), + COMPOSITE(MCLK_SPDIFRX1, "mclk_spdifrx1", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(152), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(63), 15, GFLAGS), + COMPOSITE(MCLK_SPDIFRX2, "mclk_spdifrx2", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(153), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(64), 1, GFLAGS), + GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0, + RK3588_CLKGATE_CON(73), 12, GFLAGS), + GATE(CLK_HDMIHDP1, "clk_hdmihdp1", "xin24m", 0, + RK3588_CLKGATE_CON(73), 13, GFLAGS), + GATE(PCLK_HDPTX0, "pclk_hdptx0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(72), 5, GFLAGS), + GATE(PCLK_HDPTX1, "pclk_hdptx1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(72), 6, GFLAGS), + GATE(PCLK_USBDPPHY0, "pclk_usbdpphy0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(72), 2, GFLAGS), + GATE(PCLK_USBDPPHY1, "pclk_usbdpphy1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(72), 4, GFLAGS), + GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0, + RK3588_CLKGATE_CON(52), 8, GFLAGS), + GATE(ACLK_VOP, "aclk_vop", "aclk_vop_sub_src", 0, + RK3588_CLKGATE_CON(52), 9, GFLAGS), + COMPOSITE(DCLK_VOP0_SRC, "dclk_vop0_src", gpll_cpll_v0pll_aupll_p, 0, + RK3588_CLKSEL_CON(111), 7, 2, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(52), 10, GFLAGS), + COMPOSITE(DCLK_VOP1_SRC, "dclk_vop1_src", gpll_cpll_v0pll_aupll_p, 0, + RK3588_CLKSEL_CON(111), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(52), 11, GFLAGS), + COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3588_CLKSEL_CON(112), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(52), 12, GFLAGS), + COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3588_CLKSEL_CON(112), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(52), 13, GFLAGS), + COMPOSITE_NODIV(DCLK_VOP1, "dclk_vop1", dclk_vop1_p, + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3588_CLKSEL_CON(112), 9, 2, MFLAGS, + RK3588_CLKGATE_CON(53), 0, GFLAGS), + COMPOSITE_NODIV(DCLK_VOP2, "dclk_vop2", dclk_vop2_p, + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3588_CLKSEL_CON(112), 11, 2, MFLAGS, + RK3588_CLKGATE_CON(53), 1, GFLAGS), + COMPOSITE(DCLK_VOP3, "dclk_vop3", gpll_cpll_v0pll_aupll_p, 0, + RK3588_CLKSEL_CON(113), 7, 2, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(53), 2, GFLAGS), + GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vop_root", 0, + RK3588_CLKGATE_CON(53), 4, GFLAGS), + GATE(PCLK_DSIHOST1, "pclk_dsihost1", "pclk_vop_root", 0, + RK3588_CLKGATE_CON(53), 5, GFLAGS), + COMPOSITE(CLK_DSIHOST0, "clk_dsihost0", gpll_cpll_v0pll_spll_p, 0, + RK3588_CLKSEL_CON(114), 7, 2, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(53), 6, GFLAGS), + COMPOSITE(CLK_DSIHOST1, "clk_dsihost1", gpll_cpll_v0pll_spll_p, 0, + RK3588_CLKSEL_CON(115), 7, 2, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(53), 7, GFLAGS), + GATE(CLK_VOP_PMU, "clk_vop_pmu", "xin24m", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(53), 8, GFLAGS), + GATE(ACLK_VOP_DOBY, "aclk_vop_doby", "aclk_vop_root", 0, + RK3588_CLKGATE_CON(53), 10, GFLAGS), + GATE(CLK_USBDP_PHY0_IMMORTAL, "clk_usbdp_phy0_immortal", "xin24m", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(2), 8, GFLAGS), + GATE(CLK_USBDP_PHY1_IMMORTAL, "clk_usbdp_phy1_immortal", "xin24m", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(2), 15, GFLAGS), + + GATE(CLK_REF_PIPE_PHY0_OSC_SRC, "clk_ref_pipe_phy0_osc_src", "xin24m", 0, + RK3588_CLKGATE_CON(77), 0, GFLAGS), + GATE(CLK_REF_PIPE_PHY1_OSC_SRC, "clk_ref_pipe_phy1_osc_src", "xin24m", 0, + RK3588_CLKGATE_CON(77), 1, GFLAGS), + GATE(CLK_REF_PIPE_PHY2_OSC_SRC, "clk_ref_pipe_phy2_osc_src", "xin24m", 0, + RK3588_CLKGATE_CON(77), 2, GFLAGS), + COMPOSITE_NOMUX(CLK_REF_PIPE_PHY0_PLL_SRC, "clk_ref_pipe_phy0_pll_src", "ppll", 0, + RK3588_CLKSEL_CON(176), 0, 6, DFLAGS, + RK3588_CLKGATE_CON(77), 3, GFLAGS), + COMPOSITE_NOMUX(CLK_REF_PIPE_PHY1_PLL_SRC, "clk_ref_pipe_phy1_pll_src", "ppll", 0, + RK3588_CLKSEL_CON(176), 6, 6, DFLAGS, + RK3588_CLKGATE_CON(77), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_REF_PIPE_PHY2_PLL_SRC, "clk_ref_pipe_phy2_pll_src", "ppll", 0, + RK3588_CLKSEL_CON(177), 0, 6, DFLAGS, + RK3588_CLKGATE_CON(77), 5, GFLAGS), + MUX(CLK_REF_PIPE_PHY0, "clk_ref_pipe_phy0", clk_ref_pipe_phy0_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(177), 6, 1, MFLAGS), + MUX(CLK_REF_PIPE_PHY1, "clk_ref_pipe_phy1", clk_ref_pipe_phy1_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(177), 7, 1, MFLAGS), + MUX(CLK_REF_PIPE_PHY2, "clk_ref_pipe_phy2", clk_ref_pipe_phy2_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(177), 8, 1, MFLAGS), + + /* pmu */ + COMPOSITE(CLK_PMU1_300M_SRC, "clk_pmu1_300m_src", pmu_300m_24m_p, 0, + RK3588_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 10, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE(CLK_PMU1_400M_SRC, "clk_pmu1_400m_src", pmu_400m_24m_p, 0, + RK3588_PMU_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_PMU1_50M_SRC, "clk_pmu1_50m_src", "clk_pmu1_400m_src", 0, + RK3588_PMU_CLKSEL_CON(0), 0, 4, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 0, GFLAGS), + COMPOSITE_NOMUX(CLK_PMU1_100M_SRC, "clk_pmu1_100m_src", "clk_pmu1_400m_src", 0, + RK3588_PMU_CLKSEL_CON(0), 4, 3, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_PMU1_200M_SRC, "clk_pmu1_200m_src", "clk_pmu1_400m_src", 0, + RK3588_PMU_CLKSEL_CON(0), 7, 3, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 2, GFLAGS), + COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", hclk_pmu1_root_p, CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(1), 6, 2, MFLAGS, + RK3588_PMU_CLKGATE_CON(0), 5, GFLAGS), + COMPOSITE_NODIV(PCLK_PMU1_ROOT, "pclk_pmu1_root", pmu_100m_50m_24m_src_p, CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(1), 8, 2, MFLAGS, + RK3588_PMU_CLKGATE_CON(0), 7, GFLAGS), + GATE(PCLK_PMU0_ROOT, "pclk_pmu0_root", "pclk_pmu1_root", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(5), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", hclk_pmu_cm0_root_p, CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(1), 10, 2, MFLAGS, + RK3588_PMU_CLKGATE_CON(0), 8, GFLAGS), + GATE(CLK_PMU0, "clk_pmu0", "xin24m", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(5), 1, GFLAGS), + GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(5), 2, GFLAGS), + GATE(PCLK_PMU0IOC, "pclk_pmu0ioc", "pclk_pmu0_root", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(5), 4, GFLAGS), + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0, + RK3588_PMU_CLKGATE_CON(5), 5, GFLAGS), + COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0, + RK3588_PMU_CLKSEL_CON(17), 0, 1, MFLAGS, + RK3588_PMU_CLKGATE_CON(5), 6, GFLAGS), + GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu0_root", 0, + RK3588_PMU_CLKGATE_CON(2), 1, GFLAGS), + COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", pmu_200m_100m_p, 0, + RK3588_PMU_CLKSEL_CON(3), 6, 1, MFLAGS, + RK3588_PMU_CLKGATE_CON(2), 2, GFLAGS), + GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_pmu1_root", 0, + RK3588_PMU_CLKGATE_CON(2), 7, GFLAGS), + COMPOSITE_NOMUX(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", "cpll", 0, + RK3588_PMU_CLKSEL_CON(5), 2, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(2), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", + CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(6), 0, + RK3588_PMU_CLKGATE_CON(2), 9, GFLAGS, + &rk3588_i2s1_8ch_tx_fracmux), + GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0, + RK3588_PMU_CLKGATE_CON(2), 10, GFLAGS), + COMPOSITE_NOMUX(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", "cpll", 0, + RK3588_PMU_CLKSEL_CON(7), 2, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(2), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", + CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(8), 0, + RK3588_PMU_CLKGATE_CON(2), 12, GFLAGS, + &rk3588_i2s1_8ch_rx_fracmux), + GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0, + RK3588_PMU_CLKGATE_CON(2), 13, GFLAGS), + MUX(I2S1_8CH_MCLKOUT, "i2s1_8ch_mclkout", i2s1_8ch_mclkout_p, CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(9), 2, 2, MFLAGS), + GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu0_root", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(1), 0, GFLAGS), + GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu0", CLK_IGNORE_UNUSED, + RK3588_PMU_CLKGATE_CON(1), 1, GFLAGS), + GATE(CLK_PMU1, "clk_pmu1", "clk_pmu0", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(1), 3, GFLAGS), + GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0, + RK3588_PMU_CLKGATE_CON(2), 14, GFLAGS), + COMPOSITE_NODIV(MCLK_PDM0, "mclk_pdm0", mclk_pdm0_p, 0, + RK3588_PMU_CLKSEL_CON(9), 4, 1, MFLAGS, + RK3588_PMU_CLKGATE_CON(2), 15, GFLAGS), + GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0, + RK3588_PMU_CLKGATE_CON(3), 0, GFLAGS), + GATE(FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", "hclk_pmu_cm0_root", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(0), 13, GFLAGS), + COMPOSITE(CLK_PMU_CM0_RTC, "clk_pmu_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 15, GFLAGS), + GATE(PCLK_PMU1_IOC, "pclk_pmu1_ioc", "pclk_pmu0_root", CLK_IGNORE_UNUSED, + RK3588_PMU_CLKGATE_CON(1), 5, GFLAGS), + GATE(PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu0_root", 0, + RK3588_PMU_CLKGATE_CON(1), 12, GFLAGS), + COMPOSITE_NODIV(CLK_PMU1PWM, "clk_pmu1pwm", pmu_100m_50m_24m_src_p, 0, + RK3588_PMU_CLKSEL_CON(2), 9, 2, MFLAGS, + RK3588_PMU_CLKGATE_CON(1), 13, GFLAGS), + GATE(CLK_PMU1PWM_CAPTURE, "clk_pmu1pwm_capture", "xin24m", 0, + RK3588_PMU_CLKGATE_CON(1), 14, GFLAGS), + GATE(PCLK_PMU1TIMER, "pclk_pmu1timer", "pclk_pmu0_root", 0, + RK3588_PMU_CLKGATE_CON(1), 8, GFLAGS), + COMPOSITE_NODIV(CLK_PMU1TIMER_ROOT, "clk_pmu1timer_root", pmu_24m_32k_100m_src_p, 0, + RK3588_PMU_CLKSEL_CON(2), 7, 2, MFLAGS, + RK3588_PMU_CLKGATE_CON(1), 9, GFLAGS), + GATE(CLK_PMU1TIMER0, "clk_pmu1timer0", "clk_pmu1timer_root", 0, + RK3588_PMU_CLKGATE_CON(1), 10, GFLAGS), + GATE(CLK_PMU1TIMER1, "clk_pmu1timer1", "clk_pmu1timer_root", 0, + RK3588_PMU_CLKGATE_CON(1), 11, GFLAGS), + COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "cpll", 0, + RK3588_PMU_CLKSEL_CON(3), 7, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(2), 3, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(4), 0, + RK3588_PMU_CLKGATE_CON(2), 4, GFLAGS, + &rk3588_uart0_fracmux), + GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0, + RK3588_PMU_CLKGATE_CON(2), 5, GFLAGS), + GATE(PCLK_UART0, "pclk_uart0", "pclk_pmu0_root", 0, + RK3588_PMU_CLKGATE_CON(2), 6, GFLAGS), + GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu0_root", 0, + RK3588_PMU_CLKGATE_CON(1), 6, GFLAGS), + COMPOSITE_NODIV(TCLK_PMU1WDT, "tclk_pmu1wdt", mux_24m_32k_p, 0, + RK3588_PMU_CLKSEL_CON(2), 6, 1, MFLAGS, + RK3588_PMU_CLKGATE_CON(1), 7, GFLAGS), + COMPOSITE(CLK_CR_PARA, "clk_cr_para", mux_24m_ppll_spll_p, 0, + RK3588_PMU_CLKSEL_CON(15), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(4), 11, GFLAGS), + COMPOSITE(CLK_USB2PHY_HDPTXRXPHY_REF, "clk_usb2phy_hdptxrxphy_ref", mux_24m_ppll_p, + CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(14), 14, 1, MFLAGS, 9, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(4), 7, GFLAGS), + COMPOSITE(CLK_USBDPPHY_MIPIDCPPHY_REF, "clk_usbdpphy_mipidcpphy_ref", mux_24m_ppll_spll_p, + CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(14), 7, 2, MFLAGS, 0, 7, DFLAGS, + RK3588_PMU_CLKGATE_CON(4), 3, GFLAGS), + + GATE(CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll", 0, + RK3588_PHYREF_ALT_GATE, 0, GFLAGS), + GATE(CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll", 0, + RK3588_PHYREF_ALT_GATE, 1, GFLAGS), + GATE(CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll", 0, + RK3588_PHYREF_ALT_GATE, 2, GFLAGS), + GATE(CLK_PHY1_REF_ALT_M, "clk_phy1_ref_alt_m", "ppll", 0, + RK3588_PHYREF_ALT_GATE, 3, GFLAGS), + + GATE(HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 12, GFLAGS), + GATE(HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 14, GFLAGS), + GATE(HCLK_SPDIFRX2, "hclk_spdifrx2", "hclk_vo1", 0, + RK3588_CLKGATE_CON(64), 0, GFLAGS), + GATE(HCLK_SPDIF4, "hclk_spdif4", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 8, GFLAGS), + GATE(HCLK_SPDIF3, "hclk_spdif3", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 4, GFLAGS), + GATE(HCLK_I2S6_8CH, "hclk_i2s6_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 3, GFLAGS), + GATE(HCLK_I2S5_8CH, "hclk_i2s5_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(62), 12, GFLAGS), + GATE(HCLK_I2S9_8CH, "hclk_i2s9_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(65), 0, GFLAGS), + GATE(HCLK_I2S7_8CH, "hclk_i2s7_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(60), 0, GFLAGS), + GATE(HCLK_I2S10_8CH, "hclk_i2s10_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(65), 4, GFLAGS), + GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_hdcp1_pre", 0, + RK3588_CLKGATE_CON(60), 5, GFLAGS), + GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1", 0, + RK3588_CLKGATE_CON(60), 6, GFLAGS), + GATE(HCLK_SPDIF5_DP1, "hclk_spdif5_dp1", "hclk_vo0", 0, + RK3588_CLKGATE_CON(57), 7, GFLAGS), + GATE(HCLK_SPDIF2_DP0, "hclk_spdif2_dp0", "hclk_vo0", 0, + RK3588_CLKGATE_CON(57), 2, GFLAGS), + GATE(HCLK_I2S8_8CH, "hclk_i2s8_8ch", "hclk_vo0", 0, + RK3588_CLKGATE_CON(56), 14, GFLAGS), + GATE(HCLK_I2S4_8CH, "hclk_i2s4_8ch", "hclk_vo0", 0, + RK3588_CLKGATE_CON(56), 10, GFLAGS), + GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_hdcp0_pre", 0, + RK3588_CLKGATE_CON(55), 12, GFLAGS), + GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0", 0, + RK3588_CLKGATE_CON(55), 13, GFLAGS), + GATE(HCLK_RKVENC1, "hclk_rkvenc1", "hclk_rkvenc1_pre", 0, + RK3588_CLKGATE_CON(48), 4, GFLAGS), + GATE(ACLK_RKVENC1, "aclk_rkvenc1", "aclk_rkvenc1_pre", 0, + RK3588_CLKGATE_CON(48), 5, GFLAGS), + GATE(ACLK_VPU, "aclk_vpu", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(44), 8, GFLAGS), + GATE(ACLK_IEP2P0, "aclk_iep2p0", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(45), 5, GFLAGS), + GATE(ACLK_JPEG_ENCODER0, "aclk_jpeg_encoder0", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(44), 10, GFLAGS), + GATE(ACLK_JPEG_ENCODER1, "aclk_jpeg_encoder1", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(44), 12, GFLAGS), + GATE(ACLK_JPEG_ENCODER2, "aclk_jpeg_encoder2", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(44), 14, GFLAGS), + GATE(ACLK_JPEG_ENCODER3, "aclk_jpeg_encoder3", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(45), 0, GFLAGS), + GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_decoder_pre", 0, + RK3588_CLKGATE_CON(45), 2, GFLAGS), + GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb", 0, + RK3588_CLKGATE_CON(42), 7, GFLAGS), + GATE(HCLK_HOST0, "hclk_host0", "hclk_usb", 0, + RK3588_CLKGATE_CON(42), 10, GFLAGS), + GATE(HCLK_HOST_ARB0, "hclk_host_arb0", "hclk_usb", 0, + RK3588_CLKGATE_CON(42), 11, GFLAGS), + GATE(HCLK_HOST1, "hclk_host1", "hclk_usb", 0, + RK3588_CLKGATE_CON(42), 12, GFLAGS), + GATE(HCLK_HOST_ARB1, "hclk_host_arb1", "hclk_usb", 0, + RK3588_CLKGATE_CON(42), 13, GFLAGS), + GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb", 0, + RK3588_CLKGATE_CON(42), 4, GFLAGS), + MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "scmi_cclk_sd", RK3588_SDMMC_CON0, 1), + MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "scmi_cclk_sd", RK3588_SDMMC_CON1, 1), + GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdio_pre", 0, + RK3588_CLKGATE_CON(75), 2, GFLAGS), + GATE(HCLK_RKVDEC1, "hclk_rkvdec1", "hclk_rkvdec1_pre", 0, + RK3588_CLKGATE_CON(41), 2, GFLAGS), + GATE(ACLK_RKVDEC1, "aclk_rkvdec1", "aclk_rkvdec1_pre", 0, + RK3588_CLKGATE_CON(41), 3, GFLAGS), + GATE(HCLK_RKVDEC0, "hclk_rkvdec0", "hclk_rkvdec0_pre", 0, + RK3588_CLKGATE_CON(40), 3, GFLAGS), + GATE(ACLK_RKVDEC0, "aclk_rkvdec0", "aclk_rkvdec0_pre", 0, + RK3588_CLKGATE_CON(40), 4, GFLAGS), + GATE(CLK_PCIE4L_PIPE, "clk_pcie4l_pipe", "clk_pipe30phy_pipe0_i", 0, + RK3588_CLKGATE_CON(39), 0, GFLAGS), + GATE(CLK_PCIE2L_PIPE, "clk_pcie2l_pipe", "clk_pipe30phy_pipe2_i", 0, + RK3588_CLKGATE_CON(39), 1, GFLAGS), + GATE(CLK_PIPEPHY0_PIPE_G, "clk_pipephy0_pipe_g", "clk_pipephy0_pipe_i", 0, + RK3588_CLKGATE_CON(38), 3, GFLAGS), + GATE(CLK_PIPEPHY1_PIPE_G, "clk_pipephy1_pipe_g", "clk_pipephy1_pipe_i", 0, + RK3588_CLKGATE_CON(38), 4, GFLAGS), + GATE(CLK_PIPEPHY2_PIPE_G, "clk_pipephy2_pipe_g", "clk_pipephy2_pipe_i", 0, + RK3588_CLKGATE_CON(38), 5, GFLAGS), + GATE(CLK_PIPEPHY0_PIPE_ASIC_G, "clk_pipephy0_pipe_asic_g", "clk_pipephy0_pipe_i", 0, + RK3588_CLKGATE_CON(38), 6, GFLAGS), + GATE(CLK_PIPEPHY1_PIPE_ASIC_G, "clk_pipephy1_pipe_asic_g", "clk_pipephy1_pipe_i", 0, + RK3588_CLKGATE_CON(38), 7, GFLAGS), + GATE(CLK_PIPEPHY2_PIPE_ASIC_G, "clk_pipephy2_pipe_asic_g", "clk_pipephy2_pipe_i", 0, + RK3588_CLKGATE_CON(38), 8, GFLAGS), + GATE(CLK_PIPEPHY2_PIPE_U3_G, "clk_pipephy2_pipe_u3_g", "clk_pipephy2_pipe_i", 0, + RK3588_CLKGATE_CON(38), 9, GFLAGS), + GATE(CLK_PCIE1L2_PIPE, "clk_pcie1l2_pipe", "clk_pipephy0_pipe_g", 0, + RK3588_CLKGATE_CON(38), 13, GFLAGS), + GATE(CLK_PCIE1L0_PIPE, "clk_pcie1l0_pipe", "clk_pipephy1_pipe_g", 0, + RK3588_CLKGATE_CON(38), 14, GFLAGS), + GATE(CLK_PCIE1L1_PIPE, "clk_pcie1l1_pipe", "clk_pipephy2_pipe_g", 0, + RK3588_CLKGATE_CON(38), 15, GFLAGS), + GATE(HCLK_SFC, "hclk_sfc", "hclk_nvm", 0, + RK3588_CLKGATE_CON(31), 10, GFLAGS), + GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_nvm", 0, + RK3588_CLKGATE_CON(31), 11, GFLAGS), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm", 0, + RK3588_CLKGATE_CON(31), 4, GFLAGS), + GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_pre", 0, + RK3588_CLKGATE_CON(26), 5, GFLAGS), + GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_pre", 0, + RK3588_CLKGATE_CON(26), 7, GFLAGS), + GATE(PCLK_AV1, "pclk_av1", "pclk_av1_pre", 0, + RK3588_CLKGATE_CON(68), 5, GFLAGS), + GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0, + RK3588_CLKGATE_CON(68), 2, GFLAGS), + + GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), + GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), + GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", 0, RK3588_CLKGATE_CON(31), 2, GFLAGS), + GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), + GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), + GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), + GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 5, GFLAGS), + GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", "aclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 3, GFLAGS), + GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", "hclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 2, GFLAGS), + GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 5, GFLAGS), + GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 6, GFLAGS), + GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), + GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), + GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), + GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS), + GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), + GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS), + GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), + GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), + GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), +}; + +static void __init rk3588_clk_init(struct device_node *np) +{ + struct rockchip_clk_provider *ctx; + void __iomem *reg_base; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru region\n", __func__); + return; + } + + ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip clk init failed\n", __func__); + iounmap(reg_base); + return; + } + + rockchip_clk_register_plls(ctx, rk3588_pll_clks, + ARRAY_SIZE(rk3588_pll_clks), + RK3588_GRF_SOC_STATUS0); + + rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l", + mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), + &rk3588_cpulclk_data, rk3588_cpulclk_rates, + ARRAY_SIZE(rk3588_cpulclk_rates)); + rockchip_clk_register_armclk(ctx, ARMCLK_B01, "armclk_b01", + mux_armclkb01_p, ARRAY_SIZE(mux_armclkb01_p), + &rk3588_cpub0clk_data, rk3588_cpub0clk_rates, + ARRAY_SIZE(rk3588_cpub0clk_rates)); + rockchip_clk_register_armclk(ctx, ARMCLK_B23, "armclk_b23", + mux_armclkb23_p, ARRAY_SIZE(mux_armclkb23_p), + &rk3588_cpub1clk_data, rk3588_cpub1clk_rates, + ARRAY_SIZE(rk3588_cpub1clk_rates)); + + rockchip_clk_register_branches(ctx, rk3588_clk_branches, + ARRAY_SIZE(rk3588_clk_branches)); + + rk3588_rst_init(np, reg_base); + + rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL); + + rockchip_clk_of_add_provider(np, ctx); +} + +CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init); + +struct clk_rk3588_inits { + void (*inits)(struct device_node *np); +}; + +static const struct clk_rk3588_inits clk_3588_cru_init = { + .inits = rk3588_clk_init, +}; + +static const struct of_device_id clk_rk3588_match_table[] = { + { + .compatible = "rockchip,rk3588-cru", + .data = &clk_3588_cru_init, + }, + { } +}; + +static int __init clk_rk3588_probe(struct platform_device *pdev) +{ + const struct clk_rk3588_inits *init_data; + struct device *dev = &pdev->dev; + + init_data = device_get_match_data(dev); + if (!init_data) + return -EINVAL; + + if (init_data->inits) + init_data->inits(dev->of_node); + + return 0; +} + +static struct platform_driver clk_rk3588_driver = { + .driver = { + .name = "clk-rk3588", + .of_match_table = clk_rk3588_match_table, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver_probe(clk_rk3588_driver, clk_rk3588_probe); diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 7ee231d9585d..758ebaf2236b 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -235,6 +235,51 @@ struct clk; #define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180) #define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200) +#define RK3588_PHP_CRU_BASE 0x8000 +#define RK3588_PMU_CRU_BASE 0x30000 +#define RK3588_BIGCORE0_CRU_BASE 0x50000 +#define RK3588_BIGCORE1_CRU_BASE 0x52000 +#define RK3588_DSU_CRU_BASE 0x58000 + +#define RK3588_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3588_MODE_CON0 0x280 +#define RK3588_B0_PLL_MODE_CON0 (RK3588_BIGCORE0_CRU_BASE + 0x280) +#define RK3588_B1_PLL_MODE_CON0 (RK3588_BIGCORE1_CRU_BASE + 0x280) +#define RK3588_LPLL_MODE_CON0 (RK3588_DSU_CRU_BASE + 0x280) +#define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0x300) +#define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800) +#define RK3588_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) +#define RK3588_GLB_CNT_TH 0xc00 +#define RK3588_GLB_SRST_FST 0xc08 +#define RK3588_GLB_SRST_SND 0xc0c +#define RK3588_GLB_RST_CON 0xc10 +#define RK3588_GLB_RST_ST 0xc04 +#define RK3588_SDIO_CON0 0xC24 +#define RK3588_SDIO_CON1 0xC28 +#define RK3588_SDMMC_CON0 0xC30 +#define RK3588_SDMMC_CON1 0xC34 + +#define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800) +#define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00) + +#define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE) +#define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300) +#define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800) +#define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00) + +#define RK3588_B0_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE) +#define RK3588_BIGCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300) +#define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800) +#define RK3588_BIGCORE0_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00) +#define RK3588_B1_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE) +#define RK3588_BIGCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300) +#define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800) +#define RK3588_BIGCORE1_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00) +#define RK3588_LPLL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE) +#define RK3588_DSU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300) +#define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800) +#define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00) + enum rockchip_pll_type { pll_rk3036, pll_rk3066, @@ -394,7 +439,7 @@ struct rockchip_cpuclk_clksel { u32 val; }; -#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 5 +#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 6 #define ROCKCHIP_CPUCLK_MAX_CORES 4 struct rockchip_cpuclk_rate_table { unsigned long prate; @@ -978,4 +1023,6 @@ static inline void rockchip_register_softrst(struct device_node *np, return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags); } +void rk3588_rst_init(struct device_node *np, void __iomem *reg_base); + #endif diff --git a/drivers/clk/rockchip/rst-rk3588.c b/drivers/clk/rockchip/rst-rk3588.c new file mode 100644 index 000000000000..e855bb8d5413 --- /dev/null +++ b/drivers/clk/rockchip/rst-rk3588.c @@ -0,0 +1,857 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Collabora Ltd. + * Author: Sebastian Reichel + */ + +#include +#include +#include +#include "clk.h" + +/* 0xFD7C0000 + 0x0A00 */ +#define RK3588_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) + +/* 0xFD7C8000 + 0x0A00 */ +#define RK3588_PHPTOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit) + +/* 0xFD7D0000 + 0x0A00 */ +#define RK3588_SECURECRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit) + +/* 0xFD7F0000 + 0x0A00 */ +#define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit) + +/* mapping table for reset ID to register offset */ +static const int rk3588_register_offset[] = { + /* SOFTRST_CON01 */ + RK3588_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY0, 1, 6), + RK3588_CRU_RESET_OFFSET(SRST_CSIPHY0, 1, 7), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY1, 1, 8), + RK3588_CRU_RESET_OFFSET(SRST_CSIPHY1, 1, 9), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M500_BIU, 1, 15), + + /* SOFTRST_CON02 */ + RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M400_BIU, 2, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S200_BIU, 2, 1), + RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S400_BIU, 2, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M300_BIU, 2, 3), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_INIT, 2, 8), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_CMN, 2, 9), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LANE, 2, 10), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS, 2, 11), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_INIT, 2, 15), + + /* SOFTRST_CON03 */ + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_CMN, 3, 0), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LANE, 3, 1), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS, 3, 2), + RK3588_CRU_RESET_OFFSET(SRST_DCPHY0, 3, 11), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0, 3, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0_GRF, 3, 15), + + /* SOFTRST_CON04 */ + RK3588_CRU_RESET_OFFSET(SRST_DCPHY1, 4, 0), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1, 4, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1_GRF, 4, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CDPHY, 4, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CSIPHY, 4, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO3_5, 4, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO6, 4, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_EMMCIO, 4, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_TOP, 4, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_RIGHT, 4, 11), + + /* SOFTRST_CON05 */ + RK3588_CRU_RESET_OFFSET(SRST_P_CRU, 5, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2VO1USB, 5, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2CENTER, 5, 8), + RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2VO1USB, 5, 14), + RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2CENTER, 5, 15), + + /* SOFTRST_CON06 */ + RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2VO1USB, 6, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2CENTER, 6, 1), + + /* SOFTRST_CON07 */ + RK3588_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_AUDIO_BIU, 7, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S0_8CH, 7, 4), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_TX, 7, 7), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_RX, 7, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_ACDCDIG, 7, 11), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S2_2CH, 7, 12), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S3_2CH, 7, 13), + + /* SOFTRST_CON08 */ + RK3588_CRU_RESET_OFFSET(SRST_M_I2S2_2CH, 8, 0), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S3_2CH, 8, 3), + RK3588_CRU_RESET_OFFSET(SRST_DAC_ACDCDIG, 8, 4), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF0, 8, 14), + + /* SOFTRST_CON09 */ + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF0, 9, 1), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF1, 9, 2), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF1, 9, 5), + RK3588_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 6), + RK3588_CRU_RESET_OFFSET(SRST_PDM1, 9, 7), + + /* SOFTRST_CON10 */ + RK3588_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 10, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 10, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_GIC, 10, 3), + RK3588_CRU_RESET_OFFSET(SRST_A_GIC_DBG, 10, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_DMAC0, 10, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_DMAC1, 10, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_DMAC2, 10, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C1, 10, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C2, 10, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C3, 10, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C4, 10, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C5, 10, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C6, 10, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C7, 10, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C8, 10, 15), + + /* SOFTRST_CON11 */ + RK3588_CRU_RESET_OFFSET(SRST_I2C1, 11, 0), + RK3588_CRU_RESET_OFFSET(SRST_I2C2, 11, 1), + RK3588_CRU_RESET_OFFSET(SRST_I2C3, 11, 2), + RK3588_CRU_RESET_OFFSET(SRST_I2C4, 11, 3), + RK3588_CRU_RESET_OFFSET(SRST_I2C5, 11, 4), + RK3588_CRU_RESET_OFFSET(SRST_I2C6, 11, 5), + RK3588_CRU_RESET_OFFSET(SRST_I2C7, 11, 6), + RK3588_CRU_RESET_OFFSET(SRST_I2C8, 11, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_CAN0, 11, 8), + RK3588_CRU_RESET_OFFSET(SRST_CAN0, 11, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_CAN1, 11, 10), + RK3588_CRU_RESET_OFFSET(SRST_CAN1, 11, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_CAN2, 11, 12), + RK3588_CRU_RESET_OFFSET(SRST_CAN2, 11, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_SARADC, 11, 14), + + /* SOFTRST_CON12 */ + RK3588_CRU_RESET_OFFSET(SRST_P_TSADC, 12, 0), + RK3588_CRU_RESET_OFFSET(SRST_TSADC, 12, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_UART1, 12, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_UART2, 12, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_UART3, 12, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_UART4, 12, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_UART5, 12, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_UART6, 12, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_UART7, 12, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_UART8, 12, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_UART9, 12, 10), + RK3588_CRU_RESET_OFFSET(SRST_S_UART1, 12, 13), + + /* SOFTRST_CON13 */ + RK3588_CRU_RESET_OFFSET(SRST_S_UART2, 13, 0), + RK3588_CRU_RESET_OFFSET(SRST_S_UART3, 13, 3), + RK3588_CRU_RESET_OFFSET(SRST_S_UART4, 13, 6), + RK3588_CRU_RESET_OFFSET(SRST_S_UART5, 13, 9), + RK3588_CRU_RESET_OFFSET(SRST_S_UART6, 13, 12), + RK3588_CRU_RESET_OFFSET(SRST_S_UART7, 13, 15), + + /* SOFTRST_CON14 */ + RK3588_CRU_RESET_OFFSET(SRST_S_UART8, 14, 2), + RK3588_CRU_RESET_OFFSET(SRST_S_UART9, 14, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_SPI0, 14, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_SPI1, 14, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_SPI2, 14, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_SPI3, 14, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_SPI4, 14, 10), + RK3588_CRU_RESET_OFFSET(SRST_SPI0, 14, 11), + RK3588_CRU_RESET_OFFSET(SRST_SPI1, 14, 12), + RK3588_CRU_RESET_OFFSET(SRST_SPI2, 14, 13), + RK3588_CRU_RESET_OFFSET(SRST_SPI3, 14, 14), + RK3588_CRU_RESET_OFFSET(SRST_SPI4, 14, 15), + + /* SOFTRST_CON15 */ + RK3588_CRU_RESET_OFFSET(SRST_P_WDT0, 15, 0), + RK3588_CRU_RESET_OFFSET(SRST_T_WDT0, 15, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 15, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_PWM1, 15, 3), + RK3588_CRU_RESET_OFFSET(SRST_PWM1, 15, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_PWM2, 15, 6), + RK3588_CRU_RESET_OFFSET(SRST_PWM2, 15, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_PWM3, 15, 9), + RK3588_CRU_RESET_OFFSET(SRST_PWM3, 15, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 15, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 15, 13), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER0, 15, 15), + + /* SOFTRST_CON16 */ + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER1, 16, 0), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER2, 16, 1), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER3, 16, 2), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER4, 16, 3), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER5, 16, 4), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER6, 16, 5), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER7, 16, 6), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER8, 16, 7), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER9, 16, 8), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER10, 16, 9), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER11, 16, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 16, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX1, 16, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX2, 16, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_GPIO1, 16, 14), + RK3588_CRU_RESET_OFFSET(SRST_GPIO1, 16, 15), + + /* SOFTRST_CON17 */ + RK3588_CRU_RESET_OFFSET(SRST_P_GPIO2, 17, 0), + RK3588_CRU_RESET_OFFSET(SRST_GPIO2, 17, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_GPIO3, 17, 2), + RK3588_CRU_RESET_OFFSET(SRST_GPIO3, 17, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_GPIO4, 17, 4), + RK3588_CRU_RESET_OFFSET(SRST_GPIO4, 17, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_DECOM, 17, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_DECOM, 17, 7), + RK3588_CRU_RESET_OFFSET(SRST_D_DECOM, 17, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_TOP, 17, 9), + RK3588_CRU_RESET_OFFSET(SRST_A_GICADB_GIC2CORE_BUS, 17, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_DFT2APB, 17, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_TOP, 17, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CDPHY, 17, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_BOT_RIGHT, 17, 15), + + /* SOFTRST_CON18 */ + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_TOP, 18, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_RIGHT, 18, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CSIPHY, 18, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_VCCIO3_5, 18, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_VCCIO6, 18, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_EMMCIO, 18, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 18, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 18, 9), + RK3588_CRU_RESET_OFFSET(SRST_OTPC_NS, 18, 10), + RK3588_CRU_RESET_OFFSET(SRST_OTPC_ARB, 18, 11), + + /* SOFTRST_CON19 */ + RK3588_CRU_RESET_OFFSET(SRST_P_BUSIOC, 19, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_PMUCM0_INTMUX, 19, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_DDRCM0_INTMUX, 19, 5), + + /* SOFTRST_CON20 */ + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH0, 20, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 20, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH0, 20, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 20, 3), + RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 20, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_GRF_CH01, 20, 5), + RK3588_CRU_RESET_OFFSET(SRST_DFI_CH0, 20, 6), + RK3588_CRU_RESET_OFFSET(SRST_SBR_CH0, 20, 7), + RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 20, 8), + RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH0, 20, 9), + RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 20, 10), + RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH0, 20, 11), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH0, 20, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH1, 20, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 20, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH1, 20, 15), + + /* SOFTRST_CON21 */ + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 21, 0), + RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 21, 1), + RK3588_CRU_RESET_OFFSET(SRST_DFI_CH1, 21, 2), + RK3588_CRU_RESET_OFFSET(SRST_SBR_CH1, 21, 3), + RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 21, 4), + RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH1, 21, 5), + RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 21, 6), + RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH1, 21, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH1, 21, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 21, 13), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH0, 21, 14), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH0, 21, 15), + + /* SOFTRST_CON22 */ + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE0, 22, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_SCRAMBLE0, 22, 1), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH1, 22, 3), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH1, 22, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE1, 22, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_SCRAMBLE1, 22, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 22, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 22, 8), + + /* SOFTRST_CON23 */ + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH2, 23, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH2, 23, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH2, 23, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH2, 23, 3), + RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH2, 23, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_GRF_CH23, 23, 5), + RK3588_CRU_RESET_OFFSET(SRST_DFI_CH2, 23, 6), + RK3588_CRU_RESET_OFFSET(SRST_SBR_CH2, 23, 7), + RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH2, 23, 8), + RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH2, 23, 9), + RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH2, 23, 10), + RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH2, 23, 11), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH2, 23, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH3, 23, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH3, 23, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH3, 23, 15), + + /* SOFTRST_CON24 */ + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH3, 24, 0), + RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH3, 24, 1), + RK3588_CRU_RESET_OFFSET(SRST_DFI_CH3, 24, 2), + RK3588_CRU_RESET_OFFSET(SRST_SBR_CH3, 24, 3), + RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH3, 24, 4), + RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH3, 24, 5), + RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH3, 24, 6), + RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH3, 24, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH3, 24, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_MSCH2, 24, 13), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH2, 24, 14), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH2, 24, 15), + + /* SOFTRST_CON25 */ + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE2, 25, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_SCRAMBLE2, 25, 1), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_MSCH3, 25, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH3, 25, 3), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH3, 25, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE3, 25, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_SCRAMBLE3, 25, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH2, 25, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH3, 25, 8), + + /* SOFTRST_CON26 */ + RK3588_CRU_RESET_OFFSET(SRST_ISP1, 26, 3), + RK3588_CRU_RESET_OFFSET(SRST_ISP1_VICAP, 26, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_ISP1_BIU, 26, 6), + RK3588_CRU_RESET_OFFSET(SRST_H_ISP1_BIU, 26, 8), + + /* SOFTRST_CON27 */ + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1, 27, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 27, 1), + RK3588_CRU_RESET_OFFSET(SRST_H_RKNN1, 27, 2), + RK3588_CRU_RESET_OFFSET(SRST_H_RKNN1_BIU, 27, 3), + + /* SOFTRST_CON28 */ + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2, 28, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2_BIU, 28, 1), + RK3588_CRU_RESET_OFFSET(SRST_H_RKNN2, 28, 2), + RK3588_CRU_RESET_OFFSET(SRST_H_RKNN2_BIU, 28, 3), + + /* SOFTRST_CON29 */ + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN_DSU0, 29, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 29, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 29, 6), + RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER0, 29, 8), + RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER1, 29, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 29, 10), + RK3588_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 29, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_NPU_PVTM, 29, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 29, 13), + RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTM, 29, 14), + + /* SOFTRST_CON30 */ + RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 30, 0), + RK3588_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 30, 2), + RK3588_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 30, 3), + RK3588_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 30, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0, 30, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 30, 7), + RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0, 30, 8), + RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0_BIU, 30, 9), + + /* SOFTRST_CON31 */ + RK3588_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 31, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 31, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_EMMC, 31, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_EMMC, 31, 5), + RK3588_CRU_RESET_OFFSET(SRST_C_EMMC, 31, 6), + RK3588_CRU_RESET_OFFSET(SRST_B_EMMC, 31, 7), + RK3588_CRU_RESET_OFFSET(SRST_T_EMMC, 31, 8), + RK3588_CRU_RESET_OFFSET(SRST_S_SFC, 31, 9), + RK3588_CRU_RESET_OFFSET(SRST_H_SFC, 31, 10), + RK3588_CRU_RESET_OFFSET(SRST_H_SFC_XIP, 31, 11), + + /* SOFTRST_CON32 */ + RK3588_CRU_RESET_OFFSET(SRST_P_GRF, 32, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_DEC_BIU, 32, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 32, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_PCIE_GRIDGE, 32, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 32, 9), + RK3588_CRU_RESET_OFFSET(SRST_A_GMAC0, 32, 10), + RK3588_CRU_RESET_OFFSET(SRST_A_GMAC1, 32, 11), + RK3588_CRU_RESET_OFFSET(SRST_A_PCIE_BIU, 32, 12), + RK3588_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 32, 13), + RK3588_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 32, 14), + RK3588_CRU_RESET_OFFSET(SRST_PCIE2_POWER_UP, 32, 15), + + /* SOFTRST_CON33 */ + RK3588_CRU_RESET_OFFSET(SRST_PCIE3_POWER_UP, 33, 0), + RK3588_CRU_RESET_OFFSET(SRST_PCIE4_POWER_UP, 33, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_PCIE0, 33, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_PCIE1, 33, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_PCIE2, 33, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_PCIE3, 33, 15), + + /* SOFTRST_CON34 */ + RK3588_CRU_RESET_OFFSET(SRST_P_PCIE4, 34, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_PHP_GIC_ITS, 34, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PCIE, 34, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PHP, 34, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_MMU_BIU, 34, 9), + + /* SOFTRST_CON35 */ + RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG2, 35, 7), + + /* SOFTRST_CON37 */ + RK3588_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 4), + RK3588_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 5), + RK3588_CRU_RESET_OFFSET(SRST_PMALIVE2, 37, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_SATA2, 37, 9), + RK3588_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 10), + RK3588_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 11), + RK3588_CRU_RESET_OFFSET(SRST_RXOOB2, 37, 12), + RK3588_CRU_RESET_OFFSET(SRST_ASIC0, 37, 13), + RK3588_CRU_RESET_OFFSET(SRST_ASIC1, 37, 14), + RK3588_CRU_RESET_OFFSET(SRST_ASIC2, 37, 15), + + /* SOFTRST_CON40 */ + RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC_CCU, 40, 2), + RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC0, 40, 3), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC0, 40, 4), + RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC0_BIU, 40, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC0_BIU, 40, 6), + RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CA, 40, 7), + RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_HEVC_CA, 40, 8), + RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CORE, 40, 9), + + /* SOFTRST_CON41 */ + RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC1, 41, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC1, 41, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC1_BIU, 41, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC1_BIU, 41, 5), + RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_CA, 41, 6), + RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_HEVC_CA, 41, 7), + RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_CORE, 41, 8), + + /* SOFTRST_CON42 */ + RK3588_CRU_RESET_OFFSET(SRST_A_USB_BIU, 42, 2), + RK3588_CRU_RESET_OFFSET(SRST_H_USB_BIU, 42, 3), + RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 42, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 42, 7), + RK3588_CRU_RESET_OFFSET(SRST_H_HOST0, 42, 10), + RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB0, 42, 11), + RK3588_CRU_RESET_OFFSET(SRST_H_HOST1, 42, 12), + RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB1, 42, 13), + RK3588_CRU_RESET_OFFSET(SRST_A_USB_GRF, 42, 14), + RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST0, 42, 15), + + /* SOFTRST_CON43 */ + RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST1, 43, 0), + RK3588_CRU_RESET_OFFSET(SRST_HOST_UTMI0, 43, 1), + RK3588_CRU_RESET_OFFSET(SRST_HOST_UTMI1, 43, 2), + + /* SOFTRST_CON44 */ + RK3588_CRU_RESET_OFFSET(SRST_A_VDPU_BIU, 44, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_VDPU_LOW_BIU, 44, 5), + RK3588_CRU_RESET_OFFSET(SRST_H_VDPU_BIU, 44, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER_BIU, 44, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_VPU, 44, 8), + RK3588_CRU_RESET_OFFSET(SRST_H_VPU, 44, 9), + RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER0, 44, 10), + RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER0, 44, 11), + RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER1, 44, 12), + RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER1, 44, 13), + RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER2, 44, 14), + RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER2, 44, 15), + + /* SOFTRST_CON45 */ + RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER3, 45, 0), + RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER3, 45, 1), + RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 45, 2), + RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 45, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_IEP2P0, 45, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_IEP2P0, 45, 5), + RK3588_CRU_RESET_OFFSET(SRST_IEP2P0_CORE, 45, 6), + RK3588_CRU_RESET_OFFSET(SRST_H_RGA2, 45, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_RGA2, 45, 8), + RK3588_CRU_RESET_OFFSET(SRST_RGA2_CORE, 45, 9), + RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_0, 45, 10), + RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_0, 45, 11), + RK3588_CRU_RESET_OFFSET(SRST_RGA3_0_CORE, 45, 12), + + /* SOFTRST_CON47 */ + RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC0_BIU, 47, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC0_BIU, 47, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC0, 47, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC0, 47, 5), + RK3588_CRU_RESET_OFFSET(SRST_RKVENC0_CORE, 47, 6), + + /* SOFTRST_CON48 */ + RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC1_BIU, 48, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC1_BIU, 48, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC1, 48, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC1, 48, 5), + RK3588_CRU_RESET_OFFSET(SRST_RKVENC1_CORE, 48, 6), + + /* SOFTRST_CON49 */ + RK3588_CRU_RESET_OFFSET(SRST_A_VI_BIU, 49, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_VI_BIU, 49, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_VI_BIU, 49, 5), + RK3588_CRU_RESET_OFFSET(SRST_D_VICAP, 49, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_VICAP, 49, 7), + RK3588_CRU_RESET_OFFSET(SRST_H_VICAP, 49, 8), + RK3588_CRU_RESET_OFFSET(SRST_ISP0, 49, 10), + RK3588_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 49, 11), + + /* SOFTRST_CON50 */ + RK3588_CRU_RESET_OFFSET(SRST_FISHEYE0, 50, 0), + RK3588_CRU_RESET_OFFSET(SRST_FISHEYE1, 50, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 50, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 50, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 50, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 50, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 50, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_5, 50, 9), + + /* SOFTRST_CON51 */ + RK3588_CRU_RESET_OFFSET(SRST_CSIHOST0_VICAP, 51, 4), + RK3588_CRU_RESET_OFFSET(SRST_CSIHOST1_VICAP, 51, 5), + RK3588_CRU_RESET_OFFSET(SRST_CSIHOST2_VICAP, 51, 6), + RK3588_CRU_RESET_OFFSET(SRST_CSIHOST3_VICAP, 51, 7), + RK3588_CRU_RESET_OFFSET(SRST_CSIHOST4_VICAP, 51, 8), + RK3588_CRU_RESET_OFFSET(SRST_CSIHOST5_VICAP, 51, 9), + RK3588_CRU_RESET_OFFSET(SRST_CIFIN, 51, 13), + + /* SOFTRST_CON52 */ + RK3588_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 52, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_VOP_LOW_BIU, 52, 5), + RK3588_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 52, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 52, 7), + RK3588_CRU_RESET_OFFSET(SRST_H_VOP, 52, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_VOP, 52, 9), + RK3588_CRU_RESET_OFFSET(SRST_D_VOP0, 52, 13), + RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE0, 52, 14), + RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE1, 52, 15), + + /* SOFTRST_CON53 */ + RK3588_CRU_RESET_OFFSET(SRST_D_VOP1, 53, 0), + RK3588_CRU_RESET_OFFSET(SRST_D_VOP2, 53, 1), + RK3588_CRU_RESET_OFFSET(SRST_D_VOP3, 53, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_VOPGRF, 53, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 53, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_DSIHOST1, 53, 5), + RK3588_CRU_RESET_OFFSET(SRST_DSIHOST0, 53, 6), + RK3588_CRU_RESET_OFFSET(SRST_DSIHOST1, 53, 7), + RK3588_CRU_RESET_OFFSET(SRST_VOP_PMU, 53, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_VOP_CHANNEL_BIU, 53, 9), + + /* SOFTRST_CON55 */ + RK3588_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 55, 5), + RK3588_CRU_RESET_OFFSET(SRST_H_VO0_S_BIU, 55, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 55, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_VO0_S_BIU, 55, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 55, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_VO0GRF, 55, 10), + RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY0, 55, 11), + RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0, 55, 12), + RK3588_CRU_RESET_OFFSET(SRST_H_HDCP0, 55, 13), + RK3588_CRU_RESET_OFFSET(SRST_HDCP0, 55, 15), + + /* SOFTRST_CON56 */ + RK3588_CRU_RESET_OFFSET(SRST_P_TRNG0, 56, 1), + RK3588_CRU_RESET_OFFSET(SRST_DP0, 56, 8), + RK3588_CRU_RESET_OFFSET(SRST_DP1, 56, 9), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S4_8CH, 56, 10), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S4_8CH_TX, 56, 13), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S8_8CH, 56, 14), + + /* SOFTRST_CON57 */ + RK3588_CRU_RESET_OFFSET(SRST_M_I2S8_8CH_TX, 57, 1), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF2_DP0, 57, 2), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF2_DP0, 57, 6), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF5_DP1, 57, 7), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF5_DP1, 57, 11), + + /* SOFTRST_CON59 */ + RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8), + RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9), + RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_VOP1_BIU, 59, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_VO1GRF, 59, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_VO1_S_BIU, 59, 13), + + /* SOFTRST_CON60 */ + RK3588_CRU_RESET_OFFSET(SRST_H_I2S7_8CH, 60, 0), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S7_8CH_RX, 60, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY1, 60, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1, 60, 5), + RK3588_CRU_RESET_OFFSET(SRST_H_HDCP1, 60, 6), + RK3588_CRU_RESET_OFFSET(SRST_HDCP1, 60, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_TRNG1, 60, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX0, 60, 11), + + /* SOFTRST_CON61 */ + RK3588_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 61, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX1, 61, 2), + RK3588_CRU_RESET_OFFSET(SRST_HDMITX1_REF, 61, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX, 61, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_HDMIRX, 61, 10), + RK3588_CRU_RESET_OFFSET(SRST_HDMIRX_REF, 61, 11), + + /* SOFTRST_CON62 */ + RK3588_CRU_RESET_OFFSET(SRST_P_EDP0, 62, 0), + RK3588_CRU_RESET_OFFSET(SRST_EDP0_24M, 62, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_EDP1, 62, 3), + RK3588_CRU_RESET_OFFSET(SRST_EDP1_24M, 62, 4), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S5_8CH_TX, 62, 8), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S5_8CH, 62, 12), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_TX, 62, 15), + + /* SOFTRST_CON63 */ + RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_RX, 63, 2), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S6_8CH, 63, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF3, 63, 4), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF3, 63, 7), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF4, 63, 8), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF4, 63, 11), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX0, 63, 12), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX0, 63, 13), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX1, 63, 14), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX1, 63, 15), + + /* SOFTRST_CON64 */ + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX2, 64, 0), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX2, 64, 1), + RK3588_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 64, 12), + RK3588_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY1, 64, 13), + RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE0, 64, 14), + RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE1, 64, 15), + + /* SOFTRST_CON65 */ + RK3588_CRU_RESET_OFFSET(SRST_H_I2S9_8CH, 65, 0), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S9_8CH_RX, 65, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S10_8CH, 65, 4), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S10_8CH_RX, 65, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_S_HDMIRX, 65, 8), + + /* SOFTRST_CON66 */ + RK3588_CRU_RESET_OFFSET(SRST_GPU, 66, 4), + RK3588_CRU_RESET_OFFSET(SRST_SYS_GPU, 66, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 66, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 66, 9), + RK3588_CRU_RESET_OFFSET(SRST_A_M1_GPU_BIU, 66, 10), + RK3588_CRU_RESET_OFFSET(SRST_A_M2_GPU_BIU, 66, 11), + RK3588_CRU_RESET_OFFSET(SRST_A_M3_GPU_BIU, 66, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 66, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_GPU_PVTM, 66, 15), + + /* SOFTRST_CON67 */ + RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTM, 67, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 67, 2), + RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 67, 3), + RK3588_CRU_RESET_OFFSET(SRST_GPU_JTAG, 67, 4), + + /* SOFTRST_CON68 */ + RK3588_CRU_RESET_OFFSET(SRST_A_AV1_BIU, 68, 1), + RK3588_CRU_RESET_OFFSET(SRST_A_AV1, 68, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_AV1_BIU, 68, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_AV1, 68, 5), + + /* SOFTRST_CON69 */ + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 69, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 69, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 69, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 69, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S200_BIU, 69, 10), + RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S400_BIU, 69, 11), + RK3588_CRU_RESET_OFFSET(SRST_H_AHB2APB, 69, 12), + RK3588_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 69, 13), + RK3588_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 69, 14), + + /* SOFTRST_CON70 */ + RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 70, 0), + RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 70, 1), + RK3588_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 70, 2), + RK3588_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 70, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 70, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_AHB2APB, 70, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_WDT, 70, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_TIMER, 70, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 70, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 70, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 70, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_CHANNEL_BIU, 70, 12), + + /* SOFTRST_CON72 */ + RK3588_CRU_RESET_OFFSET(SRST_P_USBDPGRF0, 72, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_USBDPPHY0, 72, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_USBDPGRF1, 72, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_USBDPPHY1, 72, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_HDPTX0, 72, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_HDPTX1, 72, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_BOT_RIGHT, 72, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_0_GRF0, 72, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_1_GRF0, 72, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_0_GRF0, 72, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_1_GRF0, 72, 11), + RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_ROPLL, 72, 12), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_LCPLL, 72, 13), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_HDPTX0, 72, 14), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_ROPLL, 72, 15), // missing in TRM + + /* SOFTRST_CON73 */ + RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_LCPLL, 73, 0), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_HDPTX1, 73, 1), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_HDMIRXPHY_SET, 73, 2), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0, 73, 3), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LCPLL, 73, 4), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_ROPLL, 73, 5), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS_HS, 73, 6), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1, 73, 7), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LCPLL, 73, 8), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_ROPLL, 73, 9), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS_HS, 73, 10), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_HDMIHDP0, 73, 12), + RK3588_CRU_RESET_OFFSET(SRST_HDMIHDP1, 73, 13), + + /* SOFTRST_CON74 */ + RK3588_CRU_RESET_OFFSET(SRST_A_VO1USB_TOP_BIU, 74, 1), + RK3588_CRU_RESET_OFFSET(SRST_H_VO1USB_TOP_BIU, 74, 3), + + /* SOFTRST_CON75 */ + RK3588_CRU_RESET_OFFSET(SRST_H_SDIO_BIU, 75, 1), + RK3588_CRU_RESET_OFFSET(SRST_H_SDIO, 75, 2), + RK3588_CRU_RESET_OFFSET(SRST_SDIO, 75, 3), + + /* SOFTRST_CON76 */ + RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_BIU, 76, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_BIU, 76, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_1, 76, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_1, 76, 5), + RK3588_CRU_RESET_OFFSET(SRST_RGA3_1_CORE, 76, 6), + + /* SOFTRST_CON77 */ + RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY0, 77, 6), + RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY1, 77, 7), + RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY2, 77, 8), + + /* PHPTOPCRU_SOFTRST_CON00 */ + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PHPTOP_CRU, 0, 1), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF0, 0, 2), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF1, 0, 3), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF2, 0, 4), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY0, 0, 5), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY1, 0, 6), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY2, 0, 7), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE3_PHY, 0, 8), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 9), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_PCIE30_PHY, 0, 10), + + /* PMU1CRU_SOFTRST_CON00 */ + RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 10), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 11), + RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 0, 12), + RK3588_PMU1CRU_RESET_OFFSET(SRST_F_PMU_CM0_CORE, 0, 13), + RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1_CM0_JTAG, 0, 14), + + /* PMU1CRU_SOFTRST_CON01 */ + RK3588_PMU1CRU_RESET_OFFSET(SRST_DDR_FAIL_SAFE, 1, 1), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 1, 2), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 1, 4), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 1, 5), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 1, 6), + RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 1, 7), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1TIMER, 1, 8), + RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER0, 1, 10), + RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER1, 1, 11), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 1, 12), + RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 1, 13), + + /* PMU1CRU_SOFTRST_CON02 */ + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 2, 1), + RK3588_PMU1CRU_RESET_OFFSET(SRST_I2C0, 2, 2), + RK3588_PMU1CRU_RESET_OFFSET(SRST_S_UART0, 2, 5), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_UART0, 2, 6), + RK3588_PMU1CRU_RESET_OFFSET(SRST_H_I2S1_8CH, 2, 7), + RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_TX, 2, 10), + RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_RX, 2, 13), + RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 2, 14), + RK3588_PMU1CRU_RESET_OFFSET(SRST_PDM0, 2, 15), + + /* PMU1CRU_SOFTRST_CON03 */ + RK3588_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 3, 0), + RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_INIT, 3, 11), + RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_CMN, 3, 12), + RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_LANE, 3, 13), + RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_INIT, 3, 15), + + /* PMU1CRU_SOFTRST_CON04 */ + RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_CMN, 4, 0), + RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_LANE, 4, 1), + RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY0, 4, 3), + RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY0, 4, 4), + RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY1, 4, 5), + RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY1, 4, 6), + RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_0, 4, 7), + RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_1, 4, 8), + RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_0, 4, 9), + RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_1, 4, 10), + + /* PMU1CRU_SOFTRST_CON05 */ + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 5, 3), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 5, 4), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 5, 5), + RK3588_PMU1CRU_RESET_OFFSET(SRST_GPIO0, 5, 6), + + /* SECURECRU_SOFTRST_CON00 */ + RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_NS_BIU, 0, 10), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_NS_BIU, 0, 11), + RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_S_BIU, 0, 12), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_S_BIU, 0, 13), + RK3588_SECURECRU_RESET_OFFSET(SRST_P_SECURE_S_BIU, 0, 14), + RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_CORE, 0, 15), + + /* SECURECRU_SOFTRST_CON01 */ + RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_PKA, 1, 0), + RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_RNG, 1, 1), + RK3588_SECURECRU_RESET_OFFSET(SRST_A_CRYPTO, 1, 2), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_CRYPTO, 1, 3), + RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_CORE, 1, 9), + RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_RNG, 1, 10), + RK3588_SECURECRU_RESET_OFFSET(SRST_A_KEYLADDER, 1, 11), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_KEYLADDER, 1, 12), + RK3588_SECURECRU_RESET_OFFSET(SRST_P_OTPC_S, 1, 13), + RK3588_SECURECRU_RESET_OFFSET(SRST_OTPC_S, 1, 14), + RK3588_SECURECRU_RESET_OFFSET(SRST_WDT_S, 1, 15), + + /* SECURECRU_SOFTRST_CON02 */ + RK3588_SECURECRU_RESET_OFFSET(SRST_T_WDT_S, 2, 0), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM, 2, 1), + RK3588_SECURECRU_RESET_OFFSET(SRST_A_DCF, 2, 2), + RK3588_SECURECRU_RESET_OFFSET(SRST_P_DCF, 2, 3), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM_NS, 2, 5), + RK3588_SECURECRU_RESET_OFFSET(SRST_P_KEYLADDER, 2, 14), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_S, 2, 15), + + /* SECURECRU_SOFTRST_CON03 */ + RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_NS, 3, 0), + RK3588_SECURECRU_RESET_OFFSET(SRST_D_SDMMC_BUFFER, 3, 1), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC, 3, 2), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC_BUFFER, 3, 3), + RK3588_SECURECRU_RESET_OFFSET(SRST_SDMMC, 3, 4), + RK3588_SECURECRU_RESET_OFFSET(SRST_P_TRNG_CHK, 3, 5), + RK3588_SECURECRU_RESET_OFFSET(SRST_TRNG_S, 3, 6), +}; + +void rk3588_rst_init(struct device_node *np, void __iomem *reg_base) +{ + rockchip_register_softrst_lut(np, + rk3588_register_offset, + ARRAY_SIZE(rk3588_register_offset), + reg_base + RK3588_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); +} From 62dfdbcc16e767b91ed35d4fc0428c86d4688505 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Mon, 24 Oct 2022 13:26:39 +0800 Subject: [PATCH 11/36] clk: imx93: correct the flexspi1 clock setting Correct IMX93_CLK_FLEXSPI1_GATE CCGR setting. Otherwise the flexspi always can't be assigned to a parent clock when dump the clock tree. Fixes: 24defbe194b6 ("clk: imx: add i.MX93 clk") Reviewed-by: Peng Fan Signed-off-by: Haibo Chen Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/1666589199-1199-1-git-send-email-haibo.chen@nxp.com --- drivers/clk/imx/clk-imx93.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index 99cff1fd108b..40ecee3b5e78 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -170,7 +170,7 @@ static const struct imx93_clk_ccgr { { IMX93_CLK_MU2_B_GATE, "mu2_b", "bus_wakeup_root", 0x8500, 0, &share_count_mub }, { IMX93_CLK_EDMA1_GATE, "edma1", "m33_root", 0x8540, }, { IMX93_CLK_EDMA2_GATE, "edma2", "wakeup_axi_root", 0x8580, }, - { IMX93_CLK_FLEXSPI1_GATE, "flexspi", "flexspi_root", 0x8640, }, + { IMX93_CLK_FLEXSPI1_GATE, "flexspi1", "flexspi1_root", 0x8640, }, { IMX93_CLK_GPIO1_GATE, "gpio1", "m33_root", 0x8880, }, { IMX93_CLK_GPIO2_GATE, "gpio2", "bus_wakeup_root", 0x88c0, }, { IMX93_CLK_GPIO3_GATE, "gpio3", "bus_wakeup_root", 0x8900, }, From 5c1f7f1090947d494c30042123e0ec846f696336 Mon Sep 17 00:00:00 2001 From: Li Jun Date: Fri, 30 Sep 2022 22:54:21 +0800 Subject: [PATCH 12/36] dt-bindings: clocks: imx8mp: Add ID for usb suspend clock usb suspend clock has a gate shared with usb_root_clk. Fixes: 9c140d9926761 ("clk: imx: Add support for i.MX8MP clock driver") Cc: stable@vger.kernel.org # v5.19+ Acked-by: Krzysztof Kozlowski Tested-by: Alexander Stein Signed-off-by: Li Jun Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/1664549663-20364-1-git-send-email-jun.li@nxp.com --- include/dt-bindings/clock/imx8mp-clock.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 9d5cc2ddde89..1417b7b1b7df 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,8 +324,9 @@ #define IMX8MP_CLK_CLKOUT2_SEL 317 #define IMX8MP_CLK_CLKOUT2_DIV 318 #define IMX8MP_CLK_CLKOUT2 319 +#define IMX8MP_CLK_USB_SUSP 320 -#define IMX8MP_CLK_END 320 +#define IMX8MP_CLK_END 321 #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 From ed1f4ccfe947a3e1018a3bd7325134574c7ff9b3 Mon Sep 17 00:00:00 2001 From: Li Jun Date: Fri, 30 Sep 2022 22:54:22 +0800 Subject: [PATCH 13/36] clk: imx: imx8mp: add shared clk gate for usb suspend clk 32K usb suspend clock gate is shared with usb_root_clk, this shared clock gate was initially defined only for usb suspend clock, usb suspend clk is kept on while system is active or system sleep with usb wakeup enabled, so usb root clock is fine with this situation; with the commit cf7f3f4fa9e5 ("clk: imx8mp: fix usb_root_clk parent"), this clock gate is changed to be for usb root clock, but usb root clock will be off while usb is suspended, so usb suspend clock will be gated too, this cause some usb functionalities will not work, so define this clock to be a shared clock gate to conform with the real HW status. Fixes: 9c140d9926761 ("clk: imx: Add support for i.MX8MP clock driver") Cc: stable@vger.kernel.org # v5.19+ Tested-by: Alexander Stein Signed-off-by: Li Jun Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/1664549663-20364-2-git-send-email-jun.li@nxp.com --- drivers/clk/imx/clk-imx8mp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 652ae58c2735..5d68d975b4eb 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -17,6 +17,7 @@ static u32 share_count_nand; static u32 share_count_media; +static u32 share_count_usb; static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; @@ -673,7 +674,8 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", ccm_base + 0x44a0, 0); hws[IMX8MP_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", ccm_base + 0x44b0, 0); hws[IMX8MP_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", ccm_base + 0x44c0, 0); - hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate4("usb_root_clk", "hsio_axi", ccm_base + 0x44d0, 0); + hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate2_shared2("usb_root_clk", "hsio_axi", ccm_base + 0x44d0, 0, &share_count_usb); + hws[IMX8MP_CLK_USB_SUSP] = imx_clk_hw_gate2_shared2("usb_suspend_clk", "osc_32k", ccm_base + 0x44d0, 0, &share_count_usb); hws[IMX8MP_CLK_USB_PHY_ROOT] = imx_clk_hw_gate4("usb_phy_root_clk", "usb_phy_ref", ccm_base + 0x44f0, 0); hws[IMX8MP_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", ccm_base + 0x4510, 0); hws[IMX8MP_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", ccm_base + 0x4520, 0); From bda7b7f396f94d8df89ecacc88f2826908e8762c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 28 Oct 2022 17:52:06 +0800 Subject: [PATCH 14/36] clk: imx93: unmap anatop base in error handling path The anatop base is not unmapped during error handling path, fix it. Fixes: 24defbe194b6 ("clk: imx: add i.MX93 clk") Reported-by: Dan Carpenter Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20221028095211.2598312-2-peng.fan@oss.nxp.com --- drivers/clk/imx/clk-imx93.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index 40ecee3b5e78..6c39f3431c79 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -258,7 +258,7 @@ static int imx93_clocks_probe(struct platform_device *pdev) struct device_node *np = dev->of_node; const struct imx93_clk_root *root; const struct imx93_clk_ccgr *ccgr; - void __iomem *base = NULL; + void __iomem *base, *anatop_base; int i, ret; clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, @@ -285,20 +285,22 @@ static int imx93_clocks_probe(struct platform_device *pdev) "sys_pll_pfd2", 1, 2); np = of_find_compatible_node(NULL, NULL, "fsl,imx93-anatop"); - base = of_iomap(np, 0); + anatop_base = of_iomap(np, 0); of_node_put(np); - if (WARN_ON(!base)) + if (WARN_ON(!anatop_base)) return -ENOMEM; - clks[IMX93_CLK_AUDIO_PLL] = imx_clk_fracn_gppll("audio_pll", "osc_24m", base + 0x1200, + clks[IMX93_CLK_AUDIO_PLL] = imx_clk_fracn_gppll("audio_pll", "osc_24m", anatop_base + 0x1200, &imx_fracn_gppll); - clks[IMX93_CLK_VIDEO_PLL] = imx_clk_fracn_gppll("video_pll", "osc_24m", base + 0x1400, + clks[IMX93_CLK_VIDEO_PLL] = imx_clk_fracn_gppll("video_pll", "osc_24m", anatop_base + 0x1400, &imx_fracn_gppll); np = dev->of_node; base = devm_platform_ioremap_resource(pdev, 0); - if (WARN_ON(IS_ERR(base))) + if (WARN_ON(IS_ERR(base))) { + iounmap(anatop_base); return PTR_ERR(base); + } for (i = 0; i < ARRAY_SIZE(root_array); i++) { root = &root_array[i]; @@ -327,6 +329,7 @@ static int imx93_clocks_probe(struct platform_device *pdev) unregister_hws: imx_unregister_hw_clocks(clks, IMX93_CLK_END); + iounmap(anatop_base); return ret; } From 4be5d91b9433f1dc76de485e240ca6aaa2d19f65 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 28 Oct 2022 17:52:07 +0800 Subject: [PATCH 15/36] clk: imx93: correct enet clock Per update Reference Mannual, correct the enet clock parent to wakeup_axi_root. Fixes: 24defbe194b6 ("clk: imx: add i.MX93 clk") Reviewed-by: Ye Li Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20221028095211.2598312-3-peng.fan@oss.nxp.com --- drivers/clk/imx/clk-imx93.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index 6c39f3431c79..02d6a9894521 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -240,7 +240,7 @@ static const struct imx93_clk_ccgr { { IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, }, { IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, }, { IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "osc_32k", 0x9dc0, }, - { IMX93_CLK_ENET1_GATE, "enet1", "enet_root", 0x9e00, }, + { IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, }, { IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, }, { IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "osc_24m", 0x9e80, }, { IMX93_CLK_TSTMR1_GATE, "tstmr1", "bus_aon_root", 0x9ec0, }, From 352a308af7c0c48070a8aeefd435a43d40bbbc57 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 28 Oct 2022 17:52:08 +0800 Subject: [PATCH 16/36] dt-bindings: clock: imx93: drop TPM1/3 LPIT1/2 entry Per updated Reference Mannual, the TPM[1,3] LPIT[1,2] root clock entries are reserved, it is because writing the CCM registers does nothing because the TPM[1,3] and LPIT[1,2] IPs source from bus clk, not from the TPM[1,3] LPIT[1,2] entries. And because there is no SW entity is using the entries since adding them, let's drop them. Reviewed-by: Jacky Bai Signed-off-by: Peng Fan Acked-by: Krzysztof Kozlowski Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20221028095211.2598312-4-peng.fan@oss.nxp.com --- include/dt-bindings/clock/imx93-clock.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h index 19bc32788d81..8e02859d8ce2 100644 --- a/include/dt-bindings/clock/imx93-clock.h +++ b/include/dt-bindings/clock/imx93-clock.h @@ -28,13 +28,9 @@ #define IMX93_CLK_M33_SYSTICK 19 #define IMX93_CLK_FLEXIO1 20 #define IMX93_CLK_FLEXIO2 21 -#define IMX93_CLK_LPIT1 22 -#define IMX93_CLK_LPIT2 23 #define IMX93_CLK_LPTMR1 24 #define IMX93_CLK_LPTMR2 25 -#define IMX93_CLK_TPM1 26 #define IMX93_CLK_TPM2 27 -#define IMX93_CLK_TPM3 28 #define IMX93_CLK_TPM4 29 #define IMX93_CLK_TPM5 30 #define IMX93_CLK_TPM6 31 From 4ec9a8b9b00b289e7d3a81533bbe710f79edb58c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 28 Oct 2022 17:52:09 +0800 Subject: [PATCH 17/36] clk: imx93: drop tpm1/3, lpit1/2 clk Per Reference Mannual System Clocks Table, LPIT1 and TPM1 sources from bus_aon_root LPIT2 and TPM3 sources from bus_wakeup_root So update driver to reflect that. Reviewed-by: Jacky Bai Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20221028095211.2598312-5-peng.fan@oss.nxp.com --- drivers/clk/imx/clk-imx93.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index 02d6a9894521..87c414d76370 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -64,13 +64,9 @@ static const struct imx93_clk_root { { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, }, { IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, }, { IMX93_CLK_FLEXIO2, "flexio2_root", 0x0580, LOW_SPEED_IO_SEL, }, - { IMX93_CLK_LPIT1, "lpit1_root", 0x0600, LOW_SPEED_IO_SEL, }, - { IMX93_CLK_LPIT2, "lpit2_root", 0x0680, LOW_SPEED_IO_SEL, }, { IMX93_CLK_LPTMR1, "lptmr1_root", 0x0700, LOW_SPEED_IO_SEL, }, { IMX93_CLK_LPTMR2, "lptmr2_root", 0x0780, LOW_SPEED_IO_SEL, }, - { IMX93_CLK_TPM1, "tpm1_root", 0x0800, TPM_SEL, }, { IMX93_CLK_TPM2, "tpm2_root", 0x0880, TPM_SEL, }, - { IMX93_CLK_TPM3, "tpm3_root", 0x0900, TPM_SEL, }, { IMX93_CLK_TPM4, "tpm4_root", 0x0980, TPM_SEL, }, { IMX93_CLK_TPM5, "tpm5_root", 0x0a00, TPM_SEL, }, { IMX93_CLK_TPM6, "tpm6_root", 0x0a80, TPM_SEL, }, @@ -177,13 +173,13 @@ static const struct imx93_clk_ccgr { { IMX93_CLK_GPIO4_GATE, "gpio4", "bus_wakeup_root", 0x8940, }, { IMX93_CLK_FLEXIO1_GATE, "flexio1", "flexio1_root", 0x8980, }, { IMX93_CLK_FLEXIO2_GATE, "flexio2", "flexio2_root", 0x89c0, }, - { IMX93_CLK_LPIT1_GATE, "lpit1", "lpit1_root", 0x8a00, }, - { IMX93_CLK_LPIT2_GATE, "lpit2", "lpit2_root", 0x8a40, }, + { IMX93_CLK_LPIT1_GATE, "lpit1", "bus_aon_root", 0x8a00, }, + { IMX93_CLK_LPIT2_GATE, "lpit2", "bus_wakeup_root", 0x8a40, }, { IMX93_CLK_LPTMR1_GATE, "lptmr1", "lptmr1_root", 0x8a80, }, { IMX93_CLK_LPTMR2_GATE, "lptmr2", "lptmr2_root", 0x8ac0, }, - { IMX93_CLK_TPM1_GATE, "tpm1", "tpm1_root", 0x8b00, }, + { IMX93_CLK_TPM1_GATE, "tpm1", "bus_aon_root", 0x8b00, }, { IMX93_CLK_TPM2_GATE, "tpm2", "tpm2_root", 0x8b40, }, - { IMX93_CLK_TPM3_GATE, "tpm3", "tpm3_root", 0x8b80, }, + { IMX93_CLK_TPM3_GATE, "tpm3", "bus_wakeup_root", 0x8b80, }, { IMX93_CLK_TPM4_GATE, "tpm4", "tpm4_root", 0x8bc0, }, { IMX93_CLK_TPM5_GATE, "tpm5", "tpm5_root", 0x8c00, }, { IMX93_CLK_TPM6_GATE, "tpm6", "tpm6_root", 0x8c40, }, From c9dcb4c1b6d53bfe74fd863957a1cbb57aea4909 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Fri, 28 Oct 2022 17:52:10 +0800 Subject: [PATCH 18/36] clk: imx: keep hsio bus clock always on During Linux System suspend/resume stress test after System Sleep enabled, system will stuck sometimes. It is because NICMIX is powered down, which HSIOMIX(always on) is not powered down. When NICMIX powering down, HSIOMIX will get a hardware handshake, without HSIO ROOT clk, the handshake will lose. Then after NICMIX power on when system resume, the access to HSIOMIX through NICMIX would be broken. So keep HSIO ROOT always on. Signed-off-by: Jacky Bai Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20221028095211.2598312-6-peng.fan@oss.nxp.com --- drivers/clk/imx/clk-imx93.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index 87c414d76370..20cedff8b0a6 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -109,7 +109,11 @@ static const struct imx93_clk_root { { IMX93_CLK_CCM_CKO2, "ccm_cko2_root", 0x1d00, CKO2_SEL, }, { IMX93_CLK_CCM_CKO3, "ccm_cko3_root", 0x1d80, CKO1_SEL, }, { IMX93_CLK_CCM_CKO4, "ccm_cko4_root", 0x1e00, CKO2_SEL, }, - { IMX93_CLK_HSIO, "hsio_root", 0x1e80, LOW_SPEED_IO_SEL, }, + /* + * Critical because clk is used for handshake between HSIOMIX and NICMIX when + * NICMIX power down/on during system suspend/resume + */ + { IMX93_CLK_HSIO, "hsio_root", 0x1e80, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL}, { IMX93_CLK_HSIO_USB_TEST_60M, "hsio_usb_test_60m_root", 0x1f00, LOW_SPEED_IO_SEL, }, { IMX93_CLK_HSIO_ACSCAN_80M, "hsio_acscan_80m_root", 0x1f80, LOW_SPEED_IO_SEL, }, { IMX93_CLK_HSIO_ACSCAN_480M, "hsio_acscan_480m_root", 0x2000, MISC_SEL, }, From f8aa5f6dc1cb71d472d023f87d05f53b1672983f Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Fri, 28 Oct 2022 17:52:11 +0800 Subject: [PATCH 19/36] clk: imx93: keep sys ctr clock always on Keep sys ctr clock always on to make sure its register can be accessed for cpuidle. Reviewed-by: Peng Fan Signed-off-by: Jacky Bai Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20221028095211.2598312-7-peng.fan@oss.nxp.com --- drivers/clk/imx/clk-imx93.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index 20cedff8b0a6..5bd06ebd6826 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -242,7 +242,8 @@ static const struct imx93_clk_ccgr { { IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "osc_32k", 0x9dc0, }, { IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, }, { IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, }, - { IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "osc_24m", 0x9e80, }, + /* Critical because clk accessed during CPU idle */ + { IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "osc_24m", 0x9e80, CLK_IS_CRITICAL}, { IMX93_CLK_TSTMR1_GATE, "tstmr1", "bus_aon_root", 0x9ec0, }, { IMX93_CLK_TSTMR2_GATE, "tstmr2", "bus_wakeup_root", 0x9f00, }, { IMX93_CLK_TMC_GATE, "tmc", "osc_24m", 0x9f40, }, From 6a11d3a00dc1f152e8cdf97171128c4186695a9d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 31 Oct 2022 21:48:38 +0100 Subject: [PATCH 20/36] clk: imx: pll14xx: Add 320 MHz and 640 MHz entries for PLL146x The PLL146x is used to implement SYS_PLL3 on i.MX8MP and can be used to drive UARTn_ROOT clock. By setting the PLL3 to 320 MHz or 640 MHz, the PLL3 output can be divided down to supply UARTn_ROOT clock with precise 64 MHz, which divided down further by 16x oversampling factor used by the i.MX UART core yields 4 Mbdps baud base for the UART IP. This is useful e.g. for BCM bluetooth chips, which can operate up to 4 Mbdps. Add 320 MHz and 640 MHz entries so the PLL can be configured accordingly. Signed-off-by: Marek Vasut Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20221031204838.195292-1-marex@denx.de --- drivers/clk/imx/clk-pll14xx.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 1d0f79e9c346..828336873a98 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -54,7 +54,9 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = { PLL_1416X_RATE(800000000U, 200, 3, 1), PLL_1416X_RATE(750000000U, 250, 2, 2), PLL_1416X_RATE(700000000U, 350, 3, 2), + PLL_1416X_RATE(640000000U, 320, 3, 2), PLL_1416X_RATE(600000000U, 300, 3, 2), + PLL_1416X_RATE(320000000U, 160, 3, 2), }; static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = { From 36759c4fe217263a4688aabf384302afbe1004fa Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Mon, 7 Nov 2022 16:50:06 +0800 Subject: [PATCH 21/36] dt-bindings: clock: imx8mp: Add ids for the audio shared gate All these IDs are for one single HW gate (CCGR101) that is shared between these root clocks. Signed-off-by: Abel Vesa Signed-off-by: Shengjiu Wang Reviewed-by: Peng Fan Acked-by: Krzysztof Kozlowski Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/1667811007-19222-2-git-send-email-shengjiu.wang@nxp.com --- include/dt-bindings/clock/imx8mp-clock.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 1417b7b1b7df..ede1f65a3147 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -325,8 +325,17 @@ #define IMX8MP_CLK_CLKOUT2_DIV 318 #define IMX8MP_CLK_CLKOUT2 319 #define IMX8MP_CLK_USB_SUSP 320 +#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 +#define IMX8MP_CLK_SAI1_ROOT 322 +#define IMX8MP_CLK_SAI2_ROOT 323 +#define IMX8MP_CLK_SAI3_ROOT 324 +#define IMX8MP_CLK_SAI5_ROOT 325 +#define IMX8MP_CLK_SAI6_ROOT 326 +#define IMX8MP_CLK_SAI7_ROOT 327 +#define IMX8MP_CLK_PDM_ROOT 328 -#define IMX8MP_CLK_END 321 +#define IMX8MP_CLK_END 329 #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 From b1f12a685d459c3fc898b12d0b052acfab2e3018 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Mon, 7 Nov 2022 16:50:07 +0800 Subject: [PATCH 22/36] clk: imx8mp: Add audio shared gate According to the RM, the CCGR101 is shared for the following root clocks: - AUDIO_AHB_CLK_ROOT - AUDIO_AXI_CLK_ROOT - SAI1_CLK_ROOT - SAI2_CLK_ROOT - SAI3_CLK_ROOT - SAI5_CLK_ROOT - SAI6_CLK_ROOT - SAI7_CLK_ROOT - PDM_CLK_ROOT IMX8MP_CLK_AUDIO_ROOT is same as AUDIO_AHB_CLK_ROOT which can avoid break any users. Signed-off-by: Abel Vesa Signed-off-by: Shengjiu Wang Reviewed-by: Peng Fan Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/1667811007-19222-3-git-send-email-shengjiu.wang@nxp.com --- drivers/clk/imx/clk-imx8mp.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 5d68d975b4eb..423a5d02b553 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -18,6 +18,7 @@ static u32 share_count_nand; static u32 share_count_media; static u32 share_count_usb; +static u32 share_count_audio; static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; @@ -701,7 +702,16 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", ccm_base + 0x45f0, 0); hws[IMX8MP_CLK_TSENSOR_ROOT] = imx_clk_hw_gate4("tsensor_root_clk", "ipg_root", ccm_base + 0x4620, 0); hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0); - hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk", "audio_ahb", ccm_base + 0x4650, 0); + + hws[IMX8MP_CLK_AUDIO_AHB_ROOT] = imx_clk_hw_gate2_shared2("audio_ahb_root", "audio_ahb", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_AUDIO_AXI_ROOT] = imx_clk_hw_gate2_shared2("audio_axi_root", "audio_axi", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI1_ROOT] = imx_clk_hw_gate2_shared2("sai1_root", "sai1", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root", "sai2", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root", "sai3", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root", "sai5", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root", "sai6", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root", "sai7", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_PDM_ROOT] = imx_clk_hw_gate2_shared2("pdm_root", "pdm", ccm_base + 0x4650, 0, &share_count_audio); hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core", hws[IMX8MP_CLK_A53_CORE]->clk, From 3095c02f95e537c553e0b30948c2f6c7cbed87ee Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 17 Nov 2022 19:10:11 +0100 Subject: [PATCH 23/36] clk: imx: imxrt1050: fix IMXRT1050_CLK_LCDIF_APB offsets Fix IMXRT1050_CLK_LCDIF_APB offsets. Fixes: 7154b046d8f3 ("clk: imx: Add initial support for i.MXRT1050 clock driver") Cc: Jesse Taube Signed-off-by: Giulio Benetti Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20221117181014.851505-1-giulio.benetti@benettiengineering.com --- drivers/clk/imx/clk-imxrt1050.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index 9539d35588ee..26108e9f7e67 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -140,7 +140,7 @@ static int imxrt1050_clocks_probe(struct platform_device *pdev) hws[IMXRT1050_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", ccm_base + 0x80, 2); hws[IMXRT1050_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", ccm_base + 0x80, 4); hws[IMXRT1050_CLK_LPUART1] = imx_clk_hw_gate2("lpuart1", "lpuart_podf", ccm_base + 0x7c, 24); - hws[IMXRT1050_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif", "lcdif_podf", ccm_base + 0x74, 10); + hws[IMXRT1050_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif", "lcdif_podf", ccm_base + 0x70, 28); hws[IMXRT1050_CLK_DMA] = imx_clk_hw_gate("dma", "ipg", ccm_base + 0x7C, 6); hws[IMXRT1050_CLK_DMA_MUX] = imx_clk_hw_gate("dmamux0", "ipg", ccm_base + 0x7C, 7); imx_check_clk_hws(hws, IMXRT1050_CLK_END); From ec689c152985deb4ee17f5203f7e243221de647c Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 17 Nov 2022 19:10:12 +0100 Subject: [PATCH 24/36] clk: imx: imxrt1050: add IMXRT1050_CLK_LCDIF_PIX clock gate Add IMXRT1050_CLK_LCDIF_PIX clock gate. Cc: Jesse Taube Signed-off-by: Giulio Benetti Acked-by: Jesse Taube Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20221117181014.851505-2-giulio.benetti@benettiengineering.com --- drivers/clk/imx/clk-imxrt1050.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index 26108e9f7e67..39f77c03b892 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -141,6 +141,7 @@ static int imxrt1050_clocks_probe(struct platform_device *pdev) hws[IMXRT1050_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", ccm_base + 0x80, 4); hws[IMXRT1050_CLK_LPUART1] = imx_clk_hw_gate2("lpuart1", "lpuart_podf", ccm_base + 0x7c, 24); hws[IMXRT1050_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif", "lcdif_podf", ccm_base + 0x70, 28); + hws[IMXRT1050_CLK_LCDIF_PIX] = imx_clk_hw_gate2("lcdif_pix", "lcdif", ccm_base + 0x74, 10); hws[IMXRT1050_CLK_DMA] = imx_clk_hw_gate("dma", "ipg", ccm_base + 0x7C, 6); hws[IMXRT1050_CLK_DMA_MUX] = imx_clk_hw_gate("dmamux0", "ipg", ccm_base + 0x7C, 7); imx_check_clk_hws(hws, IMXRT1050_CLK_END); From 9a856bee524b65405ba58e28c26e6bd1278d7930 Mon Sep 17 00:00:00 2001 From: Kory Maincent Date: Tue, 15 Nov 2022 14:58:12 +0100 Subject: [PATCH 25/36] clk: spear: Fix CLCD clock definition on SPEAr600 There is no SPEAr600 device named "clcd". Instead, the description of the CLCD (color liquid crystal display controller) name is "fc200000.clcd", so we should associate the CLCD gateable clock to this device name. Signed-off-by: Kory Maincent Acked-by: Viresh Kumar Link: https://lore.kernel.org/r/20221115135814.214388-2-kory.maincent@bootlin.com Signed-off-by: Stephen Boyd --- drivers/clk/spear/spear6xx_clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c index c192a9141b86..ee0ed89f2954 100644 --- a/drivers/clk/spear/spear6xx_clock.c +++ b/drivers/clk/spear/spear6xx_clock.c @@ -207,7 +207,7 @@ void __init spear6xx_clk_init(void __iomem *misc_base) clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0, PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "clcd"); + clk_register_clkdev(clk, NULL, "fc200000.clcd"); /* gpt clocks */ clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, From 5381dc785312e2ea77febd8274834ee5b59f580e Mon Sep 17 00:00:00 2001 From: Kory Maincent Date: Tue, 15 Nov 2022 14:58:13 +0100 Subject: [PATCH 26/36] clk: spear: Fix SSP clock definition on SPEAr600 There is no SPEAr600 device named "ssp-pl022.x". Instead, the description of the SSP (Synchronous Serial Port) was recently added to the Device Tree, and the device name is "xxx.spi", so we should associate the SSP gateable clock to these device names. Signed-off-by: Kory Maincent Acked-by: Viresh Kumar Link: https://lore.kernel.org/r/20221115135814.214388-3-kory.maincent@bootlin.com Signed-off-by: Stephen Boyd --- drivers/clk/spear/spear6xx_clock.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c index ee0ed89f2954..adfa118520c3 100644 --- a/drivers/clk/spear/spear6xx_clock.c +++ b/drivers/clk/spear/spear6xx_clock.c @@ -326,13 +326,13 @@ void __init spear6xx_clk_init(void __iomem *misc_base) clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB, SSP0_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "ssp-pl022.0"); + clk_register_clkdev(clk, NULL, "d0100000.spi"); clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB, SSP1_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "ssp-pl022.1"); + clk_register_clkdev(clk, NULL, "d0180000.spi"); clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB, SSP2_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "ssp-pl022.2"); + clk_register_clkdev(clk, NULL, "d8180000.spi"); } From 7fffdb777371cbc20929cc648509765e1923937d Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 22 Nov 2022 15:07:30 +0200 Subject: [PATCH 27/36] clk: fractional-divider: Split out clk_fd_get_div() helper Split out clk_fd_get_div() helper for the future use elsewhere. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20221122130732.48537-1-andriy.shevchenko@linux.intel.com Signed-off-by: Stephen Boyd --- drivers/clk/clk-fractional-divider.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index 8efa5142ff8c..5c6f1d0f8fb4 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -40,6 +40,7 @@ #include #include +#include #include #include #include @@ -63,14 +64,12 @@ static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val) writel(val, fd->reg); } -static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) +static void clk_fd_get_div(struct clk_hw *hw, struct u32_fract *fract) { struct clk_fractional_divider *fd = to_clk_fd(hw); unsigned long flags = 0; unsigned long m, n; u32 val; - u64 ret; if (fd->lock) spin_lock_irqsave(fd->lock, flags); @@ -92,11 +91,22 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, n++; } - if (!n || !m) + fract->numerator = m; + fract->denominator = n; +} + +static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct u32_fract fract; + u64 ret; + + clk_fd_get_div(hw, &fract); + + if (!fract.numerator || !fract.denominator) return parent_rate; - ret = (u64)parent_rate * m; - do_div(ret, n); + ret = (u64)parent_rate * fract.numerator; + do_div(ret, fract.denominator); return ret; } From ac49a19280dfc229c4f2cd262787d27b91b944ea Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 22 Nov 2022 15:07:31 +0200 Subject: [PATCH 28/36] clk: fractional-divider: Show numerator and denominator in debugfs It's very useful to see what are the values of the fractional divider. For that, add respective debugfs files. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20221122130732.48537-2-andriy.shevchenko@linux.intel.com Signed-off-by: Stephen Boyd --- drivers/clk/clk-fractional-divider.c | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index 5c6f1d0f8fb4..b6b52b79d671 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -39,6 +39,7 @@ */ #include +#include #include #include #include @@ -193,10 +194,45 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +#ifdef CONFIG_DEBUG_FS +static int clk_fd_numerator_get(void *hw, u64 *val) +{ + struct u32_fract fract; + + clk_fd_get_div(hw, &fract); + + *val = fract.numerator; + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(clk_fd_numerator_fops, clk_fd_numerator_get, NULL, "%llu\n"); + +static int clk_fd_denominator_get(void *hw, u64 *val) +{ + struct u32_fract fract; + + clk_fd_get_div(hw, &fract); + + *val = fract.denominator; + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(clk_fd_denominator_fops, clk_fd_denominator_get, NULL, "%llu\n"); + +static void clk_fd_debug_init(struct clk_hw *hw, struct dentry *dentry) +{ + debugfs_create_file("numerator", 0444, dentry, hw, &clk_fd_numerator_fops); + debugfs_create_file("denominator", 0444, dentry, hw, &clk_fd_denominator_fops); +} +#endif + const struct clk_ops clk_fractional_divider_ops = { .recalc_rate = clk_fd_recalc_rate, .round_rate = clk_fd_round_rate, .set_rate = clk_fd_set_rate, +#ifdef CONFIG_DEBUG_FS + .debug_init = clk_fd_debug_init, +#endif }; EXPORT_SYMBOL_GPL(clk_fractional_divider_ops); From 76c340e93f5aa5d66cf62dd0a78777e499f36952 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 22 Nov 2022 15:07:32 +0200 Subject: [PATCH 29/36] clk: fractional-divider: Regroup inclusions For the better maintenance regroup inclusions as follows: - split CCF related headers in its own group - order groups from generic to particular - sort each group alphabetically Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20221122130732.48537-3-andriy.shevchenko@linux.intel.com Signed-off-by: Stephen Boyd --- drivers/clk/clk-fractional-divider.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index b6b52b79d671..6affe3565025 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -38,14 +38,15 @@ * saturated values. */ -#include #include +#include #include #include #include -#include -#include #include +#include + +#include #include "clk-fractional-divider.h" From 739a6a6bbdb793bd57938cb24aa5a6df89983546 Mon Sep 17 00:00:00 2001 From: Xiu Jianfeng Date: Wed, 23 Nov 2022 17:12:01 +0800 Subject: [PATCH 30/36] clk: rockchip: Fix memory leak in rockchip_clk_register_pll() If clk_register() fails, @pll->rate_table may have allocated memory by kmemdup(), so it needs to be freed, otherwise will cause memory leak issue, this patch fixes it. Fixes: 90c590254051 ("clk: rockchip: add clock type for pll clocks and pll used on rk3066") Signed-off-by: Xiu Jianfeng Link: https://lore.kernel.org/r/20221123091201.199819-1-xiujianfeng@huawei.com Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-pll.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 4b9840994295..2d42eb628926 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -1197,6 +1197,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, return mux_clk; err_pll: + kfree(pll->rate_table); clk_unregister(mux_clk); mux_clk = pll_clk; err_mux: From a429c60baefd95ab43a2ce7f25d5b2d7a2e431df Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Thu, 17 Nov 2022 12:36:33 +0100 Subject: [PATCH 31/36] clk: imx8mn: rename vpu_pll to m7_alt_pll The IMX8MN platform does not have any video processing unit (VPU), and indeed in the reference manual (document IMX8MNRM Rev 2, 07/2022) there is no occurrence of its pll. From an analysis of the code and the RM itself, I think vpu pll is used instead of m7 alternate pll, probably for copy and paste of code taken from modules of similar architectures. As an example for all, if we consider the second row of the "Clock Root" table of chapter 5 (Clocks and Power Management) of the RM: Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX]) ... ... ... ARM_M7_CLK_ROOT 0x8080 000 - 24M_REF_CLK 001 - SYSTEM_PLL2_DIV5 010 - SYSTEM_PLL2_DIV4 011 - M7_ALT_PLL_CLK 100 - SYSTEM_PLL1_CLK 101 - AUDIO_PLL1_CLK 110 - VIDEO_PLL_CLK 111 - SYSTEM_PLL3_CLK ... ... ... but in the source code, the imx8mn_m7_sels clocks list contains vpu_pll for the source select bits 011b. So, let's rename "vpu_pll" to "m7_alt_pll" to be consistent with the RM. The IMX8MN_VPU_* constants have not been removed to ensure backward compatibility of the patch. No functional changes intended. Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Dario Binacchi Acked-by: Marco Felsch Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20221117113637.1978703-2-dario.binacchi@amarulasolutions.com --- drivers/clk/imx/clk-imx8mn.c | 16 ++++++++-------- include/dt-bindings/clock/imx8mn-clock.h | 12 ++++++++---- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index d37c45b676ab..72f9563a0ff6 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -30,7 +30,7 @@ static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; -static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; +static const char * const m7_alt_pll_bypass_sels[] = {"m7_alt_pll", "m7_alt_pll_ref_sel", }; static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; @@ -40,7 +40,7 @@ static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pl static const char * const imx8mn_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", }; -static const char * const imx8mn_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "vpu_pll_out", +static const char * const imx8mn_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "m7_alt_pll_out", "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", @@ -252,10 +252,10 @@ static const char * const imx8mn_gpt6_sels[] = {"osc_24m", "sys_pll2_100m", "sys "audio_pll1_out", "clk_ext1", }; static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", - "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", + "m7_alt_pll_out", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; -static const char * const imx8mn_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_out", +static const char * const imx8mn_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "m7_alt_pll_out", "sys_pll3_out", "sys_pll2_200m", "sys_pll1_266m", "sys_pll2_500m", "sys_pll1_100m", }; @@ -352,7 +352,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); @@ -361,7 +361,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws[IMX8MN_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll); hws[IMX8MN_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll); hws[IMX8MN_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll); - hws[IMX8MN_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll); + hws[IMX8MN_M7_ALT_PLL] = imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel", base + 0x74, &imx_1416x_pll); hws[IMX8MN_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll); hws[IMX8MN_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000); hws[IMX8MN_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000); @@ -373,7 +373,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws[IMX8MN_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MN_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT); + hws[IMX8MN_M7_ALT_PLL_BYPASS] = imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1, m7_alt_pll_bypass_sels, ARRAY_SIZE(m7_alt_pll_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MN_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT); @@ -383,7 +383,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13); hws[IMX8MN_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13); hws[IMX8MN_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11); - hws[IMX8MN_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11); + hws[IMX8MN_M7_ALT_PLL_OUT] = imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass", base + 0x74, 11); hws[IMX8MN_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11); hws[IMX8MN_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11); diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h index 07b8a282c268..694e3c050d04 100644 --- a/include/dt-bindings/clock/imx8mn-clock.h +++ b/include/dt-bindings/clock/imx8mn-clock.h @@ -19,7 +19,8 @@ #define IMX8MN_VIDEO_PLL1_REF_SEL 10 #define IMX8MN_DRAM_PLL_REF_SEL 11 #define IMX8MN_GPU_PLL_REF_SEL 12 -#define IMX8MN_VPU_PLL_REF_SEL 13 +#define IMX8MN_M7_ALT_PLL_REF_SEL 13 +#define IMX8MN_VPU_PLL_REF_SEL IMX8MN_M7_ALT_PLL_REF_SEL #define IMX8MN_ARM_PLL_REF_SEL 14 #define IMX8MN_SYS_PLL1_REF_SEL 15 #define IMX8MN_SYS_PLL2_REF_SEL 16 @@ -29,7 +30,8 @@ #define IMX8MN_VIDEO_PLL1 20 #define IMX8MN_DRAM_PLL 21 #define IMX8MN_GPU_PLL 22 -#define IMX8MN_VPU_PLL 23 +#define IMX8MN_M7_ALT_PLL 23 +#define IMX8MN_VPU_PLL IMX8MN_M7_ALT_PLL #define IMX8MN_ARM_PLL 24 #define IMX8MN_SYS_PLL1 25 #define IMX8MN_SYS_PLL2 26 @@ -39,7 +41,8 @@ #define IMX8MN_VIDEO_PLL1_BYPASS 30 #define IMX8MN_DRAM_PLL_BYPASS 31 #define IMX8MN_GPU_PLL_BYPASS 32 -#define IMX8MN_VPU_PLL_BYPASS 33 +#define IMX8MN_M7_ALT_PLL_BYPASS 33 +#define IMX8MN_VPU_PLL_BYPASS IMX8MN_M7_ALT_PLL_BYPASS #define IMX8MN_ARM_PLL_BYPASS 34 #define IMX8MN_SYS_PLL1_BYPASS 35 #define IMX8MN_SYS_PLL2_BYPASS 36 @@ -49,7 +52,8 @@ #define IMX8MN_VIDEO_PLL1_OUT 40 #define IMX8MN_DRAM_PLL_OUT 41 #define IMX8MN_GPU_PLL_OUT 42 -#define IMX8MN_VPU_PLL_OUT 43 +#define IMX8MN_M7_ALT_PLL_OUT 43 +#define IMX8MN_VPU_PLL_OUT IMX8MN_M7_ALT_PLL_OUT #define IMX8MN_ARM_PLL_OUT 44 #define IMX8MN_SYS_PLL1_OUT 45 #define IMX8MN_SYS_PLL2_OUT 46 From e7fa365ff66f16772dc06b480cd78f858d10856b Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Thu, 17 Nov 2022 12:36:34 +0100 Subject: [PATCH 32/36] clk: imx: replace osc_hdmi with dummy There is no occurrence of the hdmi oscillator in the reference manual (document IMX8MNRM Rev 2, 07/2022). Further, if we consider the indexes 76-81 and 134 of the "Clock Root" table of chapter 5 of the RM, there is no entry for the source select bits 101b, which is the setting referenced by "osc_hdmi". Fix by renaming "osc_hdmi" with "dummy", a clock which has already been used for missing source select bits. Tested on the BSH SystemMaster (SMM) S2 board. Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Dario Binacchi Acked-by: Marco Felsch Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20221117113637.1978703-3-dario.binacchi@amarulasolutions.com --- drivers/clk/imx/clk-imx8mn.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 72f9563a0ff6..0fae97e61e2c 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -108,27 +108,27 @@ static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll1_out "sys_pll3_out", "clk_ext4", }; static const char * const imx8mn_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll1_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; static const char * const imx8mn_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll1_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; static const char * const imx8mn_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll1_out", "sys_pll1_133m", "dummy", "clk_ext2", "clk_ext3", }; static const char * const imx8mn_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll1_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; static const char * const imx8mn_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll1_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; static const char * const imx8mn_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll1_out", "sys_pll1_133m", "dummy", "clk_ext2", "clk_ext3", }; static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", From bedcf9d1dcf88ed38731f0ac9620e5a421e1e9d6 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Thu, 17 Nov 2022 12:36:35 +0100 Subject: [PATCH 33/36] clk: imx: rename video_pll1 to video_pll Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's rename "video_pll1" to "video_pll" to be consistent with the RM and avoid misunderstandings. The IMX8MN_VIDEO_PLL1* constants have not been removed to ensure backward compatibility of the patch. No functional changes intended. Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Dario Binacchi Acked-by: Marco Felsch Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20221117113637.1978703-4-dario.binacchi@amarulasolutions.com --- drivers/clk/imx/clk-imx8mn.c | 96 ++++++++++++------------ include/dt-bindings/clock/imx8mn-clock.h | 12 ++- 2 files changed, 56 insertions(+), 52 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 0fae97e61e2c..b80af5d1ef46 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -27,7 +27,7 @@ static u32 share_count_nand; static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; -static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; +static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", }; static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; static const char * const m7_alt_pll_bypass_sels[] = {"m7_alt_pll", "m7_alt_pll_ref_sel", }; @@ -41,23 +41,23 @@ static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pl static const char * const imx8mn_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", }; static const char * const imx8mn_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "m7_alt_pll_out", - "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; + "sys_pll1_800m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", }; static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mn_gpu_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mn_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "sys_pll1_100m",}; + "video_pll_out", "sys_pll1_100m",}; static const char * const imx8mn_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", - "video_pll1_out", "sys_pll3_out", }; + "video_pll_out", "sys_pll3_out", }; static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", @@ -77,23 +77,23 @@ static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", " static const char * const imx8mn_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mn_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mn_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mn_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", - "audio_pll1_out", "video_pll1_out", }; + "audio_pll1_out", "video_pll_out", }; static const char * const imx8mn_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out", - "audio_pll1_out", "video_pll1_out", }; + "audio_pll1_out", "video_pll_out", }; static const char * const imx8mn_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out", @@ -103,49 +103,49 @@ static const char * const imx8mn_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", +static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll_out", "audio_pll2_out", "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; static const char * const imx8mn_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "dummy", + "video_pll_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; static const char * const imx8mn_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "dummy", + "video_pll_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; static const char * const imx8mn_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "dummy", + "video_pll_out", "sys_pll1_133m", "dummy", "clk_ext2", "clk_ext3", }; static const char * const imx8mn_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "dummy", + "video_pll_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; static const char * const imx8mn_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "dummy", + "video_pll_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; static const char * const imx8mn_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "dummy", + "video_pll_out", "sys_pll1_133m", "dummy", "clk_ext2", "clk_ext3", }; static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", - "video_pll1_out", "clk_ext4", }; + "video_pll_out", "clk_ext4", }; static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", - "clk_ext4", "video_pll1_out", }; + "clk_ext4", "video_pll_out", }; static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", - "sys_pll2_200m", "sys_pll2_500m", "video_pll1_out", + "sys_pll2_200m", "sys_pll2_500m", "video_pll_out", "audio_pll2_out", }; static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", - "sys_pll2_250m", "video_pll1_out", }; + "sys_pll2_250m", "video_pll_out", }; static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", @@ -160,19 +160,19 @@ static const char * const imx8mn_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "s "audio_pll2_out", "sys_pll1_100m", }; static const char * const imx8mn_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char * const imx8mn_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char * const imx8mn_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char * const imx8mn_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", @@ -213,42 +213,42 @@ static const char * const imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "s static const char * const imx8mn_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; static const char * const imx8mn_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1", }; static const char * const imx8mn_gpt2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1", }; static const char * const imx8mn_gpt3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1", }; static const char * const imx8mn_gpt4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1", }; static const char * const imx8mn_gpt5_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1", }; static const char * const imx8mn_gpt6_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1", }; static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", @@ -261,15 +261,15 @@ static const char * const imx8mn_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "m7_ static const char * const imx8mn_dsi_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; static const char * const imx8mn_dsi_phy_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; static const char * const imx8mn_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", @@ -277,15 +277,15 @@ static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "s static const char * const imx8mn_camera_pixel_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; static const char * const imx8mn_csi1_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; static const char * const imx8mn_csi2_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; static const char * const imx8mn_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", @@ -306,9 +306,9 @@ static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "du "dummy", "sys_pll1_80m", }; static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "osc_32k", }; + "video_pll_out", "osc_32k", }; -static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out", +static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out", "dummy", "dummy", "gpu_pll_out", "dummy", "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; @@ -349,7 +349,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); @@ -358,7 +358,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws[IMX8MN_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll); hws[IMX8MN_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MN_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll); + hws[IMX8MN_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", base + 0x28, &imx_1443x_pll); hws[IMX8MN_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll); hws[IMX8MN_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll); hws[IMX8MN_M7_ALT_PLL] = imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel", base + 0x74, &imx_1416x_pll); @@ -370,7 +370,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) /* PLL bypass out */ hws[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT); + hws[IMX8MN_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MN_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MN_M7_ALT_PLL_BYPASS] = imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1, m7_alt_pll_bypass_sels, ARRAY_SIZE(m7_alt_pll_bypass_sels), CLK_SET_RATE_PARENT); @@ -380,7 +380,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) /* PLL out gate */ hws[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base, 13); hws[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13); - hws[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13); + hws[IMX8MN_VIDEO_PLL_OUT] = imx_clk_hw_gate("video_pll_out", "video_pll_bypass", base + 0x28, 13); hws[IMX8MN_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13); hws[IMX8MN_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11); hws[IMX8MN_M7_ALT_PLL_OUT] = imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass", base + 0x74, 11); diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h index 694e3c050d04..04809edab33c 100644 --- a/include/dt-bindings/clock/imx8mn-clock.h +++ b/include/dt-bindings/clock/imx8mn-clock.h @@ -16,7 +16,8 @@ #define IMX8MN_CLK_EXT4 7 #define IMX8MN_AUDIO_PLL1_REF_SEL 8 #define IMX8MN_AUDIO_PLL2_REF_SEL 9 -#define IMX8MN_VIDEO_PLL1_REF_SEL 10 +#define IMX8MN_VIDEO_PLL_REF_SEL 10 +#define IMX8MN_VIDEO_PLL1_REF_SEL IMX8MN_VIDEO_PLL_REF_SEL #define IMX8MN_DRAM_PLL_REF_SEL 11 #define IMX8MN_GPU_PLL_REF_SEL 12 #define IMX8MN_M7_ALT_PLL_REF_SEL 13 @@ -27,7 +28,8 @@ #define IMX8MN_SYS_PLL3_REF_SEL 17 #define IMX8MN_AUDIO_PLL1 18 #define IMX8MN_AUDIO_PLL2 19 -#define IMX8MN_VIDEO_PLL1 20 +#define IMX8MN_VIDEO_PLL 20 +#define IMX8MN_VIDEO_PLL1 IMX8MN_VIDEO_PLL #define IMX8MN_DRAM_PLL 21 #define IMX8MN_GPU_PLL 22 #define IMX8MN_M7_ALT_PLL 23 @@ -38,7 +40,8 @@ #define IMX8MN_SYS_PLL3 27 #define IMX8MN_AUDIO_PLL1_BYPASS 28 #define IMX8MN_AUDIO_PLL2_BYPASS 29 -#define IMX8MN_VIDEO_PLL1_BYPASS 30 +#define IMX8MN_VIDEO_PLL_BYPASS 30 +#define IMX8MN_VIDEO_PLL1_BYPASS IMX8MN_VIDEO_PLL_BYPASS #define IMX8MN_DRAM_PLL_BYPASS 31 #define IMX8MN_GPU_PLL_BYPASS 32 #define IMX8MN_M7_ALT_PLL_BYPASS 33 @@ -49,7 +52,8 @@ #define IMX8MN_SYS_PLL3_BYPASS 37 #define IMX8MN_AUDIO_PLL1_OUT 38 #define IMX8MN_AUDIO_PLL2_OUT 39 -#define IMX8MN_VIDEO_PLL1_OUT 40 +#define IMX8MN_VIDEO_PLL_OUT 40 +#define IMX8MN_VIDEO_PLL1_OUT IMX8MN_VIDEO_PLL_OUT #define IMX8MN_DRAM_PLL_OUT 41 #define IMX8MN_GPU_PLL_OUT 42 #define IMX8MN_M7_ALT_PLL_OUT 43 From 34d996747a74e3a86990f9f9c48de09159d78edb Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Thu, 17 Nov 2022 12:36:36 +0100 Subject: [PATCH 34/36] clk: imx8mn: fix imx8mn_sai2_sels clocks list According to the "Clock Root" table of the reference manual (document IMX8MNRM Rev 2, 07/2022): Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX]) ... ... ... SAI2_CLK_ROOT 0xA600 000 - 24M_REF_CLK 001 - AUDIO_PLL1_CLK 010 - AUDIO_PLL2_CLK 011 - VIDEO_PLL_CLK 100 - SYSTEM_PLL1_DIV6 110 - EXT_CLK_2 111 - EXT_CLK_3 ... ... ... while the imx8mn_sai2_sels list contained clk_ext3 and clk_ext4 for source select bits 110b and 111b. Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Dario Binacchi Acked-by: Marco Felsch Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20221117113637.1978703-5-dario.binacchi@amarulasolutions.com --- drivers/clk/imx/clk-imx8mn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index b80af5d1ef46..37128c35198d 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -109,7 +109,7 @@ static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll_out" static const char * const imx8mn_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "dummy", - "clk_ext3", "clk_ext4", }; + "clk_ext2", "clk_ext3", }; static const char * const imx8mn_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "dummy", From 2626cf67f20b28446dfc3a5b9493dd535cdb747b Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Thu, 17 Nov 2022 12:36:37 +0100 Subject: [PATCH 35/36] clk: imx8mn: fix imx8mn_enet_phy_sels clocks list According to the "Clock Root" table of the reference manual (document IMX8MNRM Rev 2, 07/2022): Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX]) ... ... ... ENET_PHY_REF_CLK_ROOT 0xAA80 000 - 24M_REF_CLK 001 - SYSTEM_PLL2_DIV20 010 - SYSTEM_PLL2_DIV8 011 - SYSTEM_PLL2_DIV5 100 - SYSTEM_PLL2_DIV2 101 - AUDIO_PLL1_CLK 110 - VIDEO_PLL_CLK 111 - AUDIO_PLL2_CLK ... ... ... while the imx8mn_enet_phy_sels list didn't contained audio_pll1_out for source select bits 101b. Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Dario Binacchi Acked-by: Marco Felsch Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20221117113637.1978703-6-dario.binacchi@amarulasolutions.com --- drivers/clk/imx/clk-imx8mn.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 37128c35198d..2afea905f7f3 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -140,8 +140,8 @@ static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m" "clk_ext4", "video_pll_out", }; static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", - "sys_pll2_200m", "sys_pll2_500m", "video_pll_out", - "audio_pll2_out", }; + "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out", + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", From 8178e245fa953f793670147368642717fcdb302e Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Sun, 13 Nov 2022 19:08:39 +0100 Subject: [PATCH 36/36] clk: imx: rename imx_obtain_fixed_clk_hw() to imx_get_clk_hw_by_name() The imx_obtain_fixed_clk_hw name was wrong and misleading. Renaming it to imx_get_clk_hw_by_name clarifies the purpose of the function, and will allow it to be used not only for fixed rate clocks but also in wider contexts. No functional changes intended. The replacements were made with the following command: grep -rl 'imx_obtain_fixed_clk_hw' ./ | \ xargs sed -i 's/imx_obtain_fixed_clk_hw/imx_get_clk_hw_by_name/g' Tested on a BSH SystemMaster (SMM) S2 board. Signed-off-by: Dario Binacchi Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20221113180839.1625832-1-dario.binacchi@amarulasolutions.com --- drivers/clk/imx/clk-imx6sll.c | 8 ++++---- drivers/clk/imx/clk-imx6sx.c | 12 ++++++------ drivers/clk/imx/clk-imx6ul.c | 8 ++++---- drivers/clk/imx/clk-imx7d.c | 4 ++-- drivers/clk/imx/clk-imx7ulp.c | 10 +++++----- drivers/clk/imx/clk-imx8mm.c | 12 ++++++------ drivers/clk/imx/clk-imx8mn.c | 12 ++++++------ drivers/clk/imx/clk-imx8mp.c | 12 ++++++------ drivers/clk/imx/clk-imx8mq.c | 14 +++++++------- drivers/clk/imx/clk-imx93.c | 6 +++--- drivers/clk/imx/clk-imxrt1050.c | 2 +- drivers/clk/imx/clk.c | 5 ++--- drivers/clk/imx/clk.h | 3 +-- 13 files changed, 53 insertions(+), 55 deletions(-) diff --git a/drivers/clk/imx/clk-imx6sll.c b/drivers/clk/imx/clk-imx6sll.c index 31d777f30039..1c9351649eab 100644 --- a/drivers/clk/imx/clk-imx6sll.c +++ b/drivers/clk/imx/clk-imx6sll.c @@ -91,12 +91,12 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node) hws[IMX6SLL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX6SLL_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil"); - hws[IMX6SLL_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc"); + hws[IMX6SLL_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil"); + hws[IMX6SLL_CLK_OSC] = imx_get_clk_hw_by_name(ccm_node, "osc"); /* ipp_di clock is external input */ - hws[IMX6SLL_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0"); - hws[IMX6SLL_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1"); + hws[IMX6SLL_CLK_IPP_DI0] = imx_get_clk_hw_by_name(ccm_node, "ipp_di0"); + hws[IMX6SLL_CLK_IPP_DI1] = imx_get_clk_hw_by_name(ccm_node, "ipp_di1"); np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop"); base = of_iomap(np, 0); diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c index 598f3cf4eba4..b378531240e6 100644 --- a/drivers/clk/imx/clk-imx6sx.c +++ b/drivers/clk/imx/clk-imx6sx.c @@ -132,16 +132,16 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) hws[IMX6SX_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX6SX_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil"); - hws[IMX6SX_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc"); + hws[IMX6SX_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil"); + hws[IMX6SX_CLK_OSC] = imx_get_clk_hw_by_name(ccm_node, "osc"); /* ipp_di clock is external input */ - hws[IMX6SX_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0"); - hws[IMX6SX_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1"); + hws[IMX6SX_CLK_IPP_DI0] = imx_get_clk_hw_by_name(ccm_node, "ipp_di0"); + hws[IMX6SX_CLK_IPP_DI1] = imx_get_clk_hw_by_name(ccm_node, "ipp_di1"); /* Clock source from external clock via CLK1/2 PAD */ - hws[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clk_hw(ccm_node, "anaclk1"); - hws[IMX6SX_CLK_ANACLK2] = imx_obtain_fixed_clk_hw(ccm_node, "anaclk2"); + hws[IMX6SX_CLK_ANACLK1] = imx_get_clk_hw_by_name(ccm_node, "anaclk1"); + hws[IMX6SX_CLK_ANACLK2] = imx_get_clk_hw_by_name(ccm_node, "anaclk2"); np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); base = of_iomap(np, 0); diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index 520b100bff4b..67a7a77ca540 100644 --- a/drivers/clk/imx/clk-imx6ul.c +++ b/drivers/clk/imx/clk-imx6ul.c @@ -126,12 +126,12 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) hws[IMX6UL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX6UL_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil"); - hws[IMX6UL_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc"); + hws[IMX6UL_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil"); + hws[IMX6UL_CLK_OSC] = imx_get_clk_hw_by_name(ccm_node, "osc"); /* ipp_di clock is external input */ - hws[IMX6UL_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0"); - hws[IMX6UL_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1"); + hws[IMX6UL_CLK_IPP_DI0] = imx_get_clk_hw_by_name(ccm_node, "ipp_di0"); + hws[IMX6UL_CLK_IPP_DI1] = imx_get_clk_hw_by_name(ccm_node, "ipp_di1"); np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop"); base = of_iomap(np, 0); diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index cbf8131c63f7..d681b6c4b29a 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -391,8 +391,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) hws = clk_hw_data->hws; hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX7D_OSC_24M_CLK] = imx_obtain_fixed_clk_hw(ccm_node, "osc"); - hws[IMX7D_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil"); + hws[IMX7D_OSC_24M_CLK] = imx_get_clk_hw_by_name(ccm_node, "osc"); + hws[IMX7D_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil"); np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-anatop"); base = of_iomap(np, 0); diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c index b6e45e77ee39..208a0ab80d5e 100644 --- a/drivers/clk/imx/clk-imx7ulp.c +++ b/drivers/clk/imx/clk-imx7ulp.c @@ -59,11 +59,11 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np) hws[IMX7ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX7ULP_CLK_ROSC] = imx_obtain_fixed_clk_hw(np, "rosc"); - hws[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc"); - hws[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc"); - hws[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc"); - hws[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll"); + hws[IMX7ULP_CLK_ROSC] = imx_get_clk_hw_by_name(np, "rosc"); + hws[IMX7ULP_CLK_SOSC] = imx_get_clk_hw_by_name(np, "sosc"); + hws[IMX7ULP_CLK_SIRC] = imx_get_clk_hw_by_name(np, "sirc"); + hws[IMX7ULP_CLK_FIRC] = imx_get_clk_hw_by_name(np, "firc"); + hws[IMX7ULP_CLK_UPLL] = imx_get_clk_hw_by_name(np, "upll"); /* SCG1 */ base = of_iomap(np, 0); diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index b6d275855b36..cb44e8148e53 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -312,12 +312,12 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) hws = clk_hw_data->hws; hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX8MM_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m"); - hws[IMX8MM_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k"); - hws[IMX8MM_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); - hws[IMX8MM_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); - hws[IMX8MM_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); - hws[IMX8MM_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); + hws[IMX8MM_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); + hws[IMX8MM_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); + hws[IMX8MM_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); + hws[IMX8MM_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2"); + hws[IMX8MM_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3"); + hws[IMX8MM_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4"); np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); base = of_iomap(np, 0); diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 2afea905f7f3..af256ade554f 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -332,12 +332,12 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws = clk_hw_data->hws; hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX8MN_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m"); - hws[IMX8MN_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k"); - hws[IMX8MN_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); - hws[IMX8MN_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); - hws[IMX8MN_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); - hws[IMX8MN_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); + hws[IMX8MN_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); + hws[IMX8MN_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); + hws[IMX8MN_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); + hws[IMX8MN_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2"); + hws[IMX8MN_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3"); + hws[IMX8MN_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4"); np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop"); base = of_iomap(np, 0); diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 423a5d02b553..a57d877d393d 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -438,12 +438,12 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws = clk_hw_data->hws; hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX8MP_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m"); - hws[IMX8MP_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k"); - hws[IMX8MP_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); - hws[IMX8MP_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); - hws[IMX8MP_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); - hws[IMX8MP_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); + hws[IMX8MP_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); + hws[IMX8MP_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); + hws[IMX8MP_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); + hws[IMX8MP_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2"); + hws[IMX8MP_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3"); + hws[IMX8MP_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4"); hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 882dcad4817d..2bcaec19a999 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -297,13 +297,13 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) hws = clk_hw_data->hws; hws[IMX8MQ_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX8MQ_CLK_32K] = imx_obtain_fixed_clk_hw(np, "ckil"); - hws[IMX8MQ_CLK_25M] = imx_obtain_fixed_clk_hw(np, "osc_25m"); - hws[IMX8MQ_CLK_27M] = imx_obtain_fixed_clk_hw(np, "osc_27m"); - hws[IMX8MQ_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); - hws[IMX8MQ_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); - hws[IMX8MQ_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); - hws[IMX8MQ_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); + hws[IMX8MQ_CLK_32K] = imx_get_clk_hw_by_name(np, "ckil"); + hws[IMX8MQ_CLK_25M] = imx_get_clk_hw_by_name(np, "osc_25m"); + hws[IMX8MQ_CLK_27M] = imx_get_clk_hw_by_name(np, "osc_27m"); + hws[IMX8MQ_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); + hws[IMX8MQ_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2"); + hws[IMX8MQ_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3"); + hws[IMX8MQ_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4"); np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop"); base = of_iomap(np, 0); diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index 5bd06ebd6826..e464d9e71fbc 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -271,9 +271,9 @@ static int imx93_clocks_probe(struct platform_device *pdev) clks = clk_hw_data->hws; clks[IMX93_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - clks[IMX93_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m"); - clks[IMX93_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k"); - clks[IMX93_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); + clks[IMX93_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); + clks[IMX93_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); + clks[IMX93_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); clks[IMX93_CLK_SYS_PLL_PFD0] = imx_clk_hw_fixed("sys_pll_pfd0", 1000000000); clks[IMX93_CLK_SYS_PLL_PFD0_DIV2] = imx_clk_hw_fixed_factor("sys_pll_pfd0_div2", diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index 39f77c03b892..e972abd299a8 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -50,7 +50,7 @@ static int imxrt1050_clocks_probe(struct platform_device *pdev) clk_hw_data->num = IMXRT1050_CLK_END; hws = clk_hw_data->hws; - hws[IMXRT1050_CLK_OSC] = imx_obtain_fixed_clk_hw(np, "osc"); + hws[IMXRT1050_CLK_OSC] = imx_get_clk_hw_by_name(np, "osc"); anp = of_find_compatible_node(NULL, NULL, "fsl,imxrt-anatop"); pll_base = of_iomap(anp, 0); diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index 5582f18dd632..b636cc099d96 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -110,8 +110,7 @@ struct clk_hw *imx_obtain_fixed_clock_hw( return __clk_get_hw(clk); } -struct clk_hw * imx_obtain_fixed_clk_hw(struct device_node *np, - const char *name) +struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name) { struct clk *clk; @@ -121,7 +120,7 @@ struct clk_hw * imx_obtain_fixed_clk_hw(struct device_node *np, return __clk_get_hw(clk); } -EXPORT_SYMBOL_GPL(imx_obtain_fixed_clk_hw); +EXPORT_SYMBOL_GPL(imx_get_clk_hw_by_name); /* * This fixups the register CCM_CSCMR1 write value. diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index dd49f90110e8..689b3ad927c0 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -288,8 +288,7 @@ struct clk * imx_obtain_fixed_clock( struct clk_hw *imx_obtain_fixed_clock_hw( const char *name, unsigned long rate); -struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np, - const char *name); +struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name); struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent, void __iomem *reg, u8 shift, u32 exclusive_mask);