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arm64: spectre: Rename ARM64_HARDEN_EL2_VECTORS to ARM64_SPECTRE_V3A

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Since ARM64_HARDEN_EL2_VECTORS is really a mitigation for Spectre-v3a,
rename it accordingly for consistency with the v2 and v4 mitigation.

Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Quentin Perret <qperret@google.com>
Link: https://lore.kernel.org/r/20201113113847.21619-9-will@kernel.org
This commit is contained in:
Will Deacon
2020-11-16 10:43:06 +00:00
committed by Marc Zyngier
parent b881cdce77
commit c4792b6dbc
8 changed files with 22 additions and 18 deletions
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arch/arm64/kernel/cpu_errata.c
+3 -3
View File
@@ -460,10 +460,10 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
#ifdef CONFIG_RANDOMIZE_BASE
{
/* Must come after the Spectre-v2 entry */
.desc = "EL2 vector hardening",
.capability = ARM64_HARDEN_EL2_VECTORS,
.desc = "Spectre-v3a",
.capability = ARM64_SPECTRE_V3A,
ERRATA_MIDR_RANGE_LIST(ca57_a72),
.cpu_enable = cpu_el2_vector_harden_enable,
.cpu_enable = spectre_v3a_enable_mitigation,
},
#endif
{
arch/arm64/kernel/proton-pack.c
+10 -3
View File
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Handle detection, reporting and mitigation of Spectre v1, v2 and v4, as
* Handle detection, reporting and mitigation of Spectre v1, v2, v3a and v4, as
* detailed at:
*
* https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability
@@ -270,11 +270,18 @@ void spectre_v2_enable_mitigation(const struct arm64_cpu_capabilities *__unused)
update_mitigation_state(&spectre_v2_state, state);
}
void cpu_el2_vector_harden_enable(const struct arm64_cpu_capabilities *__unused)
/*
* Spectre-v3a.
*
* Phew, there's not an awful lot to do here! We just instruct EL2 to use
* an indirect trampoline for the hyp vectors so that guests can't read
* VBAR_EL2 to defeat randomisation of the hypervisor VA layout.
*/
void spectre_v3a_enable_mitigation(const struct arm64_cpu_capabilities *__unused)
{
struct bp_hardening_data *data = this_cpu_ptr(&bp_hardening_data);
if (this_cpu_has_cap(ARM64_HARDEN_EL2_VECTORS))
if (this_cpu_has_cap(ARM64_SPECTRE_V3A))
data->slot += HYP_VECTOR_INDIRECT;
}