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Merge branch 'pm-cpufreq'

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* pm-cpufreq: (33 commits)
  cpufreq: imx6q: Fix imx6sx low frequency support
  cpufreq: speedstep-lib: make several arrays static, makes code smaller
  cpufreq: ti: Fix 'of_node_put' being called twice in error handling path
  cpufreq: dt-platdev: Drop few entries from whitelist
  cpufreq: dt-platdev: Automatically create cpufreq device with OPP v2
  ARM: ux500: don't select CPUFREQ_DT
  cpufreq: Convert to using %pOF instead of full_name
  cpufreq: Cap the default transition delay value to 10 ms
  cpufreq: dbx500: Delete obsolete driver
  mfd: db8500-prcmu: Get rid of cpufreq dependency
  cpufreq: enable the DT cpufreq driver on the Ux500
  cpufreq: Loongson2: constify platform_device_id
  cpufreq: dt: Add r8a7796 support to to use generic cpufreq driver
  cpufreq: remove setting of policy->cpu in policy->cpus during init
  cpufreq: mediatek: add support of cpufreq to MT7622 SoC
  cpufreq: mediatek: add cleanups with the more generic naming
  cpufreq: rcar: Add support for R8A7795 SoC
  cpufreq: dt: Add rk3328 compatible to use generic cpufreq driver
  cpufreq: s5pv210: add missing of_node_put()
  cpufreq: Allow dynamic switching with CPUFREQ_ETERNAL latency
  ...
This commit is contained in:
Rafael J. Wysocki
2017-09-04 00:05:13 +02:00
parent 45a7953c83 fded5fc841
commit bd87c8fb9d
39 changed files with 470 additions and 378 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/mfd/db8500-prcmu.c
+21 -41
View File
@@ -33,7 +33,6 @@
#include <linux/mfd/abx500/ab8500.h>
#include <linux/regulator/db8500-prcmu.h>
#include <linux/regulator/machine.h>
#include <linux/cpufreq.h>
#include <linux/platform_data/ux500_wdt.h>
#include <linux/platform_data/db8500_thermal.h>
#include "dbx500-prcmu-regs.h"
@@ -1692,32 +1691,27 @@ static long round_clock_rate(u8 clock, unsigned long rate)
return rounded_rate;
}
/* CPU FREQ table, may be changed due to if MAX_OPP is supported. */
static struct cpufreq_frequency_table db8500_cpufreq_table[] = {
{ .frequency = 200000, .driver_data = ARM_EXTCLK,},
{ .frequency = 400000, .driver_data = ARM_50_OPP,},
{ .frequency = 800000, .driver_data = ARM_100_OPP,},
{ .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */
{ .frequency = CPUFREQ_TABLE_END,},
static const unsigned long armss_freqs[] = {
200000000,
400000000,
800000000,
998400000
};
static long round_armss_rate(unsigned long rate)
{
struct cpufreq_frequency_table *pos;
long freq = 0;
/* cpufreq table frequencies is in KHz. */
rate = rate / 1000;
unsigned long freq = 0;
int i;
/* Find the corresponding arm opp from the cpufreq table. */
cpufreq_for_each_entry(pos, db8500_cpufreq_table) {
freq = pos->frequency;
if (freq == rate)
for (i = 0; i < ARRAY_SIZE(armss_freqs); i++) {
freq = armss_freqs[i];
if (rate <= freq)
break;
}
/* Return the last valid value, even if a match was not found. */
return freq * 1000;
return freq;
}
#define MIN_PLL_VCO_RATE 600000000ULL
@@ -1854,21 +1848,23 @@ static void set_clock_rate(u8 clock, unsigned long rate)
static int set_armss_rate(unsigned long rate)
{
struct cpufreq_frequency_table *pos;
/* cpufreq table frequencies is in KHz. */
rate = rate / 1000;
unsigned long freq;
u8 opps[] = { ARM_EXTCLK, ARM_50_OPP, ARM_100_OPP, ARM_MAX_OPP };
int i;
/* Find the corresponding arm opp from the cpufreq table. */
cpufreq_for_each_entry(pos, db8500_cpufreq_table)
if (pos->frequency == rate)
for (i = 0; i < ARRAY_SIZE(armss_freqs); i++) {
freq = armss_freqs[i];
if (rate == freq)
break;
}
if (pos->frequency != rate)
if (rate != freq)
return -EINVAL;
/* Set the new arm opp. */
return db8500_prcmu_set_arm_opp(pos->driver_data);
pr_debug("SET ARM OPP 0x%02x\n", opps[i]);
return db8500_prcmu_set_arm_opp(opps[i]);
}
static int set_plldsi_rate(unsigned long rate)
@@ -3048,12 +3044,6 @@ static const struct mfd_cell db8500_prcmu_devs[] = {
.platform_data = &db8500_regulators,
.pdata_size = sizeof(db8500_regulators),
},
{
.name = "cpufreq-ux500",
.of_compatible = "stericsson,cpufreq-ux500",
.platform_data = &db8500_cpufreq_table,
.pdata_size = sizeof(db8500_cpufreq_table),
},
{
.name = "cpuidle-dbx500",
.of_compatible = "stericsson,cpuidle-dbx500",
@@ -3067,14 +3057,6 @@ static const struct mfd_cell db8500_prcmu_devs[] = {
},
};
static void db8500_prcmu_update_cpufreq(void)
{
if (prcmu_has_arm_maxopp()) {
db8500_cpufreq_table[3].frequency = 1000000;
db8500_cpufreq_table[3].driver_data = ARM_MAX_OPP;
}
}
static int db8500_prcmu_register_ab8500(struct device *parent)
{
struct device_node *np;
@@ -3160,8 +3142,6 @@ static int db8500_prcmu_probe(struct platform_device *pdev)
prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
db8500_prcmu_update_cpufreq();
err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs,
ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain);
if (err) {