Merge remote-tracking branch 'kumar/next' into next

From Kumar Gala:
<<
Add support for T4 and B4 SoC families from Freescale, e6500 altivec
support, some various board fixes and other minor cleanups.
>>
This commit is contained in:
Benjamin Herrenschmidt
2013-04-30 11:10:09 +10:00
60 changed files with 2735 additions and 92 deletions
@@ -0,0 +1,22 @@
===================================================================
Power Architecture CPU Binding
Copyright 2013 Freescale Semiconductor Inc.
Power Architecture CPUs in Freescale SOCs are represented in device trees as
per the definition in ePAPR.
In addition to the ePAPR definitions, the properties defined below may be
present on CPU nodes.
PROPERTIES
- fsl,eref-*
Usage: optional
Value type: <empty>
Definition: The EREF (EREF: A Programmer.s Reference Manual for
Freescale Power Architecture) defines the architecture for Freescale
Power CPUs. The EREF defines some architecture categories not defined
by the Power ISA. For these EREF-specific categories, the existence of
a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
name with all uppercase letters converted to lowercase, indicates that
the category is supported by the implementation.