rdc321x: GPIO routines bugfixes

This patch fixes the use of GPIO routines which are in the PCI
configuration space of the RDC321x, therefore reading/writing
to this space without spinlock protection can be problematic.

We also now request and free GPIOs and support the MGB100
board, previous code was very AR525W-centric.

Signed-off-by: Volker Weiss <volker@tintuc.de>
Signed-off-by: Florian Fainelli <florian.fainelli@telecomint.eu>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Florian Fainelli
2008-03-27 16:08:45 +01:00
committed by Ingo Molnar
parent d8d4f157b8
commit b2ef749720
4 changed files with 167 additions and 55 deletions
+5 -4
View File
@@ -5,19 +5,20 @@ extern int rdc_gpio_get_value(unsigned gpio);
extern void rdc_gpio_set_value(unsigned gpio, int value);
extern int rdc_gpio_direction_input(unsigned gpio);
extern int rdc_gpio_direction_output(unsigned gpio, int value);
extern int rdc_gpio_request(unsigned gpio, const char *label);
extern void rdc_gpio_free(unsigned gpio);
extern void __init rdc321x_gpio_setup(void);
/* Wrappers for the arch-neutral GPIO API */
static inline int gpio_request(unsigned gpio, const char *label)
{
/* Not yet implemented */
return 0;
return rdc_gpio_request(gpio, label);
}
static inline void gpio_free(unsigned gpio)
{
/* Not yet implemented */
rdc_gpio_free(gpio);
}
static inline int gpio_direction_input(unsigned gpio)
+7 -1
View File
@@ -3,4 +3,10 @@
/* General purpose configuration and data registers */
#define RDC3210_CFGREG_ADDR 0x0CF8
#define RDC3210_CFGREG_DATA 0x0CFC
#define RDC_MAX_GPIO 0x3A
#define RDC321X_GPIO_CTRL_REG1 0x48
#define RDC321X_GPIO_CTRL_REG2 0x84
#define RDC321X_GPIO_DATA_REG1 0x4c
#define RDC321X_GPIO_DATA_REG2 0x88
#define RDC321X_MAX_GPIO 58