rdc321x: GPIO routines bugfixes
This patch fixes the use of GPIO routines which are in the PCI configuration space of the RDC321x, therefore reading/writing to this space without spinlock protection can be problematic. We also now request and free GPIOs and support the MGB100 board, previous code was very AR525W-centric. Signed-off-by: Volker Weiss <volker@tintuc.de> Signed-off-by: Florian Fainelli <florian.fainelli@telecomint.eu> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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Ingo Molnar
parent
d8d4f157b8
commit
b2ef749720
@@ -5,19 +5,20 @@ extern int rdc_gpio_get_value(unsigned gpio);
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extern void rdc_gpio_set_value(unsigned gpio, int value);
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extern int rdc_gpio_direction_input(unsigned gpio);
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extern int rdc_gpio_direction_output(unsigned gpio, int value);
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extern int rdc_gpio_request(unsigned gpio, const char *label);
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extern void rdc_gpio_free(unsigned gpio);
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extern void __init rdc321x_gpio_setup(void);
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/* Wrappers for the arch-neutral GPIO API */
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static inline int gpio_request(unsigned gpio, const char *label)
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{
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/* Not yet implemented */
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return 0;
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return rdc_gpio_request(gpio, label);
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}
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static inline void gpio_free(unsigned gpio)
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{
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/* Not yet implemented */
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rdc_gpio_free(gpio);
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}
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static inline int gpio_direction_input(unsigned gpio)
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@@ -3,4 +3,10 @@
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/* General purpose configuration and data registers */
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#define RDC3210_CFGREG_ADDR 0x0CF8
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#define RDC3210_CFGREG_DATA 0x0CFC
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#define RDC_MAX_GPIO 0x3A
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#define RDC321X_GPIO_CTRL_REG1 0x48
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#define RDC321X_GPIO_CTRL_REG2 0x84
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#define RDC321X_GPIO_DATA_REG1 0x4c
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#define RDC321X_GPIO_DATA_REG2 0x88
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#define RDC321X_MAX_GPIO 58
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