Merge branch 'remotes/lorenzo/pci/endpoint'
- Use notification chain instead of EPF linkup ops for EPC events (Kishon
Vijay Abraham I)
- Protect concurrent allocation in endpoint outbound address region
(Kishon Vijay Abraham I)
- Protect concurrent access to pci_epf_ops (Kishon Vijay Abraham I)
- Assign function number for each PF in endpoint core (Kishon Vijay
Abraham I)
- Refactor endpoint mode core initialization (Vidya Sagar)
- Add API to notify when core initialization completes (Vidya Sagar)
- Add test framework support to defer core initialization (Vidya Sagar)
- Update Tegra SoC ABI header to support uninitialization of UPHY PLL
when in endpoint mode without reference clock (Vidya Sagar)
- Add DT and driver support for Tegra194 PCIe endpoint nodes (Vidya
Sagar)
- Add endpoint test support for DMA data transfer (Kishon Vijay
Abraham I)
- Print throughput information in endpoint test (Kishon Vijay Abraham I)
- Use streaming DMA APIs for endpoint test buffer allocation (Kishon
Vijay Abraham I)
- Add endpoint test command line option for DMA (Kishon Vijay Abraham I)
- When stopping a controller via configfs, clear endpoint "start" entry
to prevent WARN_ON (Kunihiko Hayashi)
- Update endpoint ->set_msix() to pay attention to MSI-X BAR Indicator
and offset when finding MSI-X tables (Kishon Vijay Abraham I)
- MSI-X tables are in local memory, not in the PCI address space. Update
pcie-designware-ep to account for this (Kishon Vijay Abraham I)
- Allow AM654 PCIe Endpoint to raise MSI-X interrupts (Kishon Vijay
Abraham I)
- Avoid using module parameter to determine irqtype for endpoint test
(Kishon Vijay Abraham I)
- Add ioctl to clear IRQ for endpoint test (Kishon Vijay Abraham I)
- Add endpoint test 'e' option to clear IRQ (Kishon Vijay Abraham I)
- Bump limit on number of endpoint test devices from 10 to 10,000 (Kishon
Vijay Abraham I)
- Use full pci-endpoint-test name in request_irq() for easier profiling
(Kishon Vijay Abraham I)
- Reduce log level of -EPROBE_DEFER error messages to debug (Thierry
Reding)
* remotes/lorenzo/pci/endpoint:
misc: pci_endpoint_test: remove duplicate macro PCI_ENDPOINT_TEST_STATUS
PCI: tegra: Print -EPROBE_DEFER error message at debug level
misc: pci_endpoint_test: Use full pci-endpoint-test name in request_irq()
misc: pci_endpoint_test: Fix to support > 10 pci-endpoint-test devices
tools: PCI: Add 'e' to clear IRQ
misc: pci_endpoint_test: Add ioctl to clear IRQ
misc: pci_endpoint_test: Avoid using module parameter to determine irqtype
PCI: keystone: Allow AM654 PCIe Endpoint to raise MSI-X interrupt
PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address
PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments
misc: pci_endpoint_test: Add support to get DMA option from userspace
tools: PCI: Add 'd' command line option to support DMA
misc: pci_endpoint_test: Use streaming DMA APIs for buffer allocation
PCI: endpoint: functions/pci-epf-test: Print throughput information
PCI: endpoint: functions/pci-epf-test: Add DMA support to transfer data
PCI: endpoint: Fix clearing start entry in configfs
PCI: tegra: Add support for PCIe endpoint mode in Tegra194
dt-bindings: PCI: tegra: Add DT support for PCIe EP nodes in Tegra194
soc/tegra: bpmp: Update ABI header
PCI: pci-epf-test: Add support to defer core initialization
PCI: dwc: Add API to notify core initialization completion
PCI: endpoint: Add notification for core init completion
PCI: dwc: Refactor core initialization code for EP mode
PCI: endpoint: Add core init notifying feature
PCI: endpoint: Assign function number for each PF in EPC core
PCI: endpoint: Protect concurrent access to pci_epf_ops with mutex
PCI: endpoint: Fix for concurrent memory allocation in OB address region
PCI: endpoint: Replace spinlock with mutex
PCI: endpoint: Use notification chain mechanism to notify EPC events to EPF
This commit is contained in:
Bjorn Helgaas
@@ -1,11 +1,11 @@
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NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
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This PCIe host controller is based on the Synopsis Designware PCIe IP
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This PCIe controller is based on the Synopsis Designware PCIe IP
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and thus inherits all the common properties defined in designware-pcie.txt.
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Some of the controller instances are dual mode where in they can work either
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in root port mode or endpoint mode but one at a time.
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Required properties:
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- compatible: For Tegra19x, must contain "nvidia,tegra194-pcie".
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- device_type: Must be "pci"
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- power-domains: A phandle to the node that controls power to the respective
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PCIe controller and a specifier name for the PCIe controller. Following are
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the specifiers for the different PCIe controllers
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@@ -32,6 +32,32 @@ Required properties:
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entry for each entry in the interrupt-names property.
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- interrupt-names: Must include the following entries:
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"intr": The Tegra interrupt that is asserted for controller interrupts
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- core
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- apb
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- core
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- phys: Must contain a phandle to P2U PHY for each entry in phy-names.
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- phy-names: Must include an entry for each active lane.
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"p2u-N": where N ranges from 0 to one less than the total number of lanes
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- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed
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by controller-id. Following are the controller ids for each controller.
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0: C0
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1: C1
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2: C2
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3: C3
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4: C4
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5: C5
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- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
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RC mode:
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- compatible: Tegra19x must contain "nvidia,tegra194-pcie"
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- device_type: Must be "pci" for RC mode
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- interrupt-names: Must include the following entries:
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"msi": The Tegra interrupt that is asserted when an MSI is received
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- bus-range: Range of bus numbers associated with this controller
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- #address-cells: Address representation for root ports (must be 3)
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@@ -60,27 +86,15 @@ Required properties:
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- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
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Please refer to the standard PCI bus binding document for a more detailed
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explanation.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- core
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- apb
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- core
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- phys: Must contain a phandle to P2U PHY for each entry in phy-names.
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- phy-names: Must include an entry for each active lane.
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"p2u-N": where N ranges from 0 to one less than the total number of lanes
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- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed
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by controller-id. Following are the controller ids for each controller.
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0: C0
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1: C1
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2: C2
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3: C3
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4: C4
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5: C5
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- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
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EP mode:
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In Tegra194, Only controllers C0, C4 & C5 support EP mode.
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- compatible: Tegra19x must contain "nvidia,tegra194-pcie-ep"
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- reg-names: Must include the following entries:
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"addr_space": Used to map remote RC address space
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- reset-gpios: Must contain a phandle to a GPIO controller followed by
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GPIO that is being used as PERST input signal. Please refer to pci.txt
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document.
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Optional properties:
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- pinctrl-names: A list of pinctrl state names.
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@@ -104,6 +118,8 @@ Optional properties:
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specified in microseconds
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- nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be
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specified in microseconds
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RC mode:
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- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot
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if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
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in p2972-0000 platform).
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@@ -111,11 +127,18 @@ Optional properties:
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if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
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in p2972-0000 platform).
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EP mode:
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- nvidia,refclk-select-gpios: Must contain a phandle to a GPIO controller
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followed by GPIO that is being used to enable REFCLK to controller from host
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NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
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operate in the endpoint mode because of the way the platform is designed.
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Examples:
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=========
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Tegra194:
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--------
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Tegra194 RC mode:
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-----------------
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pcie@14180000 {
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compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
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@@ -169,3 +192,53 @@ Tegra194:
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<&p2u_hsio_5>;
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phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
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};
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Tegra194 EP mode:
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-----------------
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pcie_ep@141a0000 {
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compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
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reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
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0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
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0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */
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0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
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reg-names = "appl", "atu_dma", "dbi", "addr_space";
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num-lanes = <8>;
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num-ib-windows = <2>;
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num-ob-windows = <8>;
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pinctrl-names = "default";
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pinctrl-0 = <&clkreq_c5_bi_dir_state>;
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clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
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clock-names = "core";
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resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
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<&bpmp TEGRA194_RESET_PEX1_CORE_5>;
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reset-names = "apb", "core";
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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interrupt-names = "intr";
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nvidia,bpmp = <&bpmp 5>;
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nvidia,aspm-cmrt-us = <60>;
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nvidia,aspm-pwr-on-t-us = <20>;
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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vddio-pex-ctl-supply = <&vdd_1v8ao>;
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reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
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nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
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GPIO_ACTIVE_HIGH>;
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phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
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<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
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<&p2u_nvhs_6>, <&p2u_nvhs_7>;
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phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
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"p2u-5", "p2u-6", "p2u-7";
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};
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