Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Arnd Bergmann:
"Device-tree updates for arm64 platforms. For the first time I can
remember, this is actually larger than the corresponding branch for
32-bit platforms overall, though that has more individual changes.
A significant portion this time is due to added machine support:
- Initial support for the Realtek RTD1295 SoC, along with the Zidoo
X9S set-top-box
- Initial support for Actions Semi S900 and the Bubblegum-96
single-board-cёmputer.
- Rockchips support for the rk3399-Firefly single-board-computer gets
added, this one stands out for being relatively fast, affordable
and well₋supported, compared to many boards that only fall into one
or two of the above categories.
- Mediatek gains support for the mt6797 mobile-phone SoC platform and
corresponding evaluation board.
- Amlogic board support gets added for the NanoPi K2 and S905x
LibreTech CC single-board computers and the R-Box Pro set-top-box
- Allwinner board support gets added for the OrangePi Win, Orangepi
Zero Plus 2, NanoPi NEO2 and Orange Pi Prime single board computers
and the SoPine system-on-module.
- Renesas board support for Salvator-XS and H3ULCB automotive
development systems.
- Socionext Uniphier board support for LD11-global and LD20-global,
whatever those may be.
- Broadcom adds support for the new Stingray communication processor
in its iProc family, along with two reference boards.
Other updates include:
- For the hisicon platform, support for Hi3660-Hikey960 gets extended
significantly.
- Lots of smaller updates for Renesas, Amlogic, Rockchip, UniPhier,
Broadcom, Allwinner, Hisilicon, Qualcomm, Marvell, and NXP"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (243 commits)
ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers
Revert "arm64: dts: marvell: add dma-mask in crypto nodes for 7k/8k"
arm64: dts: mediatek: don't include missing file
ARM64: dts: meson-gxl: Add Libre Technology CC support
dt-bindings: arm: amlogic: Add Libre Technology CC board
dt-bindings: add Libre Technology vendor prefix
arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K
arm64: dts: zte: Use - instead of @ for DT OPP entries
arm64: dts: marvell: add gpio support for Armada 7K/8K
arm64: dts: marvell: add pinctrl support for Armada 7K/8K
arm64: dts: marvell: use new binding for the system controller on cp110
arm64: dts: marvell: remove *-clock-output-names on cp110
arm64: dts: marvell: use new bindings for xor clocks on ap806
arm64: dts: marvell: mcbin: enable the mdio node
arm64: dts: Add Actions Semi S900 and Bubblegum-96
dt-bindings: Add vendor prefix for uCRobotics
arm64: dts: marvell: add xmdio nodes for 7k/8k
arm64: dts: marvell: add a comment on the cp110 slave node status
arm64: dts: marvell: remove cpm crypto nodes from dts files
arm64: dts: marvell: cp110: enable the crypto engine at the SoC level
...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,101 @@
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/*
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* BSD LICENSE
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*
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* Copyright(c) 2017 Broadcom. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Broadcom Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _CLOCK_BCM_SR_H
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#define _CLOCK_BCM_SR_H
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/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
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#define BCM_SR_GENPLL0 0
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#define BCM_SR_GENPLL0_SATA_CLK 1
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#define BCM_SR_GENPLL0_SCR_CLK 2
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#define BCM_SR_GENPLL0_250M_CLK 3
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#define BCM_SR_GENPLL0_PCIE_AXI_CLK 4
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#define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK 5
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#define BCM_SR_GENPLL0_PAXC_AXI_CLK 6
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/* GENPLL 1 clock channel ID MHB PCIE NITRO */
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#define BCM_SR_GENPLL1 0
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#define BCM_SR_GENPLL1_PCIE_TL_CLK 1
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#define BCM_SR_GENPLL1_MHB_APB_CLK 2
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/* GENPLL 2 clock channel ID NITRO MHB*/
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#define BCM_SR_GENPLL2 0
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#define BCM_SR_GENPLL2_NIC_CLK 1
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#define BCM_SR_GENPLL2_250_NITRO_CLK 2
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#define BCM_SR_GENPLL2_125_NITRO_CLK 3
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#define BCM_SR_GENPLL2_CHIMP_CLK 4
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/* GENPLL 3 HSLS clock channel ID */
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#define BCM_SR_GENPLL3 0
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#define BCM_SR_GENPLL3_HSLS_CLK 1
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#define BCM_SR_GENPLL3_SDIO_CLK 2
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/* GENPLL 4 SCR clock channel ID */
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#define BCM_SR_GENPLL4 0
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#define BCM_SR_GENPLL4_CCN_CLK 1
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/* GENPLL 5 FS4 clock channel ID */
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#define BCM_SR_GENPLL5 0
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#define BCM_SR_GENPLL5_FS_CLK 1
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#define BCM_SR_GENPLL5_SPU_CLK 2
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/* GENPLL 6 NITRO clock channel ID */
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#define BCM_SR_GENPLL6 0
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#define BCM_SR_GENPLL6_48_USB_CLK 1
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/* LCPLL0 clock channel ID */
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#define BCM_SR_LCPLL0 0
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#define BCM_SR_LCPLL0_SATA_REF_CLK 1
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#define BCM_SR_LCPLL0_USB_REF_CLK 2
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#define BCM_SR_LCPLL0_SATA_REFPN_CLK 3
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/* LCPLL1 clock channel ID */
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#define BCM_SR_LCPLL1 0
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#define BCM_SR_LCPLL1_WAN_CLK 1
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/* LCPLL PCIE clock channel ID */
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#define BCM_SR_LCPLL_PCIE 0
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#define BCM_SR_LCPLL_PCIE_PHY_REF_CLK 1
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/* GENPLL EMEM0 clock channel ID */
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#define BCM_SR_EMEMPLL0 0
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#define BCM_SR_EMEMPLL0_EMEM_CLK 1
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/* GENPLL EMEM0 clock channel ID */
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#define BCM_SR_EMEMPLL1 0
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#define BCM_SR_EMEMPLL1_EMEM_CLK 1
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/* GENPLL EMEM0 clock channel ID */
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#define BCM_SR_EMEMPLL2 0
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#define BCM_SR_EMEMPLL2_EMEM_CLK 1
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#endif /* _CLOCK_BCM_SR_H */
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@@ -0,0 +1,68 @@
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/*
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* BSD LICENSE
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*
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* Copyright(c) 2017 Broadcom Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Broadcom Corporation nor the names of its
|
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
|
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__
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#define __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__
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/* Alternate functions available in MUX controller */
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#define MODE_NITRO 0
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#define MODE_NAND 1
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#define MODE_PNOR 2
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#define MODE_GPIO 3
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/* Pad configuration attribute */
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#define PAD_SLEW_RATE_ENA (1 << 0)
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#define PAD_SLEW_RATE_ENA_MASK (1 << 0)
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#define PAD_DRIVE_STRENGTH_2_MA (0 << 1)
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#define PAD_DRIVE_STRENGTH_4_MA (1 << 1)
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#define PAD_DRIVE_STRENGTH_6_MA (2 << 1)
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#define PAD_DRIVE_STRENGTH_8_MA (3 << 1)
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#define PAD_DRIVE_STRENGTH_10_MA (4 << 1)
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#define PAD_DRIVE_STRENGTH_12_MA (5 << 1)
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#define PAD_DRIVE_STRENGTH_14_MA (6 << 1)
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#define PAD_DRIVE_STRENGTH_16_MA (7 << 1)
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#define PAD_DRIVE_STRENGTH_MASK (7 << 1)
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#define PAD_PULL_UP_ENA (1 << 4)
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#define PAD_PULL_UP_ENA_MASK (1 << 4)
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#define PAD_PULL_DOWN_ENA (1 << 5)
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#define PAD_PULL_DOWN_ENA_MASK (1 << 5)
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#define PAD_INPUT_PATH_DIS (1 << 6)
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#define PAD_INPUT_PATH_DIS_MASK (1 << 6)
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#define PAD_HYSTERESIS_ENA (1 << 7)
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#define PAD_HYSTERESIS_ENA_MASK (1 << 7)
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#endif
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