dlan17/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

[Blackfin] arch: Fix bug to Enable bf548 to Re-program Clocks while Kernel boots.

Browse Source 
Reprogram DDR EBIU register properly for bf548.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
Sonic Zhang
2008-01-27 16:32:31 +08:00
committed by Bryan Wu
parent b03b08ba9c
commit 971d5bc4e5
4 changed files with 153 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/blackfin/Kconfig
+17 -2
View File
@@ -317,7 +317,7 @@ config VCO_MULT
range 1 64
default "22" if BFIN533_EZKIT
default "45" if BFIN533_STAMP
default "20" if (BFIN537_STAMP || BFIN527_EZKIT)
default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
default "22" if BFIN533_BLUETECHNIX_CM
default "20" if BFIN537_BLUETECHNIX_CM
default "20" if BFIN561_BLUETECHNIX_CM
@@ -354,7 +354,7 @@ config SCLK_DIV
range 1 15
default 5 if BFIN533_EZKIT
default 5 if BFIN533_STAMP
default 4 if (BFIN537_STAMP || BFIN527_EZKIT)
default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
default 5 if BFIN533_BLUETECHNIX_CM
default 4 if BFIN537_BLUETECHNIX_CM
default 4 if BFIN561_BLUETECHNIX_CM
@@ -409,6 +409,7 @@ config MEM_SIZE
default 32 if BFIN533_EZKIT
default 64 if BFIN527_EZKIT
default 64 if BFIN537_STAMP
default 64 if BFIN548_EZKIT
default 64 if BFIN561_EZKIT
default 128 if BFIN533_STAMP
default 64 if PNAV10
@@ -416,6 +417,7 @@ config MEM_SIZE
config MEM_ADD_WIDTH
int "SDRAM Memory Address Width"
depends on (!BF54x)
default 9 if BFIN533_EZKIT
default 9 if BFIN561_EZKIT
default 9 if H8606_HVSISTEMAS
@@ -424,6 +426,19 @@ config MEM_ADD_WIDTH
default 11 if BFIN533_STAMP
default 10 if PNAV10
choice
prompt "DDR SDRAM Chip Type"
depends on BFIN548_EZKIT
default MEM_MT46V32M16_5B
config MEM_MT46V32M16_6T
bool "MT46V32M16_6T"
config MEM_MT46V32M16_5B
bool "MT46V32M16_5B"
endchoice
config ENET_FLASH_PIN
int "PF port/pin used for flash and ethernet sharing"
depends on (BFIN533_STAMP)
arch/blackfin/mach-bf548/head.S
+47
View File
@@ -324,12 +324,25 @@ ENTRY(_start_dma_code)
w[p0] = r0.l;
ssync;
#if defined(CONFIG_BF54x)
P2.H = hi(EBIU_RSTCTL);
P2.L = lo(EBIU_RSTCTL);
R0 = [P2];
BITSET (R0, 3);
#else
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITSET (R0, 24);
#endif
[P2] = R0;
SSYNC;
#if defined(CONFIG_BF54x)
.LSRR_MODE:
R0 = [P2];
CC = BITTST(R0, 4);
if !CC JUMP .LSRR_MODE;
#endif
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
r0 = r0 << 9; /* Shift it over, */
@@ -361,6 +374,39 @@ ENTRY(_start_dma_code)
w[p0] = r0.l;
ssync;
#if defined(CONFIG_BF54x)
P2.H = hi(EBIU_RSTCTL);
P2.L = lo(EBIU_RSTCTL);
R0 = [P2];
CC = BITTST(R0, 0);
if CC jump .Lskipddrrst;
BITSET (R0, 0);
.Lskipddrrst:
BITCLR (R0, 3);
[P2] = R0;
SSYNC;
p0.l = lo(EBIU_DDRCTL0);
p0.h = hi(EBIU_DDRCTL0);
r0.l = lo(mem_DDRCTL0);
r0.h = hi(mem_DDRCTL0);
[p0] = r0;
ssync;
p0.l = lo(EBIU_DDRCTL1);
p0.h = hi(EBIU_DDRCTL1);
r0.l = lo(mem_DDRCTL1);
r0.h = hi(mem_DDRCTL1);
[p0] = r0;
ssync;
p0.l = lo(EBIU_DDRCTL2);
p0.h = hi(EBIU_DDRCTL2);
r0.l = lo(mem_DDRCTL2);
r0.h = hi(mem_DDRCTL2);
[p0] = r0;
ssync;
#else
p0.l = lo(EBIU_SDRRC);
p0.h = hi(EBIU_SDRRC);
r0 = mem_SDRRC;
@@ -394,6 +440,7 @@ ENTRY(_start_dma_code)
R1 = R1 | R0;
[P2] = R1;
SSYNC;
#endif
p0.h = hi(SIC_IWR0);
p0.l = lo(SIC_IWR0);