From 9b533dc8f340f5e9e7f2ed610510b2191d5e447c Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 29 Sep 2020 15:05:02 +0100 Subject: [PATCH 01/18] ARM: dts: r8a7742-iwg21d-q7: Add LCD support The iwg21d comes with a 7" capacitive touch screen, therefore add support for it. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20200929140502.16017-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 99 +++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index c2c05c9685d1..0063ef92f50e 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -30,6 +30,7 @@ /dts-v1/; #include "r8a7742-iwg21m.dtsi" +#include / { model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H"; @@ -52,6 +53,16 @@ clock-frequency = <26000000>; }; + lcd_backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&tpu 2 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + pinctrl-0 = <&backlight_pins>; + pinctrl-names = "default"; + default-brightness-level = <7>; + enable-gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; + }; + leds { compatible = "gpio-leds"; @@ -62,6 +73,41 @@ }; }; + lvds-receiver { + compatible = "ti,ds90cf384a", "lvds-decoder"; + power-supply = <&vcc_3v3_tft1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds_receiver_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + port@1 { + reg = <1>; + lvds_receiver_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + panel { + compatible = "edt,etm0700g0dh6"; + backlight = <&lcd_backlight>; + power-supply = <&vcc_3v3_tft1>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds_receiver_out>; + }; + }; + }; + reg_1p5v: 1p5v { compatible = "regulator-fixed"; regulator-name = "1P5V"; @@ -85,6 +131,17 @@ }; }; + vcc_3v3_tft1: regulator-panel { + compatible = "regulator-fixed"; + + regulator-name = "vcc-3v3-tft1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <500>; + gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>; + }; + vcc_sdhi2: regulator-vcc-sdhi2 { compatible = "regulator-fixed"; @@ -139,6 +196,16 @@ VDDIO-supply = <®_3p3v>; VDDD-supply = <®_1p5v>; }; + + touch: touchpanel@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&gpio0>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + /* GP1_29 is also shared with audio codec reset pin */ + reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + vcc-supply = <&vcc_3v3_tft1>; + }; }; &can1 { @@ -152,6 +219,18 @@ status = "okay"; }; +&du { + status = "okay"; +}; + +&gpio0 { + touch-interrupt { + gpio-hog; + gpios = <24 GPIO_ACTIVE_LOW>; + input; + }; +}; + &gpio1 { can-trx-en-gpio{ gpio-hog; @@ -167,6 +246,17 @@ status = "okay"; }; +&lvds0 { + status = "okay"; + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&lvds_receiver_in>; + }; + }; + }; +}; + &msiof0 { pinctrl-0 = <&msiof0_pins>; pinctrl-names = "default"; @@ -229,6 +319,11 @@ function = "avb"; }; + backlight_pins: backlight { + groups = "tpu0_to2"; + function = "tpu0"; + }; + can1_pins: can1 { groups = "can1_data_b"; function = "can1"; @@ -335,6 +430,10 @@ shared-pin; }; +&tpu { + status = "okay"; +}; + &usbphy { status = "okay"; }; From e8c471588890f9939b23d628e65b7dcb3a856f7a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 2 Oct 2020 18:39:45 +0200 Subject: [PATCH 02/18] arm64: dts: renesas: Align GPIO hog names with dtschema The convention for node names is to use hyphens, not underscores. dtschema for pca95xx expects GPIO hogs to end with 'hog' suffix. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201002163945.7885-1-krzk@kernel.org Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a77951-salvator-xs.dts | 2 +- .../boot/dts/renesas/r8a77965-salvator-xs.dts | 2 +- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 14 +++++++------- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts index cef9da4376a3..e5922329a4b8 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts @@ -118,7 +118,7 @@ }; &pca9654 { - pcie_sata_switch { + pcie-sata-switch-hog { gpio-hog; gpios = <7 GPIO_ACTIVE_HIGH>; output-low; /* enable SATA by default */ diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts index 5cef64605464..d7e621101af7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts @@ -55,7 +55,7 @@ }; &pca9654 { - pcie_sata_switch { + pcie-sata-switch-hog { gpio-hog; gpios = <7 GPIO_ACTIVE_HIGH>; output-low; /* enable SATA by default */ diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 202177706cde..e9ed2597f1c2 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -143,49 +143,49 @@ interrupt-parent = <&gpio6>; interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - audio_out_off { + audio-out-off-hog { gpio-hog; gpios = <0 GPIO_ACTIVE_HIGH>; /* P00 */ output-high; line-name = "Audio_Out_OFF"; }; - hub_pwen { + hub-pwen-hog { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; output-high; line-name = "HUB pwen"; }; - hub_rst { + hub-rst-hog { gpio-hog; gpios = <7 GPIO_ACTIVE_HIGH>; output-high; line-name = "HUB rst"; }; - otg_extlpn { + otg-extlpn-hog { gpio-hog; gpios = <9 GPIO_ACTIVE_HIGH>; output-high; line-name = "OTG EXTLPn"; }; - otg_offvbusn { + otg-offvbusn-hog { gpio-hog; gpios = <8 GPIO_ACTIVE_HIGH>; output-low; line-name = "OTG OFFVBUSn"; }; - sd-wifi-mux { + sd-wifi-mux-hog { gpio-hog; gpios = <5 GPIO_ACTIVE_HIGH>; output-low; /* Connect WL1837 */ line-name = "SD WiFi mux"; }; - snd_rst { + snd-rst-hog { gpio-hog; gpios = <15 GPIO_ACTIVE_HIGH>; /* P17 */ output-high; From ca3b4330a5437d877e9b0093ba8b746e73695fb0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 5 Oct 2020 13:29:51 +0200 Subject: [PATCH 03/18] arm64: dts: renesas: r8a77961: Add MSIOF nodes Add the device nodes for all Clock-Synchronized Serial Interface with FIFO (MSIOF) instances on R-Car M3-W+. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201005112951.22532-1-geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 62 +++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 1ba30313c8b8..b0c4b8150d37 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1187,6 +1187,68 @@ status = "disabled"; }; + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a77961", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a77961", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a77961", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a77961", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + vin0: video@e6ef0000 { reg = <0 0xe6ef0000 0 0x1000>; /* placeholder */ From d311d818fa8cfa791d05de9e03b0d9babfc82dd2 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 14 Oct 2020 15:55:58 +0100 Subject: [PATCH 04/18] ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Enable VIN instances Enable VIN instances along with OV5640 as endpoints on the adapter board. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20201014145558.12854-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts | 222 ++++++++++++++++++ 1 file changed, 222 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts index 961c0f2eeefb..98c3fbd89fa6 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts @@ -20,6 +20,30 @@ serial5 = &hscif0; ethernet1 = ðer; }; + + mclk_cam1: mclk-cam1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + mclk_cam2: mclk-cam2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + mclk_cam3: mclk-cam3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + mclk_cam4: mclk-cam4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; }; &avb { @@ -47,6 +71,19 @@ }; }; +&gpio0 { + /* Disable hogging GP0_18 to output LOW */ + /delete-node/ qspi_en; + + /* Hog GP0_18 to output HIGH to enable VIN2 */ + vin2_en { + gpio-hog; + gpios = <18 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "VIN2_EN"; + }; +}; + &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; @@ -54,6 +91,94 @@ status = "okay"; }; +&i2c0 { + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&mclk_cam1>; + clock-names = "xclk"; + + port { + ov5640_0: endpoint { + bus-width = <8>; + data-shift = <2>; + bus-type = <6>; + pclk-sample = <1>; + remote-endpoint = <&vin0ep>; + }; + }; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&mclk_cam2>; + clock-names = "xclk"; + + port { + ov5640_1: endpoint { + bus-width = <8>; + data-shift = <2>; + bus-type = <6>; + pclk-sample = <1>; + remote-endpoint = <&vin1ep>; + }; + }; + }; +}; + +&i2c2 { + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&mclk_cam3>; + clock-names = "xclk"; + + port { + ov5640_2: endpoint { + bus-width = <8>; + data-shift = <2>; + bus-type = <6>; + pclk-sample = <1>; + remote-endpoint = <&vin2ep>; + }; + }; + }; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&mclk_cam4>; + clock-names = "xclk"; + + port { + ov5640_3: endpoint { + bus-width = <8>; + data-shift = <2>; + bus-type = <6>; + pclk-sample = <1>; + remote-endpoint = <&vin3ep>; + }; + }; + }; +}; + &pfc { can0_pins: can0 { groups = "can0_data_d"; @@ -70,6 +195,16 @@ function = "hscif0"; }; + i2c1_pins: i2c1 { + groups = "i2c1_c"; + function = "i2c1"; + }; + + i2c3_pins: i2c3 { + groups = "i2c3"; + function = "i2c3"; + }; + scif0_pins: scif0 { groups = "scif0_data"; function = "scif0"; @@ -84,6 +219,31 @@ groups = "scifb1_data"; function = "scifb1"; }; + + vin0_8bit_pins: vin0 { + groups = "vin0_data8", "vin0_clk", "vin0_sync"; + function = "vin0"; + }; + + vin1_8bit_pins: vin1 { + groups = "vin1_data8_b", "vin1_clk_b", "vin1_sync_b"; + function = "vin1"; + }; + + vin2_pins: vin2 { + groups = "vin2_g8", "vin2_clk"; + function = "vin2"; + }; + + vin3_pins: vin3 { + groups = "vin3_data8", "vin3_clk", "vin3_sync"; + function = "vin3"; + }; +}; + +&qspi { + /* Pins shared with VIN2, keep status disabled */ + status = "disabled"; }; &scif0 { @@ -106,3 +266,65 @@ rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; }; + +&vin0 { + /* + * Set SW2 switch on the SOM to 'ON' + * Set SW1 switch on camera board to 'OFF' as we are using 8bit mode + */ + status = "okay"; + pinctrl-0 = <&vin0_8bit_pins>; + pinctrl-names = "default"; + + port { + vin0ep: endpoint { + remote-endpoint = <&ov5640_0>; + bus-width = <8>; + bus-type = <6>; + }; + }; +}; + +&vin1 { + /* Set SW1 switch on the SOM to 'ON' */ + status = "okay"; + pinctrl-0 = <&vin1_8bit_pins>; + pinctrl-names = "default"; + + port { + vin1ep: endpoint { + remote-endpoint = <&ov5640_1>; + bus-width = <8>; + bus-type = <6>; + }; + }; +}; + +&vin2 { + status = "okay"; + pinctrl-0 = <&vin2_pins>; + pinctrl-names = "default"; + + port { + vin2ep: endpoint { + remote-endpoint = <&ov5640_2>; + bus-width = <8>; + data-shift = <8>; + bus-type = <6>; + }; + }; +}; + +&vin3 { + status = "okay"; + pinctrl-0 = <&vin3_pins>; + pinctrl-names = "default"; + + port { + vin3ep: endpoint { + remote-endpoint = <&ov5640_3>; + bus-width = <8>; + bus-type = <6>; + }; + }; +}; From 67d3dcf12a3d245b6fd6ca5672893f7ae4e137ed Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 15 Oct 2020 14:23:49 +0100 Subject: [PATCH 05/18] arm64: dts: renesas: hihope-rzg2-ex: Drop rxc-skew-ps from ethernet-phy node HiHope RZG2[HMN] boards uses Realtek phy and the driver does not support rxc-skew-ps property. So remove rxc-skew-ps from ethernet-phy node. Fixes: 7433f1fb8ec8fe ("arm64: dts: renesas: Add HiHope RZ/G2M sub board support") Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20201015132350.8360-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi index 178401a34cbf..b9e46aed5336 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi @@ -23,7 +23,6 @@ status = "okay"; phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; reg = <0>; interrupt-parent = <&gpio2>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; From 53e573dc39fba1834f3e4fa002cb754b61a30701 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 15 Oct 2020 14:23:50 +0100 Subject: [PATCH 06/18] arm64: dts: renesas: cat875: Remove rxc-skew-ps from ethernet-phy node The CAT875 sub board from Silicon Linux uses Realtek phy and the driver does not support rxc-skew-ps property. Fixes: 6b170cd3ed02949f ("arm64: dts: renesas: cat875: Add ethernet support") Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20201015132350.8360-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/cat875.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi index 33daa9570684..801ea54b027c 100644 --- a/arch/arm64/boot/dts/renesas/cat875.dtsi +++ b/arch/arm64/boot/dts/renesas/cat875.dtsi @@ -21,7 +21,6 @@ status = "okay"; phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; reg = <0>; interrupt-parent = <&gpio2>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; From 622007d172fbb1d7556329bafd72dc28c0baf1b8 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 20 Oct 2020 13:51:31 +0100 Subject: [PATCH 07/18] arm64: dts: renesas: aistarvision-mipi-adapter-2.1: Add parent macro for each sensor For HiHope RZ/G2H the OV5645 sensor is populated on i2c2 whereas the imx219 sensor is populated on i2c3 so add support for handling such cases by adding a parent macro for each sensor. Also update r8a774c0-ek874-mipi-2.1.dts to incorporate the changes. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20201020125134.22625-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi | 4 +++- arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts | 3 ++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi b/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi index dac6ff49020f..7ce986f0a06f 100644 --- a/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi +++ b/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi @@ -61,7 +61,7 @@ }; }; -&MIPI_PARENT_I2C { +&MIPI_OV5645_PARENT_I2C { ov5645: ov5645@3c { compatible = "ovti,ov5645"; reg = <0x3c>; @@ -77,7 +77,9 @@ }; }; }; +}; +&MIPI_IMX219_PARENT_I2C { imx219: imx219@10 { compatible = "sony,imx219"; reg = <0x10>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts index f0829e905506..e7b4a929bb17 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts +++ b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts @@ -8,7 +8,8 @@ /dts-v1/; #include "r8a774c0-ek874.dts" -#define MIPI_PARENT_I2C i2c3 +#define MIPI_OV5645_PARENT_I2C i2c3 +#define MIPI_IMX219_PARENT_I2C i2c3 #include "aistarvision-mipi-adapter-2.1.dtsi" / { From 05e6ae33cf9834dd2f0ff35001828ca09fe5af26 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 20 Oct 2020 13:51:32 +0100 Subject: [PATCH 08/18] arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to HiHope RZ/G2H MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for AISTARVISION MIPI Adapter V2.1 board connected to HiHope RZ/G2H board. Common file hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi is created which will be used by RZ/G2{HMN}, by default the CSI20 node is tied to ov5645 camera endpoint and the imx219 camera endpoint is tied to CSI40. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Acked-by: Niklas Söderlund Link: https://lore.kernel.org/r/20201020125134.22625-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + ...rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi | 109 ++++++++++++++++++ .../r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts | 16 +++ 3 files changed, 126 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index dffefe030a76..f98e9e2e520d 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-mipi-2.1.dtb dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-idk-1110wr.dtb +dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-mipi-2.1.dtb dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-salvator-x.dtb dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi new file mode 100644 index 000000000000..c62ddb9b2ba5 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2[HMN] MIPI common parts + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#define MIPI_OV5645_PARENT_I2C i2c2 +#define MIPI_IMX219_PARENT_I2C i2c3 +#include "aistarvision-mipi-adapter-2.1.dtsi" + +&csi20 { + status = "okay"; + + ports { + port@0 { + reg = <0>; + csi20_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&ov5645_ep>; + }; + }; + }; +}; + +&csi40 { + status = "okay"; + + ports { + port@0 { + reg = <0>; + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&imx219_ep>; + }; + }; + }; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&imx219 { + port { + imx219_ep: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <456000000>; + remote-endpoint = <&csi40_in>; + }; + }; +}; + +&ov5645 { + enable-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; + + port { + ov5645_ep: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&csi20_in>; + }; + }; +}; + +&pfc { + i2c3_pins: i2c3 { + groups = "i2c3"; + function = "i2c3"; + }; +}; + +&vin0 { + status = "okay"; +}; + +&vin1 { + status = "okay"; +}; + +&vin2 { + status = "okay"; +}; + +&vin3 { + status = "okay"; +}; + +&vin4 { + status = "okay"; +}; + +&vin5 { + status = "okay"; +}; + +&vin6 { + status = "okay"; +}; + +&vin7 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts new file mode 100644 index 000000000000..46adb6efb5e6 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2H board + * connected with aistarvision-mipi-v2-adapter board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774e1-hihope-rzg2h-ex.dts" +#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2H with sub board connected with aistarvision-mipi-v2-adapter board"; + compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1"; +}; From 661495164934e15bc8a192f8eafa1ec9655e74f0 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 20 Oct 2020 13:51:33 +0100 Subject: [PATCH 09/18] arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to HiHope RZ/G2M Add support for AISTARVISION MIPI Adapter V2.1 board connected to HiHope RZ/G2M board. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20201020125134.22625-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts | 29 +++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index f98e9e2e520d..ca095c7e8ee1 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-beacon-rzg2m-kit.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb +dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-mipi-2.1.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts new file mode 100644 index 000000000000..5c91e0d7e67b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2M board + * connected with aistarvision-mipi-v2-adapter board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774a1-hihope-rzg2m-ex.dts" +#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2M with sub board connected with aistarvision-mipi-v2-adapter board"; + compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1"; +}; + +/* + * On RZ/G2M SoC LSI V1.3 CSI40 supports only 4 lane mode. + * HiHope RZ/G2M Rev.4.0 board is based on LSI V1.3 so disable csi40 and + * imx219 as the imx219 endpoint driver supports only 2 lane mode. + */ +&csi40 { + status = "disabled"; +}; + +&imx219 { + status = "disabled"; +}; From bdf0c8ea8c63d9e288ff06fc300e2eb8bd332d1c Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 20 Oct 2020 13:51:34 +0100 Subject: [PATCH 10/18] arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to HiHope RZ/G2N Add support for AISTARVISION MIPI Adapter V2.1 board connected to HiHope RZ/G2N board. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20201020125134.22625-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index ca095c7e8ee1..2b043b59c669 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb +dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-mipi-2.1.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts new file mode 100644 index 000000000000..ce8e3bcc7dc9 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2N board + * connected with aistarvision-mipi-v2-adapter board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774b1-hihope-rzg2n-ex.dts" +#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2N with sub board connected with aistarvision-mipi-v2-adapter board"; + compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1"; +}; From 92494cea405fd2136033c70abd6abf6739b12a2f Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 21 Oct 2020 14:53:32 +0100 Subject: [PATCH 11/18] arm64: dts: renesas: r8a77965: Add DRIF support Add the DRIF controller nodes for r8a77965 (a.k.a. R-Car M3-N). Signed-off-by: Fabrizio Castro Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20201021135332.4928-6-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 120 ++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index c355460e5f7f..d098eb3ec73a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1550,6 +1550,126 @@ }; }; + drif00: rif@e6f40000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f40000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 515>; + clock-names = "fck"; + dmas = <&dmac1 0x20>, <&dmac2 0x20>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 515>; + renesas,bonding = <&drif01>; + status = "disabled"; + }; + + drif01: rif@e6f50000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f50000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 514>; + clock-names = "fck"; + dmas = <&dmac1 0x22>, <&dmac2 0x22>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 514>; + renesas,bonding = <&drif00>; + status = "disabled"; + }; + + drif10: rif@e6f60000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f60000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 513>; + clock-names = "fck"; + dmas = <&dmac1 0x24>, <&dmac2 0x24>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 513>; + renesas,bonding = <&drif11>; + status = "disabled"; + }; + + drif11: rif@e6f70000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f70000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 512>; + clock-names = "fck"; + dmas = <&dmac1 0x26>, <&dmac2 0x26>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 512>; + renesas,bonding = <&drif10>; + status = "disabled"; + }; + + drif20: rif@e6f80000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f80000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 511>; + clock-names = "fck"; + dmas = <&dmac1 0x28>, <&dmac2 0x28>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 511>; + renesas,bonding = <&drif21>; + status = "disabled"; + }; + + drif21: rif@e6f90000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f90000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 510>; + clock-names = "fck"; + dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 510>; + renesas,bonding = <&drif20>; + status = "disabled"; + }; + + drif30: rif@e6fa0000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fa0000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 509>; + clock-names = "fck"; + dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 509>; + renesas,bonding = <&drif31>; + status = "disabled"; + }; + + drif31: rif@e6fb0000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fb0000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 508>; + clock-names = "fck"; + dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 508>; + renesas,bonding = <&drif30>; + status = "disabled"; + }; + rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required From 9b81018185965a306158b471db75ba0aca90ec9f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 19 Aug 2020 15:43:43 +0200 Subject: [PATCH 12/18] arm64: dts: renesas: rcar-gen3: Convert EtherAVB to explicit delay handling Some EtherAVB variants support internal clock delay configuration, which can add larger delays than the delays that are typically supported by the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps" properties). Historically, the EtherAVB driver configured these delays based on the "rgmii-*id" PHY mode. This was wrong, as these are meant solely for the PHY, not for the MAC. Hence properties were introduced for explicit configuration of these delays. Convert the R-Car Gen3 DTS files from the old to the new scheme: - Add default "rx-internal-delay-ps" and "tx-internal-delay-ps" properties to the SoC .dtsi files, to be overridden by board files where needed, - Convert board files from "rgmii-*id" PHY modes to "rgmii", adding the appropriate "rx-internal-delay-ps" and/or "tx-internal-delay-ps" overrides. Notes: - R-Car E3 and D3 do not support TX internal delay handling, - On R-Car D3, TX internal delay handling must always be enabled, hence this fixes a bug on Draak, - On R-Car V3H, RX internal delay handling must always be enabled. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200819134344.27813-7-geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a77960.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a77961.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 3 ++- arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 3 ++- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77995.dtsi | 1 + arch/arm64/boot/dts/renesas/salvator-common.dtsi | 2 +- arch/arm64/boot/dts/renesas/ulcb.dtsi | 2 +- 12 files changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 18ce0face72b..644308dd886c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -1250,6 +1250,8 @@ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index f379c8d1511d..53b9aa26c9b1 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -1126,6 +1126,8 @@ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index b0c4b8150d37..9266c60f21fa 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1012,6 +1012,8 @@ power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index d098eb3ec73a..4a913df17b1d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -988,6 +988,8 @@ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index 5c28f303e911..874a7fc2730b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -81,7 +81,8 @@ renesas,no-ether-link; phy-handle = <&phy0>; - phy-mode = "rgmii-id"; + rx-internal-delay-ps = <1800>; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index 668a1ece9af0..7417cf5fea0f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -102,7 +102,8 @@ renesas,no-ether-link; phy-handle = <&phy0>; - phy-mode = "rgmii-id"; + rx-internal-delay-ps = <1800>; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index baf8cc821564..5a5d5649332a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -615,6 +615,8 @@ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_rt 3>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index d6cae90d7fd9..ec7ca72399ec 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -667,6 +667,8 @@ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <2000>; iommus = <&ipmmu_ds1 33>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 33d7e657bd9c..87d41bc076a9 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -938,6 +938,7 @@ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index cd7ca9774196..e1af7c4782f4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -628,6 +628,7 @@ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <1800>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 1bf77957d2c2..6c643ed74fc5 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -324,7 +324,7 @@ pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; phy-handle = <&phy0>; - phy-mode = "rgmii-txid"; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index a2e085db87c5..8f8d7371d8e2 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -144,7 +144,7 @@ pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; phy-handle = <&phy0>; - phy-mode = "rgmii-txid"; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { From a5200e63af57d05ed8bf0ffd9a6ffefc40e01e89 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 19 Aug 2020 15:43:44 +0200 Subject: [PATCH 13/18] arm64: dts: renesas: rzg2: Convert EtherAVB to explicit delay handling Some EtherAVB variants support internal clock delay configuration, which can add larger delays than the delays that are typically supported by the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps" properties). Historically, the EtherAVB driver configured these delays based on the "rgmii-*id" PHY mode. This was wrong, as these are meant solely for the PHY, not for the MAC. Hence properties were introduced for explicit configuration of these delays. Convert the RZ/G2 DTS files from the old to the new scheme: - Add default "rx-internal-delay-ps" and "tx-internal-delay-ps" properties to the SoC .dtsi files, to be overridden by board files where needed, - Convert board files from "rgmii-*id" PHY modes to "rgmii", adding the appropriate "rx-internal-delay-ps" and/or "tx-internal-delay-ps" overrides. Notes: - RZ/G2E does not support TX internal delay handling. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200819134344.27813-8-geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 3 ++- arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 2 ++ 6 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 97272f5fa0ab..8ac167aa18f0 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -55,7 +55,8 @@ pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; phy-handle = <&phy0>; - phy-mode = "rgmii-id"; + rx-internal-delay-ps = <1800>; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi index b9e46aed5336..202c4fc88bd5 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi @@ -19,7 +19,7 @@ pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; phy-handle = <&phy0>; - phy-mode = "rgmii-txid"; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index c15f1c571eb0..d37ec42a1caa 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1115,6 +1115,8 @@ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 39a1a26ffb54..83523916d360 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -989,6 +989,8 @@ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index f27d9b2eb996..e0e54342cd4c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -960,6 +960,7 @@ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 9cbf963aa068..31ae3530cf3d 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1212,6 +1212,8 @@ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; From a511d8be4ea4c59b7eb2c65bd787b7bb90350893 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 20 Sep 2020 14:49:04 +0100 Subject: [PATCH 14/18] arm64: dts: renesas: cat874: Move connector node out of hd3ss3220 device Move connector node out of hd3ss3220 device in order to comply with usb connector bindings. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20200920134905.4370-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a774c0-cat874.dts | 67 ++++++++++++++----- 1 file changed, 50 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts index 26aee004a44e..ea87cb5a459c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts +++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts @@ -129,6 +129,29 @@ #clock-cells = <0>; clock-frequency = <74250000>; }; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hs_ep: endpoint { + remote-endpoint = <&usb3_hs_ep>; + }; + }; + port@1 { + reg = <1>; + ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; }; &audio_clk_a { @@ -186,20 +209,19 @@ interrupt-parent = <&gpio6>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - hd3ss3220_ep: endpoint { - remote-endpoint = <&usb3_role_switch>; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + port@1 { + reg = <1>; + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb3_role_switch>; }; }; }; @@ -405,9 +427,20 @@ status = "okay"; usb-role-switch; - port { - usb3_role_switch: endpoint { - remote-endpoint = <&hd3ss3220_ep>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + usb3_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + port@1 { + reg = <1>; + usb3_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; }; }; }; From ca8edef172109821aa100763e38d6d8d49bcdf56 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 20 Sep 2020 14:49:05 +0100 Subject: [PATCH 15/18] arm64: dts: renesas: beacon-renesom-baseboard: Move connector node out of hd3ss3220 device Move connector node out of hd3ss3220 device in order to comply with usb connector bindings. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20200920134905.4370-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/beacon-renesom-baseboard.dtsi | 67 ++++++++++++++----- 1 file changed, 50 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index 66c9153b3101..e66b5b36e489 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -223,6 +223,29 @@ #clock-cells = <0>; clock-frequency = <25000000>; }; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hs_ep: endpoint { + remote-endpoint = <&usb3_hs_ep>; + }; + }; + port@1 { + reg = <1>; + ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; }; &audio_clk_a { @@ -427,20 +450,19 @@ interrupt-parent = <&gpio6>; interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - hd3ss3220_ep: endpoint { - remote-endpoint = <&usb3_role_switch>; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + port@1 { + reg = <1>; + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb3_role_switch>; }; }; }; @@ -714,9 +736,20 @@ status = "okay"; usb-role-switch; - port { - usb3_role_switch: endpoint { - remote-endpoint = <&hd3ss3220_ep>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + usb3_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + port@1 { + reg = <1>; + usb3_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; }; }; }; From f8a1620cb59bbf5d2706290ab2de7021f4eece7c Mon Sep 17 00:00:00 2001 From: Eugeniu Rosca Date: Thu, 29 Oct 2020 14:37:40 +0100 Subject: [PATCH 16/18] arm64: dts: renesas: r8a77961: Add CAN{0,1} placeholder nodes With the same background and purpose as described in v4.20-rc1 commit 92bc66bfce99cd ("arm64: dts: renesas: r8a77965: Add CAN{0,1} placeholder nodes"), add can0 and can1 placeholder nodes. Signed-off-by: Eugeniu Rosca Link: https://lore.kernel.org/r/20201029133741.25721-1-erosca@de.adit-jv.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 9266c60f21fa..4b737c616257 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1019,6 +1019,16 @@ status = "disabled"; }; + can0: can@e6c30000 { + reg = <0 0xe6c30000 0 0x1000>; + /* placeholder */ + }; + + can1: can@e6c38000 { + reg = <0 0xe6c38000 0 0x1000>; + /* placeholder */ + }; + pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 8>; From dd8ecc02743cc337ab56014448bacaa763c33074 Mon Sep 17 00:00:00 2001 From: Eugeniu Rosca Date: Thu, 29 Oct 2020 14:37:41 +0100 Subject: [PATCH 17/18] arm64: dts: renesas: r8a77961: ulcb-kf: Initial device tree Create a dedicated DTB for M3-ES3.0 + ULCB + Kingfisher combo. Inspire from the pre-existing ULCB-KF device trees: $ ls -1 arch/arm64/boot/dts/renesas/*ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a77950-ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a77951-ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a77960-ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a77965-ulcb-kf.dts Signed-off-by: Eugeniu Rosca Link: https://lore.kernel.org/r/20201029133741.25721-2-erosca@de.adit-jv.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 2b043b59c669..3b8b03705917 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb.dtb +dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts new file mode 100644 index 000000000000..6ec958348eb0 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the M3ULCB Kingfisher board + * + * Copyright (C) 2020 Eugeniu Rosca + */ + +#include "r8a77961-ulcb.dts" +#include "ulcb-kf.dtsi" + +/ { + model = "Renesas M3ULCB Kingfisher board based on r8a77961"; + compatible = "shimafuji,kingfisher", "renesas,m3ulcb", + "renesas,r8a77961"; +}; From 43bba65761952f58e850d918ee43b648427609bb Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 5 Nov 2020 12:11:27 +0000 Subject: [PATCH 18/18] arm64: dts: renesas: hihope-rev4: Add a comment explaining switch SW2404 Switch SW2404 should be at position 1 so that the clock output from CS2000 is connected to AUDIO_CLKB_A. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20201105121127.11830-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/hihope-rev4.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi index 3046c07a288b..929f4a1d3f90 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi @@ -91,7 +91,11 @@ #clock-cells = <1>; clock-frequency = <12288000 11289600>; - /* update to */ + /* + * Update to + * Switch SW2404 should be at position 1 so that clock from + * CS2000 is connected to AUDIO_CLKB_A + */ clocks = <&cpg CPG_MOD 1005>, <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,