Merge tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linux
Pull clock framework updates from Mike Turquette: "The common clock framework changes for 3.11 include new clock drivers across several different platforms and architectures, fixes to existing drivers, a MAINTAINERS file fix and improvements to the basic clock types that allow them to be of use to more platforms than before. Only a few fixes to the core framework are included with most all of the changes landing in the various clock drivers themselves." * tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linux: (55 commits) clk: tegra: fix ifdef for tegra_periph_reset_assert inline clk: tegra: provide tegra_periph_reset_assert alternative clk: exynos4: Fix clock aliases for cpufreq related clocks clk: samsung: Add MUX_FA macro to pass flag and alias clk: add support for Rockchip gate clocks clk: vexpress: Make the clock drivers directly available for arm64 clk: vexpress: Use full node name to identify individual clocks clk: tegra: T114: add DFLL DVCO reset control clk: tegra: T114: add DFLL source clocks clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL clk: gate: add CLK_GATE_HIWORD_MASK clk: divider: add CLK_DIVIDER_HIWORD_MASK flag clk: mux: add CLK_MUX_HIWORD_MASK clk: Always notify whole subtree when reparenting MAINTAINERS: make drivers/clk entry match subdirs clk: honor CLK_GET_RATE_NOCACHE in clk_set_rate clk: use clk_get_rate() for debugfs clk: tegra: Use override bits when needed clk: tegra: override bits for Tegra30 PLLM clk: tegra: override bits for Tegra114 PLLM ...
This commit is contained in:
Linus Torvalds
@@ -210,6 +210,10 @@ void of_fixed_clk_setup(struct device_node *np);
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* CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
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* enable the clock. Setting this flag does the opposite: setting the bit
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* disable the clock and clearing it enables the clock
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* CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
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* of this register, and mask of gate bits are in higher 16-bit of this
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* register. While setting the gate bits, higher 16-bit should also be
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* updated to indicate changing gate bits.
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*/
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struct clk_gate {
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struct clk_hw hw;
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@@ -220,6 +224,7 @@ struct clk_gate {
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};
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#define CLK_GATE_SET_TO_DISABLE BIT(0)
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#define CLK_GATE_HIWORD_MASK BIT(1)
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extern const struct clk_ops clk_gate_ops;
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struct clk *clk_register_gate(struct device *dev, const char *name,
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@@ -257,6 +262,10 @@ struct clk_div_table {
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* Some hardware implementations gracefully handle this case and allow a
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* zero divisor by not modifying their input clock
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* (divide by one / bypass).
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* CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
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* of this register, and mask of divider bits are in higher 16-bit of this
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* register. While setting the divider bits, higher 16-bit should also be
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* updated to indicate changing divider bits.
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*/
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struct clk_divider {
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struct clk_hw hw;
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@@ -271,6 +280,7 @@ struct clk_divider {
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#define CLK_DIVIDER_ONE_BASED BIT(0)
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#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
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#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
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#define CLK_DIVIDER_HIWORD_MASK BIT(3)
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extern const struct clk_ops clk_divider_ops;
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struct clk *clk_register_divider(struct device *dev, const char *name,
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@@ -299,6 +309,10 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
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* Flags:
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* CLK_MUX_INDEX_ONE - register index starts at 1, not 0
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* CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
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* CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
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* register, and mask of mux bits are in higher 16-bit of this register.
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* While setting the mux bits, higher 16-bit should also be updated to
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* indicate changing mux bits.
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*/
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struct clk_mux {
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struct clk_hw hw;
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@@ -312,6 +326,7 @@ struct clk_mux {
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#define CLK_MUX_INDEX_ONE BIT(0)
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#define CLK_MUX_INDEX_BIT BIT(1)
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#define CLK_MUX_HIWORD_MASK BIT(2)
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extern const struct clk_ops clk_mux_ops;
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@@ -423,6 +438,17 @@ struct of_device_id;
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typedef void (*of_clk_init_cb_t)(struct device_node *);
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struct clk_onecell_data {
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struct clk **clks;
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unsigned int clk_num;
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};
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#define CLK_OF_DECLARE(name, compat, fn) \
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static const struct of_device_id __clk_of_table_##name \
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__used __section(__clk_of_table) \
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= { .compatible = compat, .data = fn };
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#ifdef CONFIG_OF
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int of_clk_add_provider(struct device_node *np,
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struct clk *(*clk_src_get)(struct of_phandle_args *args,
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void *data),
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@@ -430,19 +456,39 @@ int of_clk_add_provider(struct device_node *np,
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void of_clk_del_provider(struct device_node *np);
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struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
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void *data);
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struct clk_onecell_data {
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struct clk **clks;
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unsigned int clk_num;
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};
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struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
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const char *of_clk_get_parent_name(struct device_node *np, int index);
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void of_clk_init(const struct of_device_id *matches);
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#define CLK_OF_DECLARE(name, compat, fn) \
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static const struct of_device_id __clk_of_table_##name \
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__used __section(__clk_of_table) \
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= { .compatible = compat, .data = fn };
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#else /* !CONFIG_OF */
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static inline int of_clk_add_provider(struct device_node *np,
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struct clk *(*clk_src_get)(struct of_phandle_args *args,
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void *data),
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void *data)
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{
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return 0;
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}
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#define of_clk_del_provider(np) \
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{ while (0); }
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static inline struct clk *of_clk_src_simple_get(
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struct of_phandle_args *clkspec, void *data)
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{
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return ERR_PTR(-ENOENT);
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}
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static inline struct clk *of_clk_src_onecell_get(
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struct of_phandle_args *clkspec, void *data)
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{
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return ERR_PTR(-ENOENT);
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}
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static inline const char *of_clk_get_parent_name(struct device_node *np,
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int index)
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{
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return NULL;
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}
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#define of_clk_init(matches) \
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{ while (0); }
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#endif /* CONFIG_OF */
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#endif /* CONFIG_COMMON_CLK */
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#endif /* CLK_PROVIDER_H */
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@@ -120,9 +120,13 @@ static inline void tegra_cpu_clock_resume(void)
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}
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#endif
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#ifdef CONFIG_ARCH_TEGRA
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void tegra_periph_reset_deassert(struct clk *c);
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void tegra_periph_reset_assert(struct clk *c);
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void tegra_clocks_init(void);
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#else
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static inline void tegra_periph_reset_deassert(struct clk *c) {}
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static inline void tegra_periph_reset_assert(struct clk *c) {}
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#endif
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void tegra_clocks_apply_init_table(void);
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#endif /* __LINUX_CLK_TEGRA_H_ */
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@@ -278,8 +278,8 @@ struct ab8500_sysctrl_platform_data {
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#define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0)
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#define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1)
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#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_MASK 0x0C
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#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_SHIFT 2
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#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL0 BIT(2)
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#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL1 BIT(3)
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#define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4)
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#define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5)
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#define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6)
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@@ -134,6 +134,11 @@ enum prcmu_clock {
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PRCMU_SIACLK,
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PRCMU_SVACLK,
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PRCMU_ACLK,
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PRCMU_HVACLK, /* Ux540 only */
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PRCMU_G1CLK, /* Ux540 only */
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PRCMU_SDMMCHCLK,
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PRCMU_CAMCLK,
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PRCMU_BML8580CLK,
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PRCMU_NUM_REG_CLOCKS,
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PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
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PRCMU_CDCLK,
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@@ -148,6 +153,13 @@ enum prcmu_clock {
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PRCMU_DSI0ESCCLK,
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PRCMU_DSI1ESCCLK,
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PRCMU_DSI2ESCCLK,
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/* LCD DSI PLL - Ux540 only */
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PRCMU_PLLDSI_LCD,
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PRCMU_DSI0CLK_LCD,
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PRCMU_DSI1CLK_LCD,
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PRCMU_DSI0ESCCLK_LCD,
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PRCMU_DSI1ESCCLK_LCD,
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PRCMU_DSI2ESCCLK_LCD,
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};
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/**
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@@ -12,7 +12,9 @@
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void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
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u32 clkrst5_base, u32 clkrst6_base);
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void u9540_clk_init(void);
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void u8540_clk_init(void);
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void u9540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
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u32 clkrst5_base, u32 clkrst6_base);
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void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
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u32 clkrst5_base, u32 clkrst6_base);
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#endif /* __CLK_UX500_H */
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@@ -78,6 +78,23 @@ enum si5351_drive_strength {
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SI5351_DRIVE_8MA = 8,
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};
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/**
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* enum si5351_disable_state - Si5351 clock output disable state
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* @SI5351_DISABLE_DEFAULT: default, do not change eeprom config
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* @SI5351_DISABLE_LOW: CLKx is set to a LOW state when disabled
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* @SI5351_DISABLE_HIGH: CLKx is set to a HIGH state when disabled
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* @SI5351_DISABLE_FLOATING: CLKx is set to a FLOATING state when
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* disabled
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* @SI5351_DISABLE_NEVER: CLKx is NEVER disabled
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*/
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enum si5351_disable_state {
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SI5351_DISABLE_DEFAULT = 0,
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SI5351_DISABLE_LOW,
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SI5351_DISABLE_HIGH,
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SI5351_DISABLE_FLOATING,
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SI5351_DISABLE_NEVER,
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};
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/**
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* struct si5351_clkout_config - Si5351 clock output configuration
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* @clkout: clkout number
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@@ -91,6 +108,7 @@ struct si5351_clkout_config {
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enum si5351_multisynth_src multisynth_src;
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enum si5351_clkout_src clkout_src;
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enum si5351_drive_strength drive;
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enum si5351_disable_state disable_state;
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bool pll_master;
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unsigned long rate;
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};
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