Merge tag 'drm-misc-next-2021-07-22' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for v5.15-rc1: UAPI Changes: - Remove sysfs stats for dma-buf attachments, as it causes a performance regression. Previous merge is not in a rc kernel yet, so no userspace regression possible. Cross-subsystem Changes: - Sanitize user input in kyro's viewport ioctl. - Use refcount_t in fb_info->count - Assorted fixes to dma-buf. - Extend x86 efifb handling to all archs. - Fix neofb divide by 0. - Document corpro,gm7123 bridge dt bindings. Core Changes: - Slightly rework drm master handling. - Cleanup vgaarb handling. - Assorted fixes. Driver Changes: - Add support for ws2401 panel. - Assorted fixes to stm, ast, bochs. - Demidlayer ingenic irq. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2d0d2fe8-01fc-e216-c3fd-38db9e69944e@linux.intel.com
This commit is contained in:
Dave Airlie
@@ -38,6 +38,9 @@ extern "C" {
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#define DRM_V3D_GET_BO_OFFSET 0x05
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#define DRM_V3D_SUBMIT_TFU 0x06
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#define DRM_V3D_SUBMIT_CSD 0x07
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#define DRM_V3D_PERFMON_CREATE 0x08
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#define DRM_V3D_PERFMON_DESTROY 0x09
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#define DRM_V3D_PERFMON_GET_VALUES 0x0a
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#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
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#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
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@@ -47,6 +50,12 @@ extern "C" {
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#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
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#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
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#define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
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#define DRM_IOCTL_V3D_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, \
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struct drm_v3d_perfmon_create)
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#define DRM_IOCTL_V3D_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, \
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struct drm_v3d_perfmon_destroy)
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#define DRM_IOCTL_V3D_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, \
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struct drm_v3d_perfmon_get_values)
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#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
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@@ -127,6 +136,11 @@ struct drm_v3d_submit_cl {
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__u32 bo_handle_count;
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__u32 flags;
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/* ID of the perfmon to attach to this job. 0 means no perfmon. */
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__u32 perfmon_id;
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__u32 pad;
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};
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/**
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@@ -195,6 +209,7 @@ enum drm_v3d_param {
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DRM_V3D_PARAM_SUPPORTS_TFU,
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DRM_V3D_PARAM_SUPPORTS_CSD,
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DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
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DRM_V3D_PARAM_SUPPORTS_PERFMON,
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};
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struct drm_v3d_get_param {
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@@ -258,6 +273,127 @@ struct drm_v3d_submit_csd {
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__u32 in_sync;
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/* Sync object to signal when the CSD job is done. */
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__u32 out_sync;
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/* ID of the perfmon to attach to this job. 0 means no perfmon. */
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__u32 perfmon_id;
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};
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enum {
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V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS,
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V3D_PERFCNT_FEP_VALID_PRIMS,
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V3D_PERFCNT_FEP_EZ_NFCLIP_QUADS,
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V3D_PERFCNT_FEP_VALID_QUADS,
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V3D_PERFCNT_TLB_QUADS_STENCIL_FAIL,
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V3D_PERFCNT_TLB_QUADS_STENCILZ_FAIL,
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V3D_PERFCNT_TLB_QUADS_STENCILZ_PASS,
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V3D_PERFCNT_TLB_QUADS_ZERO_COV,
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V3D_PERFCNT_TLB_QUADS_NONZERO_COV,
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V3D_PERFCNT_TLB_QUADS_WRITTEN,
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V3D_PERFCNT_PTB_PRIM_VIEWPOINT_DISCARD,
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V3D_PERFCNT_PTB_PRIM_CLIP,
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V3D_PERFCNT_PTB_PRIM_REV,
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V3D_PERFCNT_QPU_IDLE_CYCLES,
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V3D_PERFCNT_QPU_ACTIVE_CYCLES_VERTEX_COORD_USER,
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V3D_PERFCNT_QPU_ACTIVE_CYCLES_FRAG,
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V3D_PERFCNT_QPU_CYCLES_VALID_INSTR,
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V3D_PERFCNT_QPU_CYCLES_TMU_STALL,
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V3D_PERFCNT_QPU_CYCLES_SCOREBOARD_STALL,
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V3D_PERFCNT_QPU_CYCLES_VARYINGS_STALL,
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V3D_PERFCNT_QPU_IC_HIT,
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V3D_PERFCNT_QPU_IC_MISS,
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V3D_PERFCNT_QPU_UC_HIT,
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V3D_PERFCNT_QPU_UC_MISS,
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V3D_PERFCNT_TMU_TCACHE_ACCESS,
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V3D_PERFCNT_TMU_TCACHE_MISS,
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V3D_PERFCNT_VPM_VDW_STALL,
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V3D_PERFCNT_VPM_VCD_STALL,
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V3D_PERFCNT_BIN_ACTIVE,
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V3D_PERFCNT_RDR_ACTIVE,
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V3D_PERFCNT_L2T_HITS,
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V3D_PERFCNT_L2T_MISSES,
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V3D_PERFCNT_CYCLE_COUNT,
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V3D_PERFCNT_QPU_CYCLES_STALLED_VERTEX_COORD_USER,
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V3D_PERFCNT_QPU_CYCLES_STALLED_FRAGMENT,
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V3D_PERFCNT_PTB_PRIMS_BINNED,
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V3D_PERFCNT_AXI_WRITES_WATCH_0,
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V3D_PERFCNT_AXI_READS_WATCH_0,
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V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_0,
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V3D_PERFCNT_AXI_READ_STALLS_WATCH_0,
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V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_0,
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V3D_PERFCNT_AXI_READ_BYTES_WATCH_0,
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V3D_PERFCNT_AXI_WRITES_WATCH_1,
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V3D_PERFCNT_AXI_READS_WATCH_1,
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V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_1,
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V3D_PERFCNT_AXI_READ_STALLS_WATCH_1,
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V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_1,
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V3D_PERFCNT_AXI_READ_BYTES_WATCH_1,
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V3D_PERFCNT_TLB_PARTIAL_QUADS,
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V3D_PERFCNT_TMU_CONFIG_ACCESSES,
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V3D_PERFCNT_L2T_NO_ID_STALL,
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V3D_PERFCNT_L2T_COM_QUE_STALL,
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V3D_PERFCNT_L2T_TMU_WRITES,
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V3D_PERFCNT_TMU_ACTIVE_CYCLES,
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V3D_PERFCNT_TMU_STALLED_CYCLES,
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V3D_PERFCNT_CLE_ACTIVE,
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V3D_PERFCNT_L2T_TMU_READS,
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V3D_PERFCNT_L2T_CLE_READS,
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V3D_PERFCNT_L2T_VCD_READS,
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V3D_PERFCNT_L2T_TMUCFG_READS,
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V3D_PERFCNT_L2T_SLC0_READS,
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V3D_PERFCNT_L2T_SLC1_READS,
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V3D_PERFCNT_L2T_SLC2_READS,
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V3D_PERFCNT_L2T_TMU_W_MISSES,
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V3D_PERFCNT_L2T_TMU_R_MISSES,
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V3D_PERFCNT_L2T_CLE_MISSES,
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V3D_PERFCNT_L2T_VCD_MISSES,
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V3D_PERFCNT_L2T_TMUCFG_MISSES,
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V3D_PERFCNT_L2T_SLC0_MISSES,
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V3D_PERFCNT_L2T_SLC1_MISSES,
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V3D_PERFCNT_L2T_SLC2_MISSES,
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V3D_PERFCNT_CORE_MEM_WRITES,
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V3D_PERFCNT_L2T_MEM_WRITES,
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V3D_PERFCNT_PTB_MEM_WRITES,
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V3D_PERFCNT_TLB_MEM_WRITES,
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V3D_PERFCNT_CORE_MEM_READS,
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V3D_PERFCNT_L2T_MEM_READS,
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V3D_PERFCNT_PTB_MEM_READS,
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V3D_PERFCNT_PSE_MEM_READS,
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V3D_PERFCNT_TLB_MEM_READS,
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V3D_PERFCNT_GMP_MEM_READS,
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V3D_PERFCNT_PTB_W_MEM_WORDS,
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V3D_PERFCNT_TLB_W_MEM_WORDS,
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V3D_PERFCNT_PSE_R_MEM_WORDS,
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V3D_PERFCNT_TLB_R_MEM_WORDS,
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V3D_PERFCNT_TMU_MRU_HITS,
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V3D_PERFCNT_COMPUTE_ACTIVE,
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V3D_PERFCNT_NUM,
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};
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#define DRM_V3D_MAX_PERF_COUNTERS 32
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struct drm_v3d_perfmon_create {
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__u32 id;
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__u32 ncounters;
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__u8 counters[DRM_V3D_MAX_PERF_COUNTERS];
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};
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struct drm_v3d_perfmon_destroy {
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__u32 id;
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};
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/*
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* Returns the values of the performance counters tracked by this
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* perfmon (as an array of ncounters u64 values).
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*
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* No implicit synchronization is performed, so the user has to
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* guarantee that any jobs using this perfmon have already been
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* completed (probably by blocking on the seqno returned by the
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* last exec that used the perfmon).
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*/
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struct drm_v3d_perfmon_get_values {
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__u32 id;
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__u32 pad;
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__u64 values_ptr;
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};
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#if defined(__cplusplus)
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