gpu: ipu-v3: Add ipu-cpmem unit
Move channel parameter memory setup functions and macros into a new submodule ipu-cpmem. In the process, cleanup arguments to the functions to take a channel pointer instead of a pointer into cpmem for that channel. That allows the structure of the parameter memory to be private to ipu-cpmem.c. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
This commit is contained in:
Steve Longerbeam
committed by
Philipp Zabel
Philipp Zabel
parent
7d1311b93e
commit
7d2691da90
+36
-152
@@ -107,6 +107,42 @@ void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
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int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
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void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
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/*
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* IPU Channel Parameter Memory (cpmem) functions
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*/
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struct ipu_rgb {
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struct fb_bitfield red;
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struct fb_bitfield green;
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struct fb_bitfield blue;
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struct fb_bitfield transp;
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int bits_per_pixel;
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};
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struct ipu_image {
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struct v4l2_pix_format pix;
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struct v4l2_rect rect;
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dma_addr_t phys;
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};
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void ipu_cpmem_zero(struct ipuv3_channel *ch);
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void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
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void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
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void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
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void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
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void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
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void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
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int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
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const struct ipu_rgb *rgb);
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int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
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void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
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void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
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u32 pixel_format, int stride,
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int u_offset, int v_offset);
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void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
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u32 pixel_format, int stride, int height);
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int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
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int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
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/*
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* IPU Display Controller (dc) functions
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*/
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@@ -180,161 +216,9 @@ int ipu_smfc_disable(struct ipu_soc *ipu);
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int ipu_smfc_map_channel(struct ipu_soc *ipu, int channel, int csi_id, int mipi_id);
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int ipu_smfc_set_burstsize(struct ipu_soc *ipu, int channel, int burstsize);
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#define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size))
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#define IPU_FIELD_UBO IPU_CPMEM_WORD(0, 46, 22)
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#define IPU_FIELD_VBO IPU_CPMEM_WORD(0, 68, 22)
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#define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4)
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#define IPU_FIELD_RDRW IPU_CPMEM_WORD(0, 94, 1)
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#define IPU_FIELD_SO IPU_CPMEM_WORD(0, 113, 1)
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#define IPU_FIELD_SLY IPU_CPMEM_WORD(1, 102, 14)
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#define IPU_FIELD_SLUV IPU_CPMEM_WORD(1, 128, 14)
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#define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10)
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#define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 9)
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#define IPU_FIELD_XB IPU_CPMEM_WORD(0, 19, 13)
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#define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12)
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#define IPU_FIELD_NSB_B IPU_CPMEM_WORD(0, 44, 1)
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#define IPU_FIELD_CF IPU_CPMEM_WORD(0, 45, 1)
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#define IPU_FIELD_SX IPU_CPMEM_WORD(0, 46, 12)
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#define IPU_FIELD_SY IPU_CPMEM_WORD(0, 58, 11)
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#define IPU_FIELD_NS IPU_CPMEM_WORD(0, 69, 10)
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#define IPU_FIELD_SDX IPU_CPMEM_WORD(0, 79, 7)
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#define IPU_FIELD_SM IPU_CPMEM_WORD(0, 86, 10)
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#define IPU_FIELD_SCC IPU_CPMEM_WORD(0, 96, 1)
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#define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 97, 1)
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#define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 7)
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#define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 105, 1)
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#define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 106, 1)
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#define IPU_FIELD_BPP IPU_CPMEM_WORD(0, 107, 3)
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#define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(0, 110, 2)
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#define IPU_FIELD_DIM IPU_CPMEM_WORD(0, 112, 1)
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#define IPU_FIELD_BNDM IPU_CPMEM_WORD(0, 114, 3)
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#define IPU_FIELD_BM IPU_CPMEM_WORD(0, 117, 2)
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#define IPU_FIELD_ROT IPU_CPMEM_WORD(0, 119, 1)
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#define IPU_FIELD_HF IPU_CPMEM_WORD(0, 120, 1)
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#define IPU_FIELD_VF IPU_CPMEM_WORD(0, 121, 1)
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#define IPU_FIELD_THE IPU_CPMEM_WORD(0, 122, 1)
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#define IPU_FIELD_CAP IPU_CPMEM_WORD(0, 123, 1)
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#define IPU_FIELD_CAE IPU_CPMEM_WORD(0, 124, 1)
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#define IPU_FIELD_FW IPU_CPMEM_WORD(0, 125, 13)
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#define IPU_FIELD_FH IPU_CPMEM_WORD(0, 138, 12)
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#define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 29)
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#define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 29, 29)
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#define IPU_FIELD_ILO IPU_CPMEM_WORD(1, 58, 20)
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#define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 78, 7)
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#define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4)
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#define IPU_FIELD_ALU IPU_CPMEM_WORD(1, 89, 1)
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#define IPU_FIELD_ALBM IPU_CPMEM_WORD(1, 90, 3)
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#define IPU_FIELD_ID IPU_CPMEM_WORD(1, 93, 2)
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#define IPU_FIELD_TH IPU_CPMEM_WORD(1, 95, 7)
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#define IPU_FIELD_SL IPU_CPMEM_WORD(1, 102, 14)
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#define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 116, 3)
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#define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 119, 3)
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#define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 122, 3)
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#define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 125, 3)
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#define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 128, 5)
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#define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 133, 5)
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#define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 138, 5)
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#define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 143, 5)
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#define IPU_FIELD_SXYS IPU_CPMEM_WORD(1, 148, 1)
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#define IPU_FIELD_CRE IPU_CPMEM_WORD(1, 149, 1)
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#define IPU_FIELD_DEC_SEL2 IPU_CPMEM_WORD(1, 150, 1)
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struct ipu_cpmem_word {
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u32 data[5];
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u32 res[3];
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};
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struct ipu_ch_param {
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struct ipu_cpmem_word word[2];
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};
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void ipu_ch_param_write_field(struct ipu_ch_param __iomem *base, u32 wbs, u32 v);
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u32 ipu_ch_param_read_field(struct ipu_ch_param __iomem *base, u32 wbs);
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struct ipu_ch_param __iomem *ipu_get_cpmem(struct ipuv3_channel *channel);
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void ipu_ch_param_dump(struct ipu_ch_param __iomem *p);
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static inline void ipu_ch_param_zero(struct ipu_ch_param __iomem *p)
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{
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int i;
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void __iomem *base = p;
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for (i = 0; i < sizeof(*p) / sizeof(u32); i++)
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writel(0, base + i * sizeof(u32));
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}
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static inline void ipu_cpmem_set_buffer(struct ipu_ch_param __iomem *p,
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int bufnum, dma_addr_t buf)
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{
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if (bufnum)
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ipu_ch_param_write_field(p, IPU_FIELD_EBA1, buf >> 3);
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else
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ipu_ch_param_write_field(p, IPU_FIELD_EBA0, buf >> 3);
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}
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static inline void ipu_cpmem_set_resolution(struct ipu_ch_param __iomem *p,
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int xres, int yres)
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{
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ipu_ch_param_write_field(p, IPU_FIELD_FW, xres - 1);
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ipu_ch_param_write_field(p, IPU_FIELD_FH, yres - 1);
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}
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static inline void ipu_cpmem_set_stride(struct ipu_ch_param __iomem *p,
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int stride)
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{
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ipu_ch_param_write_field(p, IPU_FIELD_SLY, stride - 1);
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}
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void ipu_cpmem_set_high_priority(struct ipuv3_channel *channel);
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struct ipu_rgb {
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struct fb_bitfield red;
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struct fb_bitfield green;
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struct fb_bitfield blue;
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struct fb_bitfield transp;
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int bits_per_pixel;
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};
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struct ipu_image {
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struct v4l2_pix_format pix;
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struct v4l2_rect rect;
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dma_addr_t phys;
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};
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int ipu_cpmem_set_format_passthrough(struct ipu_ch_param __iomem *p,
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int width);
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int ipu_cpmem_set_format_rgb(struct ipu_ch_param __iomem *,
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const struct ipu_rgb *rgb);
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static inline void ipu_cpmem_interlaced_scan(struct ipu_ch_param *p,
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int stride)
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{
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ipu_ch_param_write_field(p, IPU_FIELD_SO, 1);
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ipu_ch_param_write_field(p, IPU_FIELD_ILO, stride / 8);
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ipu_ch_param_write_field(p, IPU_FIELD_SLY, (stride * 2) - 1);
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};
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void ipu_cpmem_set_yuv_planar(struct ipu_ch_param __iomem *p, u32 pixel_format,
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int stride, int height);
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void ipu_cpmem_set_yuv_interleaved(struct ipu_ch_param __iomem *p,
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u32 pixel_format);
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void ipu_cpmem_set_yuv_planar_full(struct ipu_ch_param __iomem *p,
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u32 pixel_format, int stride, int u_offset, int v_offset);
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int ipu_cpmem_set_fmt(struct ipu_ch_param __iomem *cpmem, u32 pixelformat);
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int ipu_cpmem_set_image(struct ipu_ch_param __iomem *cpmem,
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struct ipu_image *image);
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enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
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enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
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static inline void ipu_cpmem_set_burstsize(struct ipu_ch_param __iomem *p,
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int burstsize)
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{
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ipu_ch_param_write_field(p, IPU_FIELD_NPB, burstsize - 1);
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};
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struct ipu_client_platformdata {
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int csi;
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int di;
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