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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6

Browse Source 
Conflicts:

	drivers/net/wireless/iwlwifi/iwl-4965-rs.c
	drivers/net/wireless/rt2x00/rt61pci.c
This commit is contained in:
David S. Miller
2008-05-15 00:34:44 -07:00
parent 99dd1a2b83 066b211897
commit 63fe46da9c
980 changed files with 25435 additions and 13014 deletions
Download Patch File Download Diff File Expand all files Collapse all files
include/asm-alpha/barrier.h
+1 -1
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@@ -24,7 +24,7 @@ __asm__ __volatile__("mb": : :"memory")
#define smp_mb() barrier()
#define smp_rmb() barrier()
#define smp_wmb() barrier()
#define smp_read_barrier_depends() barrier()
#define smp_read_barrier_depends() do { } while (0)
#endif
#define set_mb(var, value) \
include/asm-alpha/param.h
+4
View File
@@ -5,8 +5,12 @@
hardware ignores reprogramming. We also need userland buy-in to the
change in HZ, since this is visible in the wait4 resources etc. */
#ifdef __KERNEL__
#define HZ CONFIG_HZ
#define USER_HZ HZ
#else
#define HZ 1024
#endif
#define EXEC_PAGESIZE 8192
include/asm-alpha/pgtable.h
+19 -2
View File
@@ -287,17 +287,34 @@ extern inline pte_t pte_mkspecial(pte_t pte) { return pte; }
#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
/*
* The smp_read_barrier_depends() in the following functions are required to
* order the load of *dir (the pointer in the top level page table) with any
* subsequent load of the returned pmd_t *ret (ret is data dependent on *dir).
*
* If this ordering is not enforced, the CPU might load an older value of
* *ret, which may be uninitialized data. See mm/memory.c:__pte_alloc for
* more details.
*
* Note that we never change the mm->pgd pointer after the task is running, so
* pgd_offset does not require such a barrier.
*/
/* Find an entry in the second-level page table.. */
extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
{
return (pmd_t *) pgd_page_vaddr(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1));
pmd_t *ret = (pmd_t *) pgd_page_vaddr(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1));
smp_read_barrier_depends(); /* see above */
return ret;
}
/* Find an entry in the third-level page table.. */
extern inline pte_t * pte_offset_kernel(pmd_t * dir, unsigned long address)
{
return (pte_t *) pmd_page_vaddr(*dir)
pte_t *ret = (pte_t *) pmd_page_vaddr(*dir)
+ ((address >> PAGE_SHIFT) & (PTRS_PER_PAGE - 1));
smp_read_barrier_depends(); /* see above */
return ret;
}
#define pte_offset_map(dir,addr) pte_offset_kernel((dir),(addr))
include/asm-arm/arch-pxa/pm.h
+1 -1
View File
@@ -10,7 +10,7 @@
#include <linux/suspend.h>
struct pxa_cpu_pm_fns {
int save_size;
int save_count;
void (*save)(unsigned long *);
void (*restore)(unsigned long *);
int (*valid)(suspend_state_t state);
include/asm-arm/arch-pxa/system.h
+2 -1
View File
@@ -22,7 +22,8 @@ static inline void arch_idle(void)
static inline void arch_reset(char mode)
{
RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
if (cpu_is_pxa2xx())
RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
if (mode == 's') {
/* Jump into ROM at address 0 */
include/asm-blackfin/dpmc.h
+9 -1
View File
@@ -1,7 +1,7 @@
/*
* include/asm-blackfin/dpmc.h - Miscellaneous IOCTL commands for Dynamic Power
* Management Controller Driver.
* Copyright (C) 2004 Analog Device Inc.
* Copyright (C) 2004-2008 Analog Device Inc.
*
*/
#ifndef _BLACKFIN_DPMC_H_
@@ -65,6 +65,14 @@ void disable_wdog_timer(void);
extern unsigned long get_cclk(void);
extern unsigned long get_sclk(void);
struct bfin_dpmc_platform_data {
const unsigned int *tuple_tab;
unsigned short tabsize;
unsigned short vr_settling_time; /* in us */
};
#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
#endif /* __KERNEL__ */
#endif /*_BLACKFIN_DPMC_H_*/
include/asm-blackfin/entry.h
+5
View File
@@ -17,6 +17,11 @@
#define PF_DTRACE_OFF 1
#define PF_DTRACE_BIT 5
/*
* NOTE! The single-stepping code assumes that all interrupt handlers
* start by saving SYSCFG on the stack with their first instruction.
*/
/* This one is used for exceptions, emulation, and NMI. It doesn't push
RETI and doesn't do cli. */
#define SAVE_ALL_SYS save_context_no_interrupts
include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
+5
View File
@@ -44,10 +44,15 @@
#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS
include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+5
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@@ -44,10 +44,15 @@
#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
#ifdef CONFIG_BFIN_UART0_CTSRTS
# define CONFIG_SERIAL_BFIN_CTSRTS
# ifndef CONFIG_UART0_CTS_PIN
include/asm-blackfin/mach-bf533/defBF532.h
+2
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@@ -468,6 +468,8 @@
#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
include/asm-blackfin/mach-bf533/irq.h
+6 -8
View File
@@ -66,12 +66,13 @@ Core Emulation **
DMA8/9 Interrupt IVG13 28
DMA10/11 Interrupt IVG13 29
Watchdog Timer IVG13 30
Software Interrupt 1 IVG14 31
Software Interrupt 2 --
Softirq IVG14 31
System Call --
(lowest priority) IVG15 32 *
*/
#define SYS_IRQS 32
#define NR_PERI_INTS 24
#define SYS_IRQS 31
#define NR_PERI_INTS 24
/* The ABSTRACT IRQ definitions */
/** the first seven of the following are fixed, the rest you change if you need to **/
@@ -96,7 +97,7 @@ Core Emulation **
#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
#define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */
#define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */
#define IRQ_TMR0 23 /*Timer 0 */
@@ -108,9 +109,6 @@ Core Emulation **
#define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */
#define IRQ_WATCH 30 /*Watch Dog Timer */
#define IRQ_SW_INT1 31 /*Software Int 1 */
#define IRQ_SW_INT2 32 /*Software Int 2 (reserved for SYSCALL) */
#define IRQ_PF0 33
#define IRQ_PF1 34
#define IRQ_PF2 35
include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
+5
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@@ -44,10 +44,15 @@
#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS
include/asm-blackfin/mach-bf537/irq.h
+16 -19
View File
@@ -34,24 +34,23 @@
/*
* Interrupt source definitions
Event Source Core Event Name
Core Emulation **
Events (highest priority) EMU 0
Reset RST 1
NMI NMI 2
Exception EVX 3
Reserved -- 4
Hardware Error IVHW 5
Core Timer IVTMR 6 *
.....
Software Interrupt 1 IVG14 31
Software Interrupt 2 --
(lowest priority) IVG15 32 *
* Event Source Core Event Name
* Core Emulation **
* Events (highest priority) EMU 0
* Reset RST 1
* NMI NMI 2
* Exception EVX 3
* Reserved -- 4
* Hardware Error IVHW 5
* Core Timer IVTMR 6
* .....
*
* Softirq IVG14
* System Call --
* (lowest priority) IVG15
*/
#define SYS_IRQS 41
#define SYS_IRQS 39
#define NR_PERI_INTS 32
/* The ABSTRACT IRQ definitions */
@@ -95,10 +94,8 @@ Core Emulation **
#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */
#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */
#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
#define IRQ_WATCH 38 /*Watch Dog Timer */
#define IRQ_SW_INT1 40 /*Software Int 1 */
#define IRQ_SW_INT2 41 /*Software Int 2 (reserved for SYSCALL) */
#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */
#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */
include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+3
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@@ -54,6 +54,9 @@
#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
#define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */
#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS
include/asm-blackfin/mach-bf548/defBF54x_base.h
+20
View File
@@ -2329,6 +2329,26 @@
#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
#define GAIN_5 0x0000 /* GAIN = 5*/
#define GAIN_10 0x0004 /* GAIN = 1*/
#define GAIN_20 0x0008 /* GAIN = 2*/
#define GAIN_50 0x000C /* GAIN = 5*/
#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
/* Bit masks for NFC_CTL */
#define WR_DLY 0xf /* Write Strobe Delay */
include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+5
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@@ -44,10 +44,15 @@
#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
#ifdef CONFIG_BFIN_UART0_CTSRTS
# define CONFIG_SERIAL_BFIN_CTSRTS
# ifndef CONFIG_UART0_CTS_PIN
include/asm-blackfin/mach-bf561/defBF561.h
+28
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@@ -868,6 +868,34 @@
#define CHIPID_FAMILY 0x0FFFF000
#define CHIPID_MANUFACTURE 0x00000FFE
/* VR_CTL Masks */
#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
#define GAIN 0x000C /* Voltage Level Gain */
#define GAIN_5 0x0000 /* GAIN = 5*/
#define GAIN_10 0x0004 /* GAIN = 1*/
#define GAIN_20 0x0008 /* GAIN = 2*/
#define GAIN_50 0x000C /* GAIN = 5*/
#define VLEV 0x00F0 /* Internal Voltage Level */
#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
/* PLL_DIV Masks */
#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
include/asm-blackfin/mach-bf561/irq.h
+6 -7
View File
@@ -118,12 +118,13 @@
Supplemental interrupt 0 IVG7 69
supplemental interrupt 1 IVG7 70
Software Interrupt 1 IVG14 71
Software Interrupt 2 IVG15 72 *
(lowest priority)
Softirq IVG14
System Call --
(lowest priority) IVG15
**********************************************************************/
#define SYS_IRQS 72
#define SYS_IRQS 71
#define NR_PERI_INTS 64
/*
@@ -237,9 +238,7 @@
#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */
#define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */
#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */
#define IRQ_SW_INT1 71 /* Software Interrupt 1 */
#define IRQ_SW_INT2 72 /* Software Interrupt 2 */
/* reserved for SYSCALL */
#define IRQ_PF0 73
#define IRQ_PF1 74
#define IRQ_PF2 75
include/asm-blackfin/mach-common/context.S
+5
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@@ -27,6 +27,11 @@
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
* NOTE! The single-stepping code assumes that all interrupt handlers
* start by saving SYSCFG on the stack with their first instruction.
*/
/*
* Code to save processor context.
* We even save the register which are preserved by a function call
include/asm-blackfin/time.h
+4
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@@ -24,6 +24,8 @@
#ifndef CONFIG_CPU_FREQ
#define TIME_SCALE 1
#define __bfin_cycles_off (0)
#define __bfin_cycles_mod (0)
#else
/*
* Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
@@ -31,6 +33,8 @@
* adjust the Core Timer Presale Register. This way we don't lose time.
*/
#define TIME_SCALE 4
extern unsigned long long __bfin_cycles_off;
extern unsigned int __bfin_cycles_mod;
#endif
#endif
include/asm-frv/system.h
+1 -1
View File
@@ -179,7 +179,7 @@ do { \
#define mb() asm volatile ("membar" : : :"memory")
#define rmb() asm volatile ("membar" : : :"memory")
#define wmb() asm volatile ("membar" : : :"memory")
#define read_barrier_depends() barrier()
#define read_barrier_depends() do { } while (0)
#ifdef CONFIG_SMP
#define smp_mb() mb()
include/asm-h8300/param.h
+3 -5
View File
@@ -1,14 +1,12 @@
#ifndef _H8300_PARAM_H
#define _H8300_PARAM_H
#ifndef HZ
#define HZ CONFIG_HZ
#endif
#ifdef __KERNEL__
#define HZ CONFIG_HZ
#define USER_HZ HZ
#define CLOCKS_PER_SEC (USER_HZ)
#else
#define HZ 100
#endif
#define EXEC_PAGESIZE 4096
include/asm-m68k/machw.h
-30
View File
@@ -66,36 +66,6 @@ struct MAC_SCC
# define mac_scc ((*(volatile struct SCC*)MAC_SCC_BAS))
#endif
/* hardware stuff */
#define MACHW_DECLARE(name) unsigned name : 1
#define MACHW_SET(name) (mac_hw_present.name = 1)
#define MACHW_PRESENT(name) (mac_hw_present.name)
struct mac_hw_present {
/* video hardware */
/* sound hardware */
/* disk storage interfaces */
MACHW_DECLARE(MAC_SCSI_80); /* Directly mapped NCR5380 */
MACHW_DECLARE(MAC_SCSI_96); /* 53c9[46] */
MACHW_DECLARE(MAC_SCSI_96_2); /* 2nd 53c9[46] Q900 and Q950 */
MACHW_DECLARE(IDE); /* IDE Interface */
/* other I/O hardware */
MACHW_DECLARE(SCC); /* Serial Communications Contr. */
/* DMA */
MACHW_DECLARE(SCSI_DMA); /* DMA for the NCR5380 */
/* real time clocks */
MACHW_DECLARE(RTC_CLK); /* clock chip */
/* supporting hardware */
MACHW_DECLARE(VIA1); /* Versatile Interface Ad. 1 */
MACHW_DECLARE(VIA2); /* Versatile Interface Ad. 2 */
MACHW_DECLARE(RBV); /* Versatile Interface Ad. 2+ */
/* NUBUS */
MACHW_DECLARE(NUBUS); /* NUBUS */
};
extern struct mac_hw_present mac_hw_present;
#endif /* __ASSEMBLY__ */
#endif /* linux/machw.h */
include/asm-mips/bitops.h
+5 -9
View File
@@ -558,11 +558,13 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *
__clear_bit(nr, addr);
}
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
/*
* Return the bit position (0..63) of the most significant 1 bit in a word
* Returns -1 if no 1 bit exists
*/
static inline int __ilog2(unsigned long x)
static inline unsigned long __fls(unsigned long x)
{
int lz;
@@ -591,13 +593,6 @@ static inline int __ilog2(unsigned long x)
return 63 - lz;
}
static inline unsigned long __fls(unsigned long x)
{
return __ilog2(x);
}
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
/*
* __ffs - find first bit in word.
* @word: The word to search
@@ -607,7 +602,7 @@ static inline unsigned long __fls(unsigned long x)
*/
static inline unsigned long __ffs(unsigned long word)
{
return __ilog2(word & -word);
return __fls(word & -word);
}
/*
@@ -654,6 +649,7 @@ static inline int ffs(int word)
#else
#include <asm-generic/bitops/__ffs.h>
#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/ffs.h>
#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/fls64.h>
include/asm-mips/compiler.h
+2 -2
View File
@@ -9,10 +9,10 @@
#define _ASM_COMPILER_H
#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
#define GCC_IMM_ASM "n"
#define GCC_IMM_ASM() "n"
#define GCC_REG_ACCUM "$0"
#else
#define GCC_IMM_ASM "rn"
#define GCC_IMM_ASM() "rn"
#define GCC_REG_ACCUM "accum"
#endif
include/asm-mips/mach-au1x00/au1000.h
+809 -813
View File
File diff suppressed because it is too large Load Diff
include/asm-mips/mach-au1x00/au1000_dma.h
+94 -81
View File
@@ -1,11 +1,10 @@
/*
* BRIEF MODULE DESCRIPTION
* Defines for using and allocating dma channels on the Alchemy
* Au1000 mips processor.
* Defines for using and allocating DMA channels on the Alchemy
* Au1x00 MIPS processors.
*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* stevel@mvista.com or source@mvista.com
* Copyright 2000, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -31,7 +30,7 @@
#ifndef __ASM_AU1000_DMA_H
#define __ASM_AU1000_DMA_H
#include <asm/io.h> /* need byte IO */
#include <linux/io.h> /* need byte IO */
#include <linux/spinlock.h> /* And spinlocks */
#include <linux/delay.h>
#include <asm/system.h>
@@ -50,36 +49,36 @@
#define DMA_DAH_MASK (0x0f << 20)
#define DMA_DID_BIT 16
#define DMA_DID_MASK (0x0f << DMA_DID_BIT)
#define DMA_DS (1<<15)
#define DMA_BE (1<<13)
#define DMA_DR (1<<12)
#define DMA_TS8 (1<<11)
#define DMA_DS (1 << 15)
#define DMA_BE (1 << 13)
#define DMA_DR (1 << 12)
#define DMA_TS8 (1 << 11)
#define DMA_DW_BIT 9
#define DMA_DW_MASK (0x03 << DMA_DW_BIT)
#define DMA_DW8 (0 << DMA_DW_BIT)
#define DMA_DW16 (1 << DMA_DW_BIT)
#define DMA_DW32 (2 << DMA_DW_BIT)
#define DMA_NC (1<<8)
#define DMA_IE (1<<7)
#define DMA_HALT (1<<6)
#define DMA_GO (1<<5)
#define DMA_AB (1<<4)
#define DMA_D1 (1<<3)
#define DMA_BE1 (1<<2)
#define DMA_D0 (1<<1)
#define DMA_BE0 (1<<0)
#define DMA_NC (1 << 8)
#define DMA_IE (1 << 7)
#define DMA_HALT (1 << 6)
#define DMA_GO (1 << 5)
#define DMA_AB (1 << 4)
#define DMA_D1 (1 << 3)
#define DMA_BE1 (1 << 2)
#define DMA_D0 (1 << 1)
#define DMA_BE0 (1 << 0)
#define DMA_PERIPHERAL_ADDR 0x00000008
#define DMA_BUFFER0_START 0x0000000C
#define DMA_BUFFER1_START 0x00000014
#define DMA_BUFFER0_COUNT 0x00000010
#define DMA_BUFFER1_COUNT 0x00000018
#define DMA_BAH_BIT 16
#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
#define DMA_COUNT_BIT 0
#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
#define DMA_PERIPHERAL_ADDR 0x00000008
#define DMA_BUFFER0_START 0x0000000C
#define DMA_BUFFER1_START 0x00000014
#define DMA_BUFFER0_COUNT 0x00000010
#define DMA_BUFFER1_COUNT 0x00000018
#define DMA_BAH_BIT 16
#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
#define DMA_COUNT_BIT 0
#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
/* DMA Device ID's follow */
/* DMA Device IDs follow */
enum {
DMA_ID_UART0_TX = 0,
DMA_ID_UART0_RX,
@@ -110,7 +109,8 @@ enum {
};
struct dma_chan {
int dev_id; // this channel is allocated if >=0, free otherwise
int dev_id; /* this channel is allocated if >= 0, */
/* free otherwise */
unsigned int io;
const char *dev_str;
int irq;
@@ -132,23 +132,23 @@ extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
extern void dump_au1000_dma_channel(unsigned int dmanr);
extern spinlock_t au1000_dma_spin_lock;
static __inline__ struct dma_chan *get_dma_chan(unsigned int dmanr)
static inline struct dma_chan *get_dma_chan(unsigned int dmanr)
{
if (dmanr >= NUM_AU1000_DMA_CHANNELS
|| au1000_dma_table[dmanr].dev_id < 0)
if (dmanr >= NUM_AU1000_DMA_CHANNELS ||
au1000_dma_table[dmanr].dev_id < 0)
return NULL;
return &au1000_dma_table[dmanr];
}
static __inline__ unsigned long claim_dma_lock(void)
static inline unsigned long claim_dma_lock(void)
{
unsigned long flags;
spin_lock_irqsave(&au1000_dma_spin_lock, flags);
return flags;
}
static __inline__ void release_dma_lock(unsigned long flags)
static inline void release_dma_lock(unsigned long flags)
{
spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
}
@@ -156,48 +156,53 @@ static __inline__ void release_dma_lock(unsigned long flags)
/*
* Set the DMA buffer enable bits in the mode register.
*/
static __inline__ void enable_dma_buffer0(unsigned int dmanr)
static inline void enable_dma_buffer0(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(DMA_BE0, chan->io + DMA_MODE_SET);
}
static __inline__ void enable_dma_buffer1(unsigned int dmanr)
static inline void enable_dma_buffer1(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(DMA_BE1, chan->io + DMA_MODE_SET);
}
static __inline__ void enable_dma_buffers(unsigned int dmanr)
static inline void enable_dma_buffers(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
}
static __inline__ void start_dma(unsigned int dmanr)
static inline void start_dma(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(DMA_GO, chan->io + DMA_MODE_SET);
}
#define DMA_HALT_POLL 0x5000
static __inline__ void halt_dma(unsigned int dmanr)
static inline void halt_dma(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
int i;
if (!chan)
return;
au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
// poll the halt bit
/* Poll the halt bit */
for (i = 0; i < DMA_HALT_POLL; i++)
if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
break;
@@ -205,55 +210,57 @@ static __inline__ void halt_dma(unsigned int dmanr)
printk(KERN_INFO "halt_dma: HALT poll expired!\n");
}
static __inline__ void disable_dma(unsigned int dmanr)
static inline void disable_dma(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
halt_dma(dmanr);
// now we can disable the buffers
/* Now we can disable the buffers */
au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
}
static __inline__ int dma_halted(unsigned int dmanr)
static inline int dma_halted(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return 1;
return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
}
/* initialize a DMA channel */
static __inline__ void init_dma(unsigned int dmanr)
/* Initialize a DMA channel. */
static inline void init_dma(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
u32 mode;
if (!chan)
return;
disable_dma(dmanr);
// set device FIFO address
au_writel(CPHYSADDR(chan->fifo_addr),
chan->io + DMA_PERIPHERAL_ADDR);
/* Set device FIFO address */
au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
if (chan->irq)
mode |= DMA_IE;
au_writel(~mode, chan->io + DMA_MODE_CLEAR);
au_writel(mode, chan->io + DMA_MODE_SET);
au_writel(mode, chan->io + DMA_MODE_SET);
}
/*
* set mode for a specific DMA channel
* Set mode for a specific DMA channel
*/
static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode)
static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
/*
@@ -266,36 +273,37 @@ static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode)
chan->mode |= mode;
}
static __inline__ unsigned int get_dma_mode(unsigned int dmanr)
static inline unsigned int get_dma_mode(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return 0;
return chan->mode;
}
static __inline__ int get_dma_active_buffer(unsigned int dmanr)
static inline int get_dma_active_buffer(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return -1;
return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
}
/*
* set the device FIFO address for a specific DMA channel - only
* Set the device FIFO address for a specific DMA channel - only
* applicable to GPO4 and GPO5. All the other devices have fixed
* FIFO addresses.
*/
static __inline__ void set_dma_fifo_addr(unsigned int dmanr,
unsigned int a)
static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
if (chan->mode & DMA_DS) /* second bank of device ids */
if (chan->mode & DMA_DS) /* second bank of device IDs */
return;
if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
@@ -307,16 +315,19 @@ static __inline__ void set_dma_fifo_addr(unsigned int dmanr,
/*
* Clear the DMA buffer done bits in the mode register.
*/
static __inline__ void clear_dma_done0(unsigned int dmanr)
static inline void clear_dma_done0(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
}
static __inline__ void clear_dma_done1(unsigned int dmanr)
static inline void clear_dma_done1(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
@@ -325,16 +336,17 @@ static __inline__ void clear_dma_done1(unsigned int dmanr)
/*
* This does nothing - not applicable to Au1000 DMA.
*/
static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
static inline void set_dma_page(unsigned int dmanr, char pagenr)
{
}
/*
* Set Buffer 0 transfer address for specific DMA channel.
*/
static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a)
static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(a, chan->io + DMA_BUFFER0_START);
@@ -343,9 +355,10 @@ static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a)
/*
* Set Buffer 1 transfer address for specific DMA channel.
*/
static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a)
static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(a, chan->io + DMA_BUFFER1_START);
@@ -355,10 +368,10 @@ static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a)
/*
* Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
*/
static __inline__ void set_dma_count0(unsigned int dmanr,
unsigned int count)
static inline void set_dma_count0(unsigned int dmanr, unsigned int count)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
count &= DMA_COUNT_MASK;
@@ -368,10 +381,10 @@ static __inline__ void set_dma_count0(unsigned int dmanr,
/*
* Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
*/
static __inline__ void set_dma_count1(unsigned int dmanr,
unsigned int count)
static inline void set_dma_count1(unsigned int dmanr, unsigned int count)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
count &= DMA_COUNT_MASK;
@@ -381,10 +394,10 @@ static __inline__ void set_dma_count1(unsigned int dmanr,
/*
* Set both buffer transfer sizes (max 64k) for a specific DMA channel.
*/
static __inline__ void set_dma_count(unsigned int dmanr,
unsigned int count)
static inline void set_dma_count(unsigned int dmanr, unsigned int count)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
count &= DMA_COUNT_MASK;
@@ -396,35 +409,36 @@ static __inline__ void set_dma_count(unsigned int dmanr,
* Returns which buffer has its done bit set in the mode register.
* Returns -1 if neither or both done bits set.
*/
static __inline__ unsigned int get_dma_buffer_done(unsigned int dmanr)
static inline unsigned int get_dma_buffer_done(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return 0;
return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
}
/*
* Returns the DMA channel's Buffer Done IRQ number.
*/
static __inline__ int get_dma_done_irq(unsigned int dmanr)
static inline int get_dma_done_irq(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return -1;
return chan->irq;
}
/*
* Get DMA residue count. Returns the number of _bytes_ left to transfer.
*/
static __inline__ int get_dma_residue(unsigned int dmanr)
static inline int get_dma_residue(unsigned int dmanr)
{
int curBufCntReg, count;
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return 0;
@@ -442,4 +456,3 @@ static __inline__ int get_dma_residue(unsigned int dmanr)
}
#endif /* __ASM_AU1000_DMA_H */
include/asm-mips/mach-au1x00/au1000_gpio.h
+9 -9
View File
@@ -2,12 +2,12 @@
* FILE NAME au1000_gpio.h
*
* BRIEF MODULE DESCRIPTION
* API to Alchemy Au1000 GPIO device.
* API to Alchemy Au1xx0 GPIO device.
*
* Author: MontaVista Software, Inc. <source@mvista.com>
* Steve Longerbeam <stevel@mvista.com>
* Steve Longerbeam
*
* Copyright 2001 MontaVista Software Inc.
* Copyright 2001, 2008 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -37,12 +37,12 @@
#define AU1000GPIO_IOC_MAGIC 'A'
#define AU1000GPIO_IN _IOR (AU1000GPIO_IOC_MAGIC, 0, int)
#define AU1000GPIO_SET _IOW (AU1000GPIO_IOC_MAGIC, 1, int)
#define AU1000GPIO_CLEAR _IOW (AU1000GPIO_IOC_MAGIC, 2, int)
#define AU1000GPIO_OUT _IOW (AU1000GPIO_IOC_MAGIC, 3, int)
#define AU1000GPIO_TRISTATE _IOW (AU1000GPIO_IOC_MAGIC, 4, int)
#define AU1000GPIO_AVAIL_MASK _IOR (AU1000GPIO_IOC_MAGIC, 5, int)
#define AU1000GPIO_IN _IOR(AU1000GPIO_IOC_MAGIC, 0, int)
#define AU1000GPIO_SET _IOW(AU1000GPIO_IOC_MAGIC, 1, int)
#define AU1000GPIO_CLEAR _IOW(AU1000GPIO_IOC_MAGIC, 2, int)
#define AU1000GPIO_OUT _IOW(AU1000GPIO_IOC_MAGIC, 3, int)
#define AU1000GPIO_TRISTATE _IOW(AU1000GPIO_IOC_MAGIC, 4, int)
#define AU1000GPIO_AVAIL_MASK _IOR(AU1000GPIO_IOC_MAGIC, 5, int)
#ifdef __KERNEL__
extern u32 get_au1000_avail_gpio_mask(void);
include/asm-mips/mach-au1x00/au1550_spi.h
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* au1550_spi.h - au1550 psc spi controller driver - platform data struct
* au1550_spi.h - Au1550 PSC SPI controller driver - platform data structure
*/
#ifndef _AU1550_SPI_H_
include/asm-mips/mach-au1x00/au1xxx.h
+2 -2
View File
@@ -23,10 +23,10 @@
#ifndef _AU1XXX_H_
#define _AU1XXX_H_
#include <asm/mach-au1x00/au1000.h>
#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \
defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
#include <asm/mach-db1x00/db1x00.h>
#elif defined(CONFIG_MIPS_PB1550)
include/asm-mips/mach-au1x00/au1xxx_dbdma.h
+73 -80
View File
@@ -28,17 +28,18 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/* Specifics for the Au1xxx Descriptor-Based DMA Controllers, first
* seen in the AU1550 part.
/*
* Specifics for the Au1xxx Descriptor-Based DMA Controller,
* first seen in the AU1550 part.
*/
#ifndef _AU1000_DBDMA_H_
#define _AU1000_DBDMA_H_
#ifndef _LANGUAGE_ASSEMBLY
/* The DMA base addresses.
* The Channels are every 256 bytes (0x0100) from the channel 0 base.
/*
* The DMA base addresses.
* The channels are every 256 bytes (0x0100) from the channel 0 base.
* Interrupt status/enable is bits 15:0 for channels 15 to zero.
*/
#define DDMA_GLOBAL_BASE 0xb4003000
@@ -51,16 +52,14 @@ typedef volatile struct dbdma_global {
u32 ddma_inten;
} dbdma_global_t;
/* General Configuration.
*/
/* General Configuration. */
#define DDMA_CONFIG_AF (1 << 2)
#define DDMA_CONFIG_AH (1 << 1)
#define DDMA_CONFIG_AL (1 << 0)
#define DDMA_THROTTLE_EN (1 << 31)
/* The structure of a DMA Channel.
*/
/* The structure of a DMA Channel. */
typedef volatile struct au1xxx_dma_channel {
u32 ddma_cfg; /* See below */
u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
@@ -69,8 +68,7 @@ typedef volatile struct au1xxx_dma_channel {
u32 ddma_irq; /* If bit 0 set, interrupt pending */
u32 ddma_stat; /* See below */
u32 ddma_bytecnt; /* Byte count, valid only when chan idle */
/* Remainder, up to the 256 byte boundary, is reserved.
*/
/* Remainder, up to the 256 byte boundary, is reserved. */
} au1x_dma_chan_t;
#define DDMA_CFG_SED (1 << 9) /* source DMA level/edge detect */
@@ -84,7 +82,8 @@ typedef volatile struct au1xxx_dma_channel {
#define DDMA_CFG_DBE (1 << 1) /* Destination big endian */
#define DDMA_CFG_EN (1 << 0) /* Channel enable */
/* Always set when descriptor processing done, regardless of
/*
* Always set when descriptor processing done, regardless of
* interrupt enable state. Reflected in global intstat, don't
* clear this until global intstat is read/used.
*/
@@ -94,7 +93,8 @@ typedef volatile struct au1xxx_dma_channel {
#define DDMA_STAT_V (1 << 1) /* Descriptor valid */
#define DDMA_STAT_H (1 << 0) /* Channel Halted */
/* "Standard" DDMA Descriptor.
/*
* "Standard" DDMA Descriptor.
* Must be 32-byte aligned.
*/
typedef volatile struct au1xxx_ddma_desc {
@@ -106,8 +106,9 @@ typedef volatile struct au1xxx_ddma_desc {
u32 dscr_dest1; /* See below */
u32 dscr_stat; /* completion status */
u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
/* First 32bytes are HW specific!!!
Lets have some SW data following.. make sure its 32bytes
/*
* First 32 bytes are HW specific!!!
* Lets have some SW data following -- make sure it's 32 bytes.
*/
u32 sw_status;
u32 sw_context;
@@ -130,10 +131,9 @@ typedef volatile struct au1xxx_ddma_desc {
#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */
#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */
#define SW_STATUS_INUSE (1<<0)
#define SW_STATUS_INUSE (1 << 0)
/* Command 0 device IDs.
*/
/* Command 0 device IDs. */
#ifdef CONFIG_SOC_AU1550
#define DSCR_CMD0_UART0_TX 0
#define DSCR_CMD0_UART0_RX 1
@@ -198,16 +198,15 @@ typedef volatile struct au1xxx_ddma_desc {
#define DSCR_CMD0_THROTTLE 30
#define DSCR_CMD0_ALWAYS 31
#define DSCR_NDEV_IDS 32
/* THis macro is used to find/create custom device types */
#define DSCR_DEV2CUSTOM_ID(x, d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF))
#define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF)
/* This macro is used to find/create custom device types */
#define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \
((d) & 0xFF))
#define DSCR_CUSTOM2DEV_ID(x) ((x) & 0xFF)
#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)
#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
/* Source/Destination transfer width.
*/
/* Source/Destination transfer width. */
#define DSCR_CMD0_BYTE 0
#define DSCR_CMD0_HALFWORD 1
#define DSCR_CMD0_WORD 2
@@ -215,16 +214,14 @@ typedef volatile struct au1xxx_ddma_desc {
#define DSCR_CMD0_SW(x) (((x) & 0x3) << 18)
#define DSCR_CMD0_DW(x) (((x) & 0x3) << 16)
/* DDMA Descriptor Type.
*/
/* DDMA Descriptor Type. */
#define DSCR_CMD0_STANDARD 0
#define DSCR_CMD0_LITERAL 1
#define DSCR_CMD0_CMP_BRANCH 2
#define DSCR_CMD0_DT(x) (((x) & 0x3) << 13)
/* Status Instruction.
*/
/* Status Instruction. */
#define DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */
#define DSCR_CMD0_ST_CURRENT 1 /* Write current status */
#define DSCR_CMD0_ST_CMD0 2 /* Write cmd0 with V cleared */
@@ -232,23 +229,20 @@ typedef volatile struct au1xxx_ddma_desc {
#define DSCR_CMD0_ST(x) (((x) & 0x3) << 0)
/* Descriptor Command 1
*/
/* Descriptor Command 1. */
#define DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */
#define DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */
#define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */
#define DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */
/* Flag description.
*/
/* Flag description. */
#define DSCR_CMD1_FL_MEM_STRIDE0 0
#define DSCR_CMD1_FL_MEM_STRIDE1 1
#define DSCR_CMD1_FL_MEM_STRIDE2 2
#define DSCR_CMD1_FL(x) (((x) & 0x3) << 22)
/* Source1, 1-dimensional stride.
*/
/* Source1, 1-dimensional stride. */
#define DSCR_SRC1_STS_MASK (3 << 30) /* Src xfer size */
#define DSCR_SRC1_SAM_MASK (3 << 28) /* Src xfer movement */
#define DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */
@@ -256,8 +250,7 @@ typedef volatile struct au1xxx_ddma_desc {
#define DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */
#define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0)
/* Dest1, 1-dimensional stride.
*/
/* Dest1, 1-dimensional stride. */
#define DSCR_DEST1_DTS_MASK (3 << 30) /* Dest xfer size */
#define DSCR_DEST1_DAM_MASK (3 << 28) /* Dest xfer movement */
#define DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */
@@ -279,29 +272,27 @@ typedef volatile struct au1xxx_ddma_desc {
#define DSCR_SRC1_SAM(x) (((x) & 3) << 28)
#define DSCR_DEST1_DAM(x) (((x) & 3) << 28)
/* The next descriptor pointer.
*/
/* The next descriptor pointer. */
#define DSCR_NXTPTR_MASK (0x07ffffff)
#define DSCR_NXTPTR(x) ((x) >> 5)
#define DSCR_GET_NXTPTR(x) ((x) << 5)
#define DSCR_NXTPTR_MS (1 << 27)
/* The number of DBDMA channels.
*/
/* The number of DBDMA channels. */
#define NUM_DBDMA_CHANS 16
/*
* Ddma API definitions
* DDMA API definitions
* FIXME: may not fit to this header file
*/
typedef struct dbdma_device_table {
u32 dev_id;
u32 dev_flags;
u32 dev_tsize;
u32 dev_devwidth;
u32 dev_physaddr; /* If FIFO */
u32 dev_intlevel;
u32 dev_intpolarity;
u32 dev_id;
u32 dev_flags;
u32 dev_tsize;
u32 dev_devwidth;
u32 dev_physaddr; /* If FIFO */
u32 dev_intlevel;
u32 dev_intpolarity;
} dbdev_tab_t;
@@ -316,44 +307,41 @@ typedef struct dbdma_chan_config {
au1x_ddma_desc_t *chan_desc_base;
au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
void *chan_callparam;
void (*chan_callback)(int, void *);
void (*chan_callback)(int, void *);
} chan_tab_t;
#define DEV_FLAGS_INUSE (1 << 0)
#define DEV_FLAGS_ANYUSE (1 << 1)
#define DEV_FLAGS_OUT (1 << 2)
#define DEV_FLAGS_IN (1 << 3)
#define DEV_FLAGS_BURSTABLE (1 << 4)
#define DEV_FLAGS_BURSTABLE (1 << 4)
#define DEV_FLAGS_SYNC (1 << 5)
/* end Ddma API definitions */
/* end DDMA API definitions */
/* External functions for drivers to use.
*/
/* Use this to allocate a dbdma channel. The device ids are one of the
* DSCR_CMD0 devices IDs, which is usually redefined to a more
* meaningful name. The 'callback' is called during dma completion
/*
* External functions for drivers to use.
* Use this to allocate a DBDMA channel. The device IDs are one of
* the DSCR_CMD0 devices IDs, which is usually redefined to a more
* meaningful name. The 'callback' is called during DMA completion
* interrupt.
*/
extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
void (*callback)(int, void *), void *callparam);
void (*callback)(int, void *),
void *callparam);
#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
/* Set the device width of a in/out fifo.
*/
/* Set the device width of an in/out FIFO. */
u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
/* Allocate a ring of descriptors for dbdma.
*/
/* Allocate a ring of descriptors for DBDMA. */
u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
/* Put buffers on source/destination descriptors.
*/
/* Put buffers on source/destination descriptors. */
u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
/* Get a buffer from the destination descriptor.
*/
/* Get a buffer from the destination descriptor. */
u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
void au1xxx_dbdma_stop(u32 chanid);
@@ -364,29 +352,34 @@ u32 au1xxx_get_dma_residue(u32 chanid);
void au1xxx_dbdma_chan_free(u32 chanid);
void au1xxx_dbdma_dump(u32 chanid);
u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr );
u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
u32 au1xxx_ddma_add_device( dbdev_tab_t *dev );
void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
/*
Some compatibilty macros --
Needed to make changes to API without breaking existing drivers
*/
#define au1xxx_dbdma_put_source(chanid, buf, nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
#define put_source_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
* Some compatibilty macros -- needed to make changes to API
* without breaking existing drivers.
*/
#define au1xxx_dbdma_put_source(chanid, buf, nbytes) \
_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) \
_au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
#define put_source_flags(chanid, buf, nbytes, flags) \
au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
#define put_dest_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) \
_au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) \
_au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
#define put_dest_flags(chanid, buf, nbytes, flags) \
au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
/*
* Flags for the put_source/put_dest functions.
*/
#define DDMA_FLAGS_IE (1<<0)
#define DDMA_FLAGS_NOIE (1<<1)
#define DDMA_FLAGS_IE (1 << 0)
#define DDMA_FLAGS_NOIE (1 << 1)
#endif /* _LANGUAGE_ASSEMBLY */
#endif /* _AU1000_DBDMA_H_ */
include/asm-mips/mach-au1x00/au1xxx_ide.h
+124 -127
View File
@@ -31,167 +31,164 @@
*/
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
#define DMA_WAIT_TIMEOUT 100
#define NUM_DESCRIPTORS PRD_ENTRIES
#define DMA_WAIT_TIMEOUT 100
#define NUM_DESCRIPTORS PRD_ENTRIES
#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
#define NUM_DESCRIPTORS 2
#define NUM_DESCRIPTORS 2
#endif
#ifndef AU1XXX_ATA_RQSIZE
#define AU1XXX_ATA_RQSIZE 128
#define AU1XXX_ATA_RQSIZE 128
#endif
/* Disable Burstable-Support for DBDMA */
#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
#endif
#ifdef CONFIG_PM
/*
* This will enable the device to be powered up when write() or read()
* is called. If this is not defined, the driver will return -EBUSY.
*/
* This will enable the device to be powered up when write() or read()
* is called. If this is not defined, the driver will return -EBUSY.
*/
#define WAKE_ON_ACCESS 1
typedef struct
{
spinlock_t lock; /* Used to block on state transitions */
au1xxx_power_dev_t *dev; /* Power Managers device structure */
unsigned stopped; /* USed to signaling device is stopped */
typedef struct {
spinlock_t lock; /* Used to block on state transitions */
au1xxx_power_dev_t *dev; /* Power Managers device structure */
unsigned stopped; /* Used to signal device is stopped */
} pm_state;
#endif
typedef struct
{
u32 tx_dev_id, rx_dev_id, target_dev_id;
u32 tx_chan, rx_chan;
void *tx_desc_head, *rx_desc_head;
ide_hwif_t *hwif;
typedef struct {
u32 tx_dev_id, rx_dev_id, target_dev_id;
u32 tx_chan, rx_chan;
void *tx_desc_head, *rx_desc_head;
ide_hwif_t *hwif;
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
ide_drive_t *drive;
struct dbdma_cmd *dma_table_cpu;
dma_addr_t dma_table_dma;
ide_drive_t *drive;
struct dbdma_cmd *dma_table_cpu;
dma_addr_t dma_table_dma;
#endif
int irq;
u32 regbase;
#ifdef CONFIG_PM
pm_state pm;
pm_state pm;
#endif
} _auide_hwif;
/*******************************************************************************
* PIO Mode timing calculation : *
* *
* Static Bus Spec ATA Spec *
* Tcsoe = t1 *
* Toecs = t9 *
* Twcs = t9 *
* Tcsh = t2i | t2 *
* Tcsoff = t2i | t2 *
* Twp = t2 *
* Tcsw = t1 *
* Tpm = 0 *
* Ta = t1+t2 *
*******************************************************************************/
/******************************************************************************/
/* PIO Mode timing calculation : */
/* */
/* Static Bus Spec ATA Spec */
/* Tcsoe = t1 */
/* Toecs = t9 */
/* Twcs = t9 */
/* Tcsh = t2i | t2 */
/* Tcsoff = t2i | t2 */
/* Twp = t2 */
/* Tcsw = t1 */
/* Tpm = 0 */
/* Ta = t1+t2 */
/******************************************************************************/
#define TCSOE_MASK (0x07<<29)
#define TOECS_MASK (0x07<<26)
#define TWCS_MASK (0x07<<28)
#define TCSH_MASK (0x0F<<24)
#define TCSOFF_MASK (0x07<<20)
#define TWP_MASK (0x3F<<14)
#define TCSW_MASK (0x0F<<10)
#define TPM_MASK (0x0F<<6)
#define TA_MASK (0x3F<<0)
#define TS_MASK (1<<8)
#define TCSOE_MASK (0x07 << 29)
#define TOECS_MASK (0x07 << 26)
#define TWCS_MASK (0x07 << 28)
#define TCSH_MASK (0x0F << 24)
#define TCSOFF_MASK (0x07 << 20)
#define TWP_MASK (0x3F << 14)
#define TCSW_MASK (0x0F << 10)
#define TPM_MASK (0x0F << 6)
#define TA_MASK (0x3F << 0)
#define TS_MASK (1 << 8)
/* Timing parameters PIO mode 0 */
#define SBC_IDE_PIO0_TCSOE (0x04<<29)
#define SBC_IDE_PIO0_TOECS (0x01<<26)
#define SBC_IDE_PIO0_TWCS (0x02<<28)
#define SBC_IDE_PIO0_TCSH (0x08<<24)
#define SBC_IDE_PIO0_TCSOFF (0x07<<20)
#define SBC_IDE_PIO0_TWP (0x10<<14)
#define SBC_IDE_PIO0_TCSW (0x04<<10)
#define SBC_IDE_PIO0_TPM (0x0<<6)
#define SBC_IDE_PIO0_TA (0x15<<0)
#define SBC_IDE_PIO0_TCSOE (0x04 << 29)
#define SBC_IDE_PIO0_TOECS (0x01 << 26)
#define SBC_IDE_PIO0_TWCS (0x02 << 28)
#define SBC_IDE_PIO0_TCSH (0x08 << 24)
#define SBC_IDE_PIO0_TCSOFF (0x07 << 20)
#define SBC_IDE_PIO0_TWP (0x10 << 14)
#define SBC_IDE_PIO0_TCSW (0x04 << 10)
#define SBC_IDE_PIO0_TPM (0x00 << 6)
#define SBC_IDE_PIO0_TA (0x15 << 0)
/* Timing parameters PIO mode 1 */
#define SBC_IDE_PIO1_TCSOE (0x03<<29)
#define SBC_IDE_PIO1_TOECS (0x01<<26)
#define SBC_IDE_PIO1_TWCS (0x01<<28)
#define SBC_IDE_PIO1_TCSH (0x06<<24)
#define SBC_IDE_PIO1_TCSOFF (0x06<<20)
#define SBC_IDE_PIO1_TWP (0x08<<14)
#define SBC_IDE_PIO1_TCSW (0x03<<10)
#define SBC_IDE_PIO1_TPM (0x00<<6)
#define SBC_IDE_PIO1_TA (0x0B<<0)
#define SBC_IDE_PIO1_TCSOE (0x03 << 29)
#define SBC_IDE_PIO1_TOECS (0x01 << 26)
#define SBC_IDE_PIO1_TWCS (0x01 << 28)
#define SBC_IDE_PIO1_TCSH (0x06 << 24)
#define SBC_IDE_PIO1_TCSOFF (0x06 << 20)
#define SBC_IDE_PIO1_TWP (0x08 << 14)
#define SBC_IDE_PIO1_TCSW (0x03 << 10)
#define SBC_IDE_PIO1_TPM (0x00 << 6)
#define SBC_IDE_PIO1_TA (0x0B << 0)
/* Timing parameters PIO mode 2 */
#define SBC_IDE_PIO2_TCSOE (0x05<<29)
#define SBC_IDE_PIO2_TOECS (0x01<<26)
#define SBC_IDE_PIO2_TWCS (0x01<<28)
#define SBC_IDE_PIO2_TCSH (0x07<<24)
#define SBC_IDE_PIO2_TCSOFF (0x07<<20)
#define SBC_IDE_PIO2_TWP (0x1F<<14)
#define SBC_IDE_PIO2_TCSW (0x05<<10)
#define SBC_IDE_PIO2_TPM (0x00<<6)
#define SBC_IDE_PIO2_TA (0x22<<0)
#define SBC_IDE_PIO2_TCSOE (0x05 << 29)
#define SBC_IDE_PIO2_TOECS (0x01 << 26)
#define SBC_IDE_PIO2_TWCS (0x01 << 28)
#define SBC_IDE_PIO2_TCSH (0x07 << 24)
#define SBC_IDE_PIO2_TCSOFF (0x07 << 20)
#define SBC_IDE_PIO2_TWP (0x1F << 14)
#define SBC_IDE_PIO2_TCSW (0x05 << 10)
#define SBC_IDE_PIO2_TPM (0x00 << 6)
#define SBC_IDE_PIO2_TA (0x22 << 0)
/* Timing parameters PIO mode 3 */
#define SBC_IDE_PIO3_TCSOE (0x05<<29)
#define SBC_IDE_PIO3_TOECS (0x01<<26)
#define SBC_IDE_PIO3_TWCS (0x01<<28)
#define SBC_IDE_PIO3_TCSH (0x0D<<24)
#define SBC_IDE_PIO3_TCSOFF (0x0D<<20)
#define SBC_IDE_PIO3_TWP (0x15<<14)
#define SBC_IDE_PIO3_TCSW (0x05<<10)
#define SBC_IDE_PIO3_TPM (0x00<<6)
#define SBC_IDE_PIO3_TA (0x1A<<0)
#define SBC_IDE_PIO3_TCSOE (0x05 << 29)
#define SBC_IDE_PIO3_TOECS (0x01 << 26)
#define SBC_IDE_PIO3_TWCS (0x01 << 28)
#define SBC_IDE_PIO3_TCSH (0x0D << 24)
#define SBC_IDE_PIO3_TCSOFF (0x0D << 20)
#define SBC_IDE_PIO3_TWP (0x15 << 14)
#define SBC_IDE_PIO3_TCSW (0x05 << 10)
#define SBC_IDE_PIO3_TPM (0x00 << 6)
#define SBC_IDE_PIO3_TA (0x1A << 0)
/* Timing parameters PIO mode 4 */
#define SBC_IDE_PIO4_TCSOE (0x04<<29)
#define SBC_IDE_PIO4_TOECS (0x01<<26)
#define SBC_IDE_PIO4_TWCS (0x01<<28)
#define SBC_IDE_PIO4_TCSH (0x04<<24)
#define SBC_IDE_PIO4_TCSOFF (0x04<<20)
#define SBC_IDE_PIO4_TWP (0x0D<<14)
#define SBC_IDE_PIO4_TCSW (0x03<<10)
#define SBC_IDE_PIO4_TPM (0x00<<6)
#define SBC_IDE_PIO4_TA (0x12<<0)
#define SBC_IDE_PIO4_TCSOE (0x04 << 29)
#define SBC_IDE_PIO4_TOECS (0x01 << 26)
#define SBC_IDE_PIO4_TWCS (0x01 << 28)
#define SBC_IDE_PIO4_TCSH (0x04 << 24)
#define SBC_IDE_PIO4_TCSOFF (0x04 << 20)
#define SBC_IDE_PIO4_TWP (0x0D << 14)
#define SBC_IDE_PIO4_TCSW (0x03 << 10)
#define SBC_IDE_PIO4_TPM (0x00 << 6)
#define SBC_IDE_PIO4_TA (0x12 << 0)
/* Timing parameters MDMA mode 0 */
#define SBC_IDE_MDMA0_TCSOE (0x03<<29)
#define SBC_IDE_MDMA0_TOECS (0x01<<26)
#define SBC_IDE_MDMA0_TWCS (0x01<<28)
#define SBC_IDE_MDMA0_TCSH (0x07<<24)
#define SBC_IDE_MDMA0_TCSOFF (0x07<<20)
#define SBC_IDE_MDMA0_TWP (0x0C<<14)
#define SBC_IDE_MDMA0_TCSW (0x03<<10)
#define SBC_IDE_MDMA0_TPM (0x00<<6)
#define SBC_IDE_MDMA0_TA (0x0F<<0)
#define SBC_IDE_MDMA0_TCSOE (0x03 << 29)
#define SBC_IDE_MDMA0_TOECS (0x01 << 26)
#define SBC_IDE_MDMA0_TWCS (0x01 << 28)
#define SBC_IDE_MDMA0_TCSH (0x07 << 24)
#define SBC_IDE_MDMA0_TCSOFF (0x07 << 20)
#define SBC_IDE_MDMA0_TWP (0x0C << 14)
#define SBC_IDE_MDMA0_TCSW (0x03 << 10)
#define SBC_IDE_MDMA0_TPM (0x00 << 6)
#define SBC_IDE_MDMA0_TA (0x0F << 0)
/* Timing parameters MDMA mode 1 */
#define SBC_IDE_MDMA1_TCSOE (0x05<<29)
#define SBC_IDE_MDMA1_TOECS (0x01<<26)
#define SBC_IDE_MDMA1_TWCS (0x01<<28)
#define SBC_IDE_MDMA1_TCSH (0x05<<24)
#define SBC_IDE_MDMA1_TCSOFF (0x05<<20)
#define SBC_IDE_MDMA1_TWP (0x0F<<14)
#define SBC_IDE_MDMA1_TCSW (0x05<<10)
#define SBC_IDE_MDMA1_TPM (0x00<<6)
#define SBC_IDE_MDMA1_TA (0x15<<0)
#define SBC_IDE_MDMA1_TCSOE (0x05 << 29)
#define SBC_IDE_MDMA1_TOECS (0x01 << 26)
#define SBC_IDE_MDMA1_TWCS (0x01 << 28)
#define SBC_IDE_MDMA1_TCSH (0x05 << 24)
#define SBC_IDE_MDMA1_TCSOFF (0x05 << 20)
#define SBC_IDE_MDMA1_TWP (0x0F << 14)
#define SBC_IDE_MDMA1_TCSW (0x05 << 10)
#define SBC_IDE_MDMA1_TPM (0x00 << 6)
#define SBC_IDE_MDMA1_TA (0x15 << 0)
/* Timing parameters MDMA mode 2 */
#define SBC_IDE_MDMA2_TCSOE (0x04<<29)
#define SBC_IDE_MDMA2_TOECS (0x01<<26)
#define SBC_IDE_MDMA2_TWCS (0x01<<28)
#define SBC_IDE_MDMA2_TCSH (0x04<<24)
#define SBC_IDE_MDMA2_TCSOFF (0x04<<20)
#define SBC_IDE_MDMA2_TWP (0x0D<<14)
#define SBC_IDE_MDMA2_TCSW (0x04<<10)
#define SBC_IDE_MDMA2_TPM (0x00<<6)
#define SBC_IDE_MDMA2_TA (0x12<<0)
#define SBC_IDE_MDMA2_TCSOE (0x04 << 29)
#define SBC_IDE_MDMA2_TOECS (0x01 << 26)
#define SBC_IDE_MDMA2_TWCS (0x01 << 28)
#define SBC_IDE_MDMA2_TCSH (0x04 << 24)
#define SBC_IDE_MDMA2_TCSOFF (0x04 << 20)
#define SBC_IDE_MDMA2_TWP (0x0D << 14)
#define SBC_IDE_MDMA2_TCSW (0x04 << 10)
#define SBC_IDE_MDMA2_TPM (0x00 << 6)
#define SBC_IDE_MDMA2_TA (0x12 << 0)
#define SBC_IDE_TIMING(mode) \
SBC_IDE_##mode##_TWCS | \
SBC_IDE_##mode##_TCSH | \
SBC_IDE_##mode##_TCSOFF | \
SBC_IDE_##mode##_TWP | \
SBC_IDE_##mode##_TCSW | \
SBC_IDE_##mode##_TPM | \
SBC_IDE_##mode##_TA
(SBC_IDE_##mode##_TWCS | \
SBC_IDE_##mode##_TCSH | \
SBC_IDE_##mode##_TCSOFF | \
SBC_IDE_##mode##_TWP | \
SBC_IDE_##mode##_TCSW | \
SBC_IDE_##mode##_TPM | \
SBC_IDE_##mode##_TA)
include/asm-mips/mach-au1x00/au1xxx_psc.h
+47 -80
View File
@@ -33,7 +33,6 @@
#ifndef _AU1000_PSC_H_
#define _AU1000_PSC_H_
/* The PSC base addresses. */
#ifdef CONFIG_SOC_AU1550
#define PSC0_BASE_ADDR 0xb1a00000
@@ -47,8 +46,8 @@
#define PSC1_BASE_ADDR 0xb1b00000
#endif
/* The PSC select and control registers are common to
* all protocols.
/*
* The PSC select and control registers are common to all protocols.
*/
#define PSC_SEL_OFFSET 0x00000000
#define PSC_CTRL_OFFSET 0x00000004
@@ -59,18 +58,17 @@
#define PSC_SEL_CLK_SERCLK (2 << 4)
#define PSC_SEL_PS_MASK 0x00000007
#define PSC_SEL_PS_DISABLED (0)
#define PSC_SEL_PS_SPIMODE (2)
#define PSC_SEL_PS_I2SMODE (3)
#define PSC_SEL_PS_AC97MODE (4)
#define PSC_SEL_PS_SMBUSMODE (5)
#define PSC_SEL_PS_DISABLED 0
#define PSC_SEL_PS_SPIMODE 2
#define PSC_SEL_PS_I2SMODE 3
#define PSC_SEL_PS_AC97MODE 4
#define PSC_SEL_PS_SMBUSMODE 5
#define PSC_CTRL_DISABLE (0)
#define PSC_CTRL_SUSPEND (2)
#define PSC_CTRL_ENABLE (3)
#define PSC_CTRL_DISABLE 0
#define PSC_CTRL_SUSPEND 2
#define PSC_CTRL_ENABLE 3
/* AC97 Registers.
*/
/* AC97 Registers. */
#define PSC_AC97CFG_OFFSET 0x00000008
#define PSC_AC97MSK_OFFSET 0x0000000c
#define PSC_AC97PCR_OFFSET 0x00000010
@@ -95,8 +93,7 @@
#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
/* AC97 Config Register.
*/
/* AC97 Config Register. */
#define PSC_AC97CFG_RT_MASK (3 << 30)
#define PSC_AC97CFG_RT_FIFO1 (0 << 30)
#define PSC_AC97CFG_RT_FIFO2 (1 << 30)
@@ -118,20 +115,19 @@
#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1)
#define PSC_AC97CFG_GE_ENABLE (1)
/* Enable slots 3-12.
*/
/* Enable slots 3-12. */
#define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11))
#define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1))
/* The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
/*
* The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
* The only sensible numbers are 7, 9, or possibly 11. Nah, just do the
* arithmetic in the macro.
*/
#define PSC_AC97CFG_SET_LEN(x) (((((x)-2)/2) & 0xf) << 21)
#define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21)
#define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2)
/* AC97 Mask Register.
*/
/* AC97 Mask Register. */
#define PSC_AC97MSK_GR (1 << 25)
#define PSC_AC97MSK_CD (1 << 24)
#define PSC_AC97MSK_RR (1 << 13)
@@ -148,8 +144,7 @@
PSC_AC97MSK_TO | PSC_AC97MSK_TU | \
PSC_AC97MSK_RD | PSC_AC97MSK_TD)
/* AC97 Protocol Control Register.
*/
/* AC97 Protocol Control Register. */
#define PSC_AC97PCR_RC (1 << 6)
#define PSC_AC97PCR_RP (1 << 5)
#define PSC_AC97PCR_RS (1 << 4)
@@ -157,8 +152,7 @@
#define PSC_AC97PCR_TP (1 << 1)
#define PSC_AC97PCR_TS (1 << 0)
/* AC97 Status register (read only).
*/
/* AC97 Status register (read only). */
#define PSC_AC97STAT_CB (1 << 26)
#define PSC_AC97STAT_CP (1 << 25)
#define PSC_AC97STAT_CR (1 << 24)
@@ -174,8 +168,7 @@
#define PSC_AC97STAT_DR (1 << 1)
#define PSC_AC97STAT_SR (1 << 0)
/* AC97 Event Register.
*/
/* AC97 Event Register. */
#define PSC_AC97EVNT_GR (1 << 25)
#define PSC_AC97EVNT_CD (1 << 24)
#define PSC_AC97EVNT_RR (1 << 13)
@@ -187,22 +180,18 @@
#define PSC_AC97EVNT_RD (1 << 5)
#define PSC_AC97EVNT_TD (1 << 4)
/* CODEC Command Register.
*/
/* CODEC Command Register. */
#define PSC_AC97CDC_RD (1 << 25)
#define PSC_AC97CDC_ID_MASK (3 << 23)
#define PSC_AC97CDC_INDX_MASK (0x7f << 16)
#define PSC_AC97CDC_ID(x) (((x) & 0x3) << 23)
#define PSC_AC97CDC_ID(x) (((x) & 0x03) << 23)
#define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16)
/* AC97 Reset Control Register.
*/
/* AC97 Reset Control Register. */
#define PSC_AC97RST_RST (1 << 1)
#define PSC_AC97RST_SNC (1 << 0)
/* PSC in I2S Mode.
*/
/* PSC in I2S Mode. */
typedef struct psc_i2s {
u32 psc_sel;
u32 psc_ctrl;
@@ -215,8 +204,7 @@ typedef struct psc_i2s {
u32 psc_i2sudf;
} psc_i2s_t;
/* I2S Config Register.
*/
/* I2S Config Register. */
#define PSC_I2SCFG_RT_MASK (3 << 30)
#define PSC_I2SCFG_RT_FIFO1 (0 << 30)
#define PSC_I2SCFG_RT_FIFO2 (1 << 30)
@@ -247,8 +235,7 @@ typedef struct psc_i2s {
#define PSC_I2SCFG_MLJ (1 << 10)
#define PSC_I2SCFG_XM (1 << 9)
/* The word length equation is simply LEN+1.
*/
/* The word length equation is simply LEN+1. */
#define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4)
#define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1)
@@ -256,8 +243,7 @@ typedef struct psc_i2s {
#define PSC_I2SCFG_MLF (1 << 1)
#define PSC_I2SCFG_MS (1 << 0)
/* I2S Mask Register.
*/
/* I2S Mask Register. */
#define PSC_I2SMSK_RR (1 << 13)
#define PSC_I2SMSK_RO (1 << 12)
#define PSC_I2SMSK_RU (1 << 11)
@@ -271,8 +257,7 @@ typedef struct psc_i2s {
PSC_I2SMSK_TO | PSC_I2SMSK_TU | \
PSC_I2SMSK_RD | PSC_I2SMSK_TD)
/* I2S Protocol Control Register.
*/
/* I2S Protocol Control Register. */
#define PSC_I2SPCR_RC (1 << 6)
#define PSC_I2SPCR_RP (1 << 5)
#define PSC_I2SPCR_RS (1 << 4)
@@ -280,8 +265,7 @@ typedef struct psc_i2s {
#define PSC_I2SPCR_TP (1 << 1)
#define PSC_I2SPCR_TS (1 << 0)
/* I2S Status register (read only).
*/
/* I2S Status register (read only). */
#define PSC_I2SSTAT_RF (1 << 13)
#define PSC_I2SSTAT_RE (1 << 12)
#define PSC_I2SSTAT_RR (1 << 11)
@@ -294,8 +278,7 @@ typedef struct psc_i2s {
#define PSC_I2SSTAT_DR (1 << 1)
#define PSC_I2SSTAT_SR (1 << 0)
/* I2S Event Register.
*/
/* I2S Event Register. */
#define PSC_I2SEVNT_RR (1 << 13)
#define PSC_I2SEVNT_RO (1 << 12)
#define PSC_I2SEVNT_RU (1 << 11)
@@ -305,8 +288,7 @@ typedef struct psc_i2s {
#define PSC_I2SEVNT_RD (1 << 5)
#define PSC_I2SEVNT_TD (1 << 4)
/* PSC in SPI Mode.
*/
/* PSC in SPI Mode. */
typedef struct psc_spi {
u32 psc_sel;
u32 psc_ctrl;
@@ -318,8 +300,7 @@ typedef struct psc_spi {
u32 psc_spitxrx;
} psc_spi_t;
/* SPI Config Register.
*/
/* SPI Config Register. */
#define PSC_SPICFG_RT_MASK (3 << 30)
#define PSC_SPICFG_RT_FIFO1 (0 << 30)
#define PSC_SPICFG_RT_FIFO2 (1 << 30)
@@ -355,8 +336,7 @@ typedef struct psc_spi {
#define PSC_SPICFG_MLF (1 << 1)
#define PSC_SPICFG_MO (1 << 0)
/* SPI Mask Register.
*/
/* SPI Mask Register. */
#define PSC_SPIMSK_MM (1 << 16)
#define PSC_SPIMSK_RR (1 << 13)
#define PSC_SPIMSK_RO (1 << 12)
@@ -371,16 +351,14 @@ typedef struct psc_spi {
PSC_SPIMSK_TU | PSC_SPIMSK_SD | \
PSC_SPIMSK_MD)
/* SPI Protocol Control Register.
*/
/* SPI Protocol Control Register. */
#define PSC_SPIPCR_RC (1 << 6)
#define PSC_SPIPCR_SP (1 << 5)
#define PSC_SPIPCR_SS (1 << 4)
#define PSC_SPIPCR_TC (1 << 2)
#define PSC_SPIPCR_MS (1 << 0)
/* SPI Status register (read only).
*/
/* SPI Status register (read only). */
#define PSC_SPISTAT_RF (1 << 13)
#define PSC_SPISTAT_RE (1 << 12)
#define PSC_SPISTAT_RR (1 << 11)
@@ -393,8 +371,7 @@ typedef struct psc_spi {
#define PSC_SPISTAT_DR (1 << 1)
#define PSC_SPISTAT_SR (1 << 0)
/* SPI Event Register.
*/
/* SPI Event Register. */
#define PSC_SPIEVNT_MM (1 << 16)
#define PSC_SPIEVNT_RR (1 << 13)
#define PSC_SPIEVNT_RO (1 << 12)
@@ -405,13 +382,11 @@ typedef struct psc_spi {
#define PSC_SPIEVNT_SD (1 << 5)
#define PSC_SPIEVNT_MD (1 << 4)
/* Transmit register control.
*/
/* Transmit register control. */
#define PSC_SPITXRX_LC (1 << 29)
#define PSC_SPITXRX_SR (1 << 28)
/* PSC in SMBus (I2C) Mode.
*/
/* PSC in SMBus (I2C) Mode. */
typedef struct psc_smb {
u32 psc_sel;
u32 psc_ctrl;
@@ -424,8 +399,7 @@ typedef struct psc_smb {
u32 psc_smbtmr;
} psc_smb_t;
/* SMBus Config Register.
*/
/* SMBus Config Register. */
#define PSC_SMBCFG_RT_MASK (3 << 30)
#define PSC_SMBCFG_RT_FIFO1 (0 << 30)
#define PSC_SMBCFG_RT_FIFO2 (1 << 30)
@@ -452,8 +426,7 @@ typedef struct psc_smb {
#define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1)
/* SMBus Mask Register.
*/
/* SMBus Mask Register. */
#define PSC_SMBMSK_DN (1 << 30)
#define PSC_SMBMSK_AN (1 << 29)
#define PSC_SMBMSK_AL (1 << 28)
@@ -471,13 +444,11 @@ typedef struct psc_smb {
PSC_SMBMSK_TU | PSC_SMBMSK_SD | \
PSC_SMBMSK_MD)
/* SMBus Protocol Control Register.
*/
/* SMBus Protocol Control Register. */
#define PSC_SMBPCR_DC (1 << 2)
#define PSC_SMBPCR_MS (1 << 0)
/* SMBus Status register (read only).
*/
/* SMBus Status register (read only). */
#define PSC_SMBSTAT_BB (1 << 28)
#define PSC_SMBSTAT_RF (1 << 13)
#define PSC_SMBSTAT_RE (1 << 12)
@@ -491,8 +462,7 @@ typedef struct psc_smb {
#define PSC_SMBSTAT_DR (1 << 1)
#define PSC_SMBSTAT_SR (1 << 0)
/* SMBus Event Register.
*/
/* SMBus Event Register. */
#define PSC_SMBEVNT_DN (1 << 30)
#define PSC_SMBEVNT_AN (1 << 29)
#define PSC_SMBEVNT_AL (1 << 28)
@@ -510,15 +480,13 @@ typedef struct psc_smb {
PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \
PSC_SMBEVNT_MD)
/* Transmit register control.
*/
/* Transmit register control. */
#define PSC_SMBTXRX_RSR (1 << 28)
#define PSC_SMBTXRX_STP (1 << 29)
#define PSC_SMBTXRX_DATAMASK (0xff)
#define PSC_SMBTXRX_DATAMASK 0xff
/* SMBus protocol timers register.
*/
#define PSC_SMBTMR_SET_TH(x) (((x) & 0x3) << 30)
/* SMBus protocol timers register. */
#define PSC_SMBTMR_SET_TH(x) (((x) & 0x03) << 30)
#define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25)
#define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20)
#define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15)
@@ -526,5 +494,4 @@ typedef struct psc_smb {
#define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5)
#define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0)
#endif /* _AU1000_PSC_H_ */
include/asm-mips/mach-db1x00/db1200.h
+35 -38
View File
@@ -1,6 +1,6 @@
/*
* AMD Alchemy DB1200 Referrence Board
* Board Registers defines.
* AMD Alchemy DBAu1200 Reference Board
* Board register defines.
*
* ########################################################################
*
@@ -27,26 +27,25 @@
#include <linux/types.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
// This is defined in au1000.h with bogus value
#undef AU1X00_EXTERNAL_INT
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
/* SPI and SMB are muxed on the Pb1200 board.
Refer to board documentation.
/*
* SPI and SMB are muxed on the DBAu1200 board.
* Refer to board documentation.
*/
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define SMBUS_PSC_BASE PSC0_BASE_ADDR
/* AC97 and I2S are muxed on the Pb1200 board.
Refer to board documentation.
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define SMBUS_PSC_BASE PSC0_BASE_ADDR
/*
* AC'97 and I2S are muxed on the DBAu1200 board.
* Refer to board documentation.
*/
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define I2S_PSC_BASE PSC1_BASE_ADDR
#define BCSR_KSEG1_ADDR 0xB9800000
#define BCSR_KSEG1_ADDR 0xB9800000
typedef volatile struct
{
@@ -102,9 +101,9 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_STATUS_SWAPBOOT 0x0040
#define BCSR_STATUS_FLASHBUSY 0x0100
#define BCSR_STATUS_IDECBLID 0x0200
#define BCSR_STATUS_SD0WP 0x0400
#define BCSR_STATUS_U0RXD 0x1000
#define BCSR_STATUS_U1RXD 0x2000
#define BCSR_STATUS_SD0WP 0x0400
#define BCSR_STATUS_U0RXD 0x1000
#define BCSR_STATUS_U1RXD 0x2000
#define BCSR_SWITCHES_OCTAL 0x00FF
#define BCSR_SWITCHES_DIP_1 0x0080
@@ -122,8 +121,8 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_RESETS_DC 0x0004
#define BCSR_RESETS_IDE 0x0008
#define BCSR_RESETS_TV 0x0010
/* not resets but in the same register */
#define BCSR_RESETS_PWMR1mUX 0x0800
/* Not resets but in the same register */
#define BCSR_RESETS_PWMR1MUX 0x0800
#define BCSR_RESETS_PCS0MUX 0x1000
#define BCSR_RESETS_PCS1MUX 0x2000
#define BCSR_RESETS_SPISEL 0x4000
@@ -160,7 +159,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_INT_PC0STSCHG 0x0008
#define BCSR_INT_PC1 0x0010
#define BCSR_INT_PC1STSCHG 0x0020
#define BCSR_INT_DC 0x0040
#define BCSR_INT_DC 0x0040
#define BCSR_INT_FLASHBUSY 0x0080
#define BCSR_INT_PC0INSERT 0x0100
#define BCSR_INT_PC0EJECT 0x0200
@@ -179,10 +178,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
#define IDE_RQSIZE 128
#define NAND_PHYS_ADDR 0x20000000
#define NAND_PHYS_ADDR 0x20000000
/*
* External Interrupts for Pb1200 as of 8/6/2004.
* External Interrupts for DBAu1200 as of 8/6/2004.
* Bit positions in the CPLD registers can be calculated by taking
* the interrupt define and subtracting the DB1200_INT_BEGIN value.
*
@@ -211,23 +210,21 @@ enum external_pb1200_ints {
};
/* For drivers/pcmcia/au1000_db1x00.c */
/* PCMCIA Db1x00 specific defines */
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
/*
* DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
*/
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP, SLOT)\
((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
#define SET_VCC_VPP(VCC, VPP, SLOT) \
((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
#define BOARD_PC0_INT DB1200_PC0_INT
#define BOARD_PC1_INT DB1200_PC1_INT
#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
#define BOARD_PC0_INT DB1200_PC0_INT
#define BOARD_PC1_INT DB1200_PC1_INT
#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
/* Nand chip select */
/* NAND chip select */
#define NAND_CS 1
#endif /* __ASM_DB1200_H */
include/asm-mips/mach-db1x00/db1x00.h
+42 -41
View File
@@ -1,9 +1,8 @@
/*
* AMD Alchemy DB1x00 Reference Boards
* AMD Alchemy DBAu1x00 Reference Boards
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
*
* ########################################################################
@@ -32,26 +31,26 @@
#ifdef CONFIG_MIPS_DB1550
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define SMBUS_PSC_BASE PSC2_BASE_ADDR
#define I2S_PSC_BASE PSC3_BASE_ADDR
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define SMBUS_PSC_BASE PSC2_BASE_ADDR
#define I2S_PSC_BASE PSC3_BASE_ADDR
#define BCSR_KSEG1_ADDR 0xAF000000
#define NAND_PHYS_ADDR 0x20000000
#define BCSR_KSEG1_ADDR 0xAF000000
#define NAND_PHYS_ADDR 0x20000000
#else
#define BCSR_KSEG1_ADDR 0xAE000000
#endif
/*
* Overlay data structure of the Db1x00 board registers.
* Registers located at physical 0E0000xx, KSEG1 0xAE0000xx
* Overlay data structure of the DBAu1x00 board registers.
* Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx.
*/
typedef volatile struct
{
@@ -138,18 +137,19 @@ typedef volatile struct
#define BCSR_SWRESET_RESET 0x0080
/* PCMCIA Db1x00 specific defines */
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
/* PCMCIA DBAu1x00 specific defines */
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP, SLOT)\
((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
/* SD controller macros */
/*
* Detect card.
* SD controller macros
*/
/* Detect card. */
#define mmc_card_inserted(_n_, _res_) \
do { \
BCSR * const bcsr = (BCSR *)0xAE000000; \
@@ -176,10 +176,10 @@ typedef volatile struct
unsigned long mmc_pwr, mmc_wp, board_specific; \
if ((_n_)) { \
mmc_pwr = BCSR_BOARD_SD1_PWR; \
mmc_wp = BCSR_BOARD_SD1_WP; \
mmc_wp = BCSR_BOARD_SD1_WP; \
} else { \
mmc_pwr = BCSR_BOARD_SD0_PWR; \
mmc_wp = BCSR_BOARD_SD0_WP; \
mmc_wp = BCSR_BOARD_SD0_WP; \
} \
board_specific = au_readl((unsigned long)(&bcsr->specific)); \
if (!(board_specific & mmc_wp)) {/* low means card present */ \
@@ -190,17 +190,19 @@ typedef volatile struct
} while (0)
/* NAND defines */
/* Timing values as described in databook, * ns value stripped of
/*
* NAND defines
*
* Timing values as described in databook, * ns value stripped of the
* lower 2 bits.
* These defines are here rather than an SOC1550 generic file because
* These defines are here rather than an Au1550 generic file because
* the parts chosen on another board may be different and may require
* different timings.
*/
#define NAND_T_H (18 >> 2)
#define NAND_T_PUL (30 >> 2)
#define NAND_T_SU (30 >> 2)
#define NAND_T_WH (30 >> 2)
#define NAND_T_H (18 >> 2)
#define NAND_T_PUL (30 >> 2)
#define NAND_T_SU (30 >> 2)
#define NAND_T_WH (30 >> 2)
/* Bitfield shift amounts */
#define NAND_T_H_SHIFT 0
@@ -208,16 +210,15 @@ typedef volatile struct
#define NAND_T_SU_SHIFT 8
#define NAND_T_WH_SHIFT 12
#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
#define NAND_CS 1
#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
#define NAND_CS 1
/* should be done by yamon */
#define NAND_STCFG 0x00400005 /* 8-bit NAND */
#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */
#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
/* Should be done by YAMON */
#define NAND_STCFG 0x00400005 /* 8-bit NAND */
#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
#endif /* __ASM_DB1X00_H */
include/asm-mips/mach-pb1x00/pb1000.h
+48 -133
View File
@@ -1,9 +1,8 @@
/*
* Alchemy Semi PB1000 Referrence Board
* Alchemy Semi Pb1000 Referrence Board
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* ########################################################################
*
@@ -28,145 +27,61 @@
#define __ASM_PB1000_H
/* PCMCIA PB1000 specific defines */
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
#define PB1000_PCR 0xBE000000
# define PCR_SLOT_0_VPP0 (1<<0)
# define PCR_SLOT_0_VPP1 (1<<1)
# define PCR_SLOT_0_VCC0 (1<<2)
# define PCR_SLOT_0_VCC1 (1<<3)
# define PCR_SLOT_0_RST (1<<4)
#define PB1000_PCR 0xBE000000
# define PCR_SLOT_0_VPP0 (1 << 0)
# define PCR_SLOT_0_VPP1 (1 << 1)
# define PCR_SLOT_0_VCC0 (1 << 2)
# define PCR_SLOT_0_VCC1 (1 << 3)
# define PCR_SLOT_0_RST (1 << 4)
# define PCR_SLOT_1_VPP0 (1 << 8)
# define PCR_SLOT_1_VPP1 (1 << 9)
# define PCR_SLOT_1_VCC0 (1 << 10)
# define PCR_SLOT_1_VCC1 (1 << 11)
# define PCR_SLOT_1_RST (1 << 12)
# define PCR_SLOT_1_VPP0 (1<<8)
# define PCR_SLOT_1_VPP1 (1<<9)
# define PCR_SLOT_1_VCC0 (1<<10)
# define PCR_SLOT_1_VCC1 (1<<11)
# define PCR_SLOT_1_RST (1<<12)
#define PB1000_MDR 0xBE000004
# define MDR_PI (1 << 5) /* PCMCIA int latch */
# define MDR_EPI (1 << 14) /* enable PCMCIA int */
# define MDR_CPI (1 << 15) /* clear PCMCIA int */
#define PB1000_MDR 0xBE000004
# define MDR_PI (1<<5) /* pcmcia int latch */
# define MDR_EPI (1<<14) /* enable pcmcia int */
# define MDR_CPI (1<<15) /* clear pcmcia int */
#define PB1000_ACR1 0xBE000008
# define ACR1_SLOT_0_CD1 (1 << 0) /* card detect 1 */
# define ACR1_SLOT_0_CD2 (1 << 1) /* card detect 2 */
# define ACR1_SLOT_0_READY (1 << 2) /* ready */
# define ACR1_SLOT_0_STATUS (1 << 3) /* status change */
# define ACR1_SLOT_0_VS1 (1 << 4) /* voltage sense 1 */
# define ACR1_SLOT_0_VS2 (1 << 5) /* voltage sense 2 */
# define ACR1_SLOT_0_INPACK (1 << 6) /* inpack pin status */
# define ACR1_SLOT_1_CD1 (1 << 8) /* card detect 1 */
# define ACR1_SLOT_1_CD2 (1 << 9) /* card detect 2 */
# define ACR1_SLOT_1_READY (1 << 10) /* ready */
# define ACR1_SLOT_1_STATUS (1 << 11) /* status change */
# define ACR1_SLOT_1_VS1 (1 << 12) /* voltage sense 1 */
# define ACR1_SLOT_1_VS2 (1 << 13) /* voltage sense 2 */
# define ACR1_SLOT_1_INPACK (1 << 14) /* inpack pin status */
#define PB1000_ACR1 0xBE000008
# define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */
# define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */
# define ACR1_SLOT_0_READY (1<<2) /* ready */
# define ACR1_SLOT_0_STATUS (1<<3) /* status change */
# define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */
# define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */
# define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */
# define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */
# define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */
# define ACR1_SLOT_1_READY (1<<10) /* ready */
# define ACR1_SLOT_1_STATUS (1<<11) /* status change */
# define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */
# define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */
# define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */
#define CPLD_AUX0 0xBE00000C
#define CPLD_AUX1 0xBE000010
#define CPLD_AUX2 0xBE000014
#define CPLD_AUX0 0xBE00000C
#define CPLD_AUX1 0xBE000010
#define CPLD_AUX2 0xBE000014
/* Voltage levels */
/* VPPEN1 - VPPEN0 */
#define VPP_GND ((0<<1) | (0<<0))
#define VPP_5V ((1<<1) | (0<<0))
#define VPP_3V ((0<<1) | (1<<0))
#define VPP_12V ((0<<1) | (1<<0))
#define VPP_HIZ ((1<<1) | (1<<0))
#define VPP_GND ((0 << 1) | (0 << 0))
#define VPP_5V ((1 << 1) | (0 << 0))
#define VPP_3V ((0 << 1) | (1 << 0))
#define VPP_12V ((0 << 1) | (1 << 0))
#define VPP_HIZ ((1 << 1) | (1 << 0))
/* VCCEN1 - VCCEN0 */
#define VCC_3V ((0<<1) | (1<<0))
#define VCC_5V ((1<<1) | (0<<0))
#define VCC_HIZ ((0<<1) | (0<<0))
#define VCC_3V ((0 << 1) | (1 << 0))
#define VCC_5V ((1 << 1) | (0 << 0))
#define VCC_HIZ ((0 << 1) | (0 << 0))
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP, SLOT)\
((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
/* PCI PB1000 specific defines */
/* The reason these defines are here instead of au1000.h is because
* the Au1000 does not have a PCI bus controller so the PCI implementation
* on the some of the older Pb1000 boards was very board specific.
*/
#define PCI_CONFIG_BASE 0xBA020000 /* the only external slot */
#define SDRAM_DEVID 0xBA010000
#define SDRAM_CMD 0xBA010004
#define SDRAM_CLASS 0xBA010008
#define SDRAM_MISC 0xBA01000C
#define SDRAM_MBAR 0xBA010010
#define PCI_IO_DATA_PORT 0xBA800000
#define PCI_IO_ADDR 0xBE00001C
#define PCI_INT_ACK 0xBBC00000
#define PCI_IO_READ 0xBBC00020
#define PCI_IO_WRITE 0xBBC00030
#define PCI_BRIDGE_CONFIG 0xBE000018
#define PCI_IO_START 0x10000000
#define PCI_IO_END 0x1000ffff
#define PCI_MEM_START 0x18000000
#define PCI_MEM_END 0x18ffffff
#define PCI_FIRST_DEVFN 0
#define PCI_LAST_DEVFN 1
static inline u8 au_pci_io_readb(u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
return (readl(PCI_IO_DATA_PORT) & 0xff);
}
static inline u16 au_pci_io_readw(u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
return (readl(PCI_IO_DATA_PORT) & 0xffff);
}
static inline u32 au_pci_io_readl(u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff), PCI_BRIDGE_CONFIG);
return readl(PCI_IO_DATA_PORT);
}
static inline void au_pci_io_writeb(u8 val, u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
writel(val, PCI_IO_DATA_PORT);
}
static inline void au_pci_io_writew(u16 val, u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
writel(val, PCI_IO_DATA_PORT);
}
static inline void au_pci_io_writel(u32 val, u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel(readl(PCI_BRIDGE_CONFIG) & 0xffffcfff, PCI_BRIDGE_CONFIG);
writel(val, PCI_IO_DATA_PORT);
}
static inline void set_sdram_extbyte(void)
{
writel(readl(PCI_BRIDGE_CONFIG) & 0xffffff00, PCI_BRIDGE_CONFIG);
}
static inline void set_slot_extbyte(void)
{
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffbf00) | 0x18, PCI_BRIDGE_CONFIG);
}
#define SET_VCC_VPP(VCC, VPP, SLOT) \
((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
#endif /* __ASM_PB1000_H */
include/asm-mips/mach-pb1x00/pb1100.h
+48 -48
View File
@@ -1,9 +1,8 @@
/*
* Alchemy Semi PB1100 Referrence Board
* Alchemy Semi Pb1100 Referrence Board
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* ########################################################################
*
@@ -27,59 +26,60 @@
#ifndef __ASM_PB1100_H
#define __ASM_PB1100_H
#define PB1100_IDENT 0xAE000000
#define BOARD_STATUS_REG 0xAE000004
# define PB1100_ROM_SEL (1<<15)
# define PB1100_ROM_SIZ (1<<14)
# define PB1100_SWAP_BOOT (1<<13)
# define PB1100_FLASH_WP (1<<12)
# define PB1100_ROM_H_STS (1<<11)
# define PB1100_ROM_L_STS (1<<10)
# define PB1100_FLASH_H_STS (1<<9)
# define PB1100_FLASH_L_STS (1<<8)
# define PB1100_SRAM_SIZ (1<<7)
# define PB1100_TSC_BUSY (1<<6)
# define PB1100_PCMCIA_VS_MASK (3<<4)
# define PB1100_RS232_CD (1<<3)
# define PB1100_RS232_CTS (1<<2)
# define PB1100_RS232_DSR (1<<1)
# define PB1100_RS232_RI (1<<0)
#define PB1100_IDENT 0xAE000000
#define BOARD_STATUS_REG 0xAE000004
# define PB1100_ROM_SEL (1 << 15)
# define PB1100_ROM_SIZ (1 << 14)
# define PB1100_SWAP_BOOT (1 << 13)
# define PB1100_FLASH_WP (1 << 12)
# define PB1100_ROM_H_STS (1 << 11)
# define PB1100_ROM_L_STS (1 << 10)
# define PB1100_FLASH_H_STS (1 << 9)
# define PB1100_FLASH_L_STS (1 << 8)
# define PB1100_SRAM_SIZ (1 << 7)
# define PB1100_TSC_BUSY (1 << 6)
# define PB1100_PCMCIA_VS_MASK (3 << 4)
# define PB1100_RS232_CD (1 << 3)
# define PB1100_RS232_CTS (1 << 2)
# define PB1100_RS232_DSR (1 << 1)
# define PB1100_RS232_RI (1 << 0)
#define PB1100_IRDA_RS232 0xAE00000C
# define PB1100_IRDA_FULL (0<<14) /* full power */
# define PB1100_IRDA_SHUTDOWN (1<<14)
# define PB1100_IRDA_TT (2<<14) /* 2/3 power */
# define PB1100_IRDA_OT (3<<14) /* 1/3 power */
# define PB1100_IRDA_FIR (1<<13)
#define PB1100_IRDA_RS232 0xAE00000C
# define PB1100_IRDA_FULL (0 << 14) /* full power */
# define PB1100_IRDA_SHUTDOWN (1 << 14)
# define PB1100_IRDA_TT (2 << 14) /* 2/3 power */
# define PB1100_IRDA_OT (3 << 14) /* 1/3 power */
# define PB1100_IRDA_FIR (1 << 13)
#define PCMCIA_BOARD_REG 0xAE000010
# define PB1100_SD_WP1_RO (1<<15) /* read only */
# define PB1100_SD_WP0_RO (1<<14) /* read only */
# define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */
# define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */
# define PB1100_SEL_SD_CONN1 (1<<9)
# define PB1100_SEL_SD_CONN0 (1<<8)
# define PC_DEASSERT_RST (1<<7)
# define PC_DRV_EN (1<<4)
#define PCMCIA_BOARD_REG 0xAE000010
# define PB1100_SD_WP1_RO (1 << 15) /* read only */
# define PB1100_SD_WP0_RO (1 << 14) /* read only */
# define PB1100_SD_PWR1 (1 << 11) /* applies power to SD1 */
# define PB1100_SD_PWR0 (1 << 10) /* applies power to SD0 */
# define PB1100_SEL_SD_CONN1 (1 << 9)
# define PB1100_SEL_SD_CONN0 (1 << 8)
# define PC_DEASSERT_RST (1 << 7)
# define PC_DRV_EN (1 << 4)
#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
#define PB1100_RST_VDDI 0xAE00001C
# define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */
# define PB1100_VDDI_MASK (0x1F)
#define PB1100_RST_VDDI 0xAE00001C
# define PB1100_SOFT_RESET (1 << 15) /* clear to reset the board */
# define PB1100_VDDI_MASK 0x1F
#define PB1100_LEDS 0xAE000018
#define PB1100_LEDS 0xAE000018
/* 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
* 7:0 is the LED Display's decimal points.
/*
* 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
* 7:0 is the LED Display's decimal points.
*/
#define PB1100_HEX_LED 0xAE000018
#define PB1100_HEX_LED 0xAE000018
/* PCMCIA PB1100 specific defines */
#define PCMCIA_MAX_SOCK 0
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
/* PCMCIA Pb1100 specific defines */
#define PCMCIA_MAX_SOCK 0
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0))
#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
#endif /* __ASM_PB1100_H */
include/asm-mips/mach-pb1x00/pb1200.h
+46 -47
View File
@@ -1,5 +1,5 @@
/*
* AMD Alchemy PB1200 Referrence Board
* AMD Alchemy Pb1200 Referrence Board
* Board Registers defines.
*
* ########################################################################
@@ -27,21 +27,20 @@
#include <linux/types.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
// This is defined in au1000.h with bogus value
#undef AU1X00_EXTERNAL_INT
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
/* SPI and SMB are muxed on the Pb1200 board.
Refer to board documentation.
/*
* SPI and SMB are muxed on the Pb1200 board.
* Refer to board documentation.
*/
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define SMBUS_PSC_BASE PSC0_BASE_ADDR
/* AC97 and I2S are muxed on the Pb1200 board.
Refer to board documentation.
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define SMBUS_PSC_BASE PSC0_BASE_ADDR
/*
* AC97 and I2S are muxed on the Pb1200 board.
* Refer to board documentation.
*/
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define I2S_PSC_BASE PSC1_BASE_ADDR
@@ -102,10 +101,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_STATUS_SWAPBOOT 0x0040
#define BCSR_STATUS_FLASHBUSY 0x0100
#define BCSR_STATUS_IDECBLID 0x0200
#define BCSR_STATUS_SD0WP 0x0400
#define BCSR_STATUS_SD1WP 0x0800
#define BCSR_STATUS_U0RXD 0x1000
#define BCSR_STATUS_U1RXD 0x2000
#define BCSR_STATUS_SD0WP 0x0400
#define BCSR_STATUS_SD1WP 0x0800
#define BCSR_STATUS_U0RXD 0x1000
#define BCSR_STATUS_U1RXD 0x2000
#define BCSR_SWITCHES_OCTAL 0x00FF
#define BCSR_SWITCHES_DIP_1 0x0080
@@ -123,11 +122,11 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_RESETS_DC 0x0004
#define BCSR_RESETS_IDE 0x0008
/* not resets but in the same register */
#define BCSR_RESETS_WSCFSM 0x0800
#define BCSR_RESETS_WSCFSM 0x0800
#define BCSR_RESETS_PCS0MUX 0x1000
#define BCSR_RESETS_PCS1MUX 0x2000
#define BCSR_RESETS_SPISEL 0x4000
#define BCSR_RESETS_SD1MUX 0x8000
#define BCSR_RESETS_SD1MUX 0x8000
#define BCSR_PCMCIA_PC0VPP 0x0003
#define BCSR_PCMCIA_PC0VCC 0x000C
@@ -163,7 +162,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_INT_PC0STSCHG 0x0008
#define BCSR_INT_PC1 0x0010
#define BCSR_INT_PC1STSCHG 0x0020
#define BCSR_INT_DC 0x0040
#define BCSR_INT_DC 0x0040
#define BCSR_INT_FLASHBUSY 0x0080
#define BCSR_INT_PC0INSERT 0x0100
#define BCSR_INT_PC0EJECT 0x0200
@@ -174,14 +173,6 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_INT_SD1INSERT 0x4000
#define BCSR_INT_SD1EJECT 0x8000
/* PCMCIA Db1x00 specific defines */
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP, SLOT)\
((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
#define SMC91C111_PHYS_ADDR 0x0D000300
#define SMC91C111_INT PB1200_ETH_INT
@@ -192,18 +183,19 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
#define IDE_RQSIZE 128
#define NAND_PHYS_ADDR 0x1C000000
#define NAND_PHYS_ADDR 0x1C000000
/* Timing values as described in databook, * ns value stripped of
/*
* Timing values as described in databook, * ns value stripped of
* lower 2 bits.
* These defines are here rather than an SOC1200 generic file because
* These defines are here rather than an Au1200 generic file because
* the parts chosen on another board may be different and may require
* different timings.
*/
#define NAND_T_H (18 >> 2)
#define NAND_T_PUL (30 >> 2)
#define NAND_T_SU (30 >> 2)
#define NAND_T_WH (30 >> 2)
#define NAND_T_H (18 >> 2)
#define NAND_T_PUL (30 >> 2)
#define NAND_T_SU (30 >> 2)
#define NAND_T_WH (30 >> 2)
/* Bitfield shift amounts */
#define NAND_T_H_SHIFT 0
@@ -211,11 +203,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define NAND_T_SU_SHIFT 8
#define NAND_T_WH_SHIFT 12
#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
/*
* External Interrupts for Pb1200 as of 8/6/2004.
@@ -248,13 +239,21 @@ enum external_pb1200_ints {
PB1200_INT_END = PB1200_INT_BEGIN + 15
};
/* For drivers/pcmcia/au1000_db1x00.c */
#define BOARD_PC0_INT PB1200_PC0_INT
#define BOARD_PC1_INT PB1200_PC1_INT
#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
/*
* Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
*/
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* Nand chip select */
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP, SLOT) \
((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
#define BOARD_PC0_INT PB1200_PC0_INT
#define BOARD_PC1_INT PB1200_PC1_INT
#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
/* NAND chip select */
#define NAND_CS 1
#endif /* __ASM_PB1200_H */
include/asm-mips/mach-pb1x00/pb1500.h
+18 -20
View File
@@ -1,9 +1,8 @@
/*
* Alchemy Semi PB1500 Referrence Board
* Alchemy Semi Pb1500 Referrence Board
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* ########################################################################
*
@@ -27,25 +26,24 @@
#ifndef __ASM_PB1500_H
#define __ASM_PB1500_H
#define IDENT_BOARD_REG 0xAE000000
#define BOARD_STATUS_REG 0xAE000004
#define PCI_BOARD_REG 0xAE000010
#define PCMCIA_BOARD_REG 0xAE000010
# define PC_DEASSERT_RST 0x80
# define PC_DRV_EN 0x10
#define PB1500_G_CONTROL 0xAE000014
#define PB1500_RST_VDDI 0xAE00001C
#define PB1500_LEDS 0xAE000018
#define IDENT_BOARD_REG 0xAE000000
#define BOARD_STATUS_REG 0xAE000004
#define PCI_BOARD_REG 0xAE000010
#define PCMCIA_BOARD_REG 0xAE000010
#define PC_DEASSERT_RST 0x80
#define PC_DRV_EN 0x10
#define PB1500_G_CONTROL 0xAE000014
#define PB1500_RST_VDDI 0xAE00001C
#define PB1500_LEDS 0xAE000018
#define PB1500_HEX_LED 0xAF000004
#define PB1500_HEX_LED_BLANK 0xAF000008
#define PB1500_HEX_LED 0xAF000004
#define PB1500_HEX_LED_BLANK 0xAF000008
/* PCMCIA PB1500 specific defines */
#define PCMCIA_MAX_SOCK 0
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
/* PCMCIA Pb1500 specific defines */
#define PCMCIA_MAX_SOCK 0
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0))
#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
#endif /* __ASM_PB1500_H */
include/asm-mips/mach-pb1x00/pb1550.h
+26 -25
View File
@@ -30,15 +30,15 @@
#include <linux/types.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define SMBUS_PSC_BASE PSC2_BASE_ADDR
#define I2S_PSC_BASE PSC3_BASE_ADDR
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define SMBUS_PSC_BASE PSC2_BASE_ADDR
#define I2S_PSC_BASE PSC3_BASE_ADDR
#define BCSR_PHYS_ADDR 0xAF000000
@@ -129,12 +129,12 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
#define BCSR_SYSTEM_POWEROFF 0x4000
#define BCSR_SYSTEM_RESET 0x8000
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP, SLOT)\
((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
#define SET_VCC_VPP(VCC, VPP, SLOT) \
((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
#define PB1550_BOTH_BANKS
@@ -144,16 +144,17 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
#define PB1550_USER_ONLY
#endif
/* Timing values as described in databook, * ns value stripped of
/*
* Timing values as described in databook, * ns value stripped of
* lower 2 bits.
* These defines are here rather than an SOC1550 generic file because
* the parts chosen on another board may be different and may require
* different timings.
*/
#define NAND_T_H (18 >> 2)
#define NAND_T_PUL (30 >> 2)
#define NAND_T_SU (30 >> 2)
#define NAND_T_WH (30 >> 2)
#define NAND_T_H (18 >> 2)
#define NAND_T_PUL (30 >> 2)
#define NAND_T_SU (30 >> 2)
#define NAND_T_WH (30 >> 2)
/* Bitfield shift amounts */
#define NAND_T_H_SHIFT 0
@@ -161,16 +162,16 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
#define NAND_T_SU_SHIFT 8
#define NAND_T_WH_SHIFT 12
#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
#define NAND_CS 1
/* should be done by yamon */
#define NAND_STCFG 0x00400005 /* 8-bit NAND */
#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */
#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
/* Should be done by YAMON */
#define NAND_STCFG 0x00400005 /* 8-bit NAND */
#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
#endif /* __ASM_PB1550_H */
include/asm-mips/rtlx.h
+2 -2
View File
@@ -29,13 +29,13 @@ extern unsigned int rtlx_read_poll(int index, int can_sleep);
extern unsigned int rtlx_write_poll(int index);
enum rtlx_state {
RTLX_STATE_UNUSED,
RTLX_STATE_UNUSED = 0,
RTLX_STATE_INITIALISED,
RTLX_STATE_REMOTE_READY,
RTLX_STATE_OPENED
};
#define RTLX_BUFFER_SIZE 1024
#define RTLX_BUFFER_SIZE 2048
/* each channel supports read and write.
linux (vpe0) reads lx_buffer and writes rt_buffer
include/asm-mn10300/processor.h
+1 -1
View File
@@ -58,7 +58,7 @@ extern struct mn10300_cpuinfo boot_cpu_data;
extern void identify_cpu(struct mn10300_cpuinfo *);
extern void print_cpu_info(struct mn10300_cpuinfo *);
extern void dodgy_tsc(void);
#define cpu_relax() do {} while (0)
#define cpu_relax() barrier()
/*
* User space process size: 1.75GB (default).
include/asm-powerpc/io.h
+7 -1
View File
@@ -2,7 +2,7 @@
#define _ASM_POWERPC_IO_H
#ifdef __KERNEL__
/*
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
@@ -18,6 +18,9 @@ extern int check_legacy_ioport(unsigned long base_port);
#define _PNPWRP 0xa79
#define PNPBIOS_BASE 0xf000
#include <linux/device.h>
#include <linux/io.h>
#include <linux/compiler.h>
#include <asm/page.h>
#include <asm/byteorder.h>
@@ -744,6 +747,9 @@ static inline void * bus_to_virt(unsigned long address)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
void __iomem *devm_ioremap_prot(struct device *dev, resource_size_t offset,
size_t size, unsigned long flags);
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_IO_H */
include/asm-powerpc/pgtable-ppc32.h
+7
View File
@@ -209,6 +209,13 @@ extern int icache_44x_need_flush;
* 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
* - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
*
* Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
* TLB2 storage attibute fields. Those are:
*
* TLB2:
* 0...10 11 12 13 14 15 16...31
* no change WL1 IL1I IL1D IL2I IL2D no change
*
* There are some constrains and options, to decide mapping software bits
* into TLB entry.
*
include/asm-powerpc/spu.h
+6 -3
View File
@@ -100,6 +100,7 @@
/* Flag indicating progress during context switch. */
#define SPU_CONTEXT_SWITCH_PENDING 0UL
#define SPU_CONTEXT_FAULT_PENDING 1UL
struct spu_context;
struct spu_runqueue;
@@ -128,9 +129,11 @@ struct spu {
unsigned int irqs[3];
u32 node;
u64 flags;
u64 dar;
u64 dsisr;
u64 class_0_pending;
u64 class_0_dar;
u64 class_0_dsisr;
u64 class_1_dar;
u64 class_1_dsisr;
size_t ls_size;
unsigned int slb_replace;
struct mm_struct *mm;
@@ -143,7 +146,7 @@ struct spu {
void (* wbox_callback)(struct spu *spu);
void (* ibox_callback)(struct spu *spu);
void (* stop_callback)(struct spu *spu);
void (* stop_callback)(struct spu *spu, int irq);
void (* mfc_callback)(struct spu *spu);
char irq_c0[8];
include/asm-powerpc/spu_csa.h
+2 -1
View File
@@ -254,7 +254,8 @@ struct spu_state {
u64 spu_chnldata_RW[32];
u32 spu_mailbox_data[4];
u32 pu_mailbox_data[1];
u64 dar, dsisr, class_0_pending;
u64 class_0_dar, class_0_dsisr, class_0_pending;
u64 class_1_dar, class_1_dsisr;
unsigned long suspend_time;
spinlock_t register_lock;
};
include/asm-ppc/system.h
+1 -1
View File
@@ -178,7 +178,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
}
extern inline void * xchg_ptr(void * m, void * val)
static inline void * xchg_ptr(void * m, void * val)
{
return (void *) xchg_u32(m, (unsigned long) val);
}
include/asm-s390/kvm_host.h
+1
View File
@@ -104,6 +104,7 @@ struct sie_block {
struct kvm_vcpu_stat {
u32 exit_userspace;
u32 exit_null;
u32 exit_external_request;
u32 exit_external_interrupt;
u32 exit_stop_request;
include/asm-s390/page.h
+11
View File
@@ -125,6 +125,17 @@ page_get_storage_key(unsigned long addr)
return skey;
}
#ifdef CONFIG_PAGE_STATES
struct page;
void arch_free_page(struct page *page, int order);
void arch_alloc_page(struct page *page, int order);
#define HAVE_ARCH_FREE_PAGE
#define HAVE_ARCH_ALLOC_PAGE
#endif
#endif /* !__ASSEMBLY__ */
/* to align the pointer to the (next) page boundary */
include/asm-s390/ptrace.h
+2
View File
@@ -471,6 +471,8 @@ struct task_struct;
extern void user_enable_single_step(struct task_struct *);
extern void user_disable_single_step(struct task_struct *);
#define __ARCH_WANT_COMPAT_SYS_PTRACE
#define user_mode(regs) (((regs)->psw.mask & PSW_MASK_PSTATE) != 0)
#define instruction_pointer(regs) ((regs)->psw.addr & PSW_ADDR_INSN)
#define regs_return_value(regs)((regs)->gprs[2])
include/asm-s390/system.h
+6
View File
@@ -116,6 +116,12 @@ extern void pfault_fini(void);
#define pfault_fini() do { } while (0)
#endif /* CONFIG_PFAULT */
#ifdef CONFIG_PAGE_STATES
extern void cmma_init(void);
#else
static inline void cmma_init(void) { }
#endif
#define finish_arch_switch(prev) do { \
set_fs(current->thread.mm_segment); \
account_vtime(prev); \
include/asm-s390/types.h
+2 -2
View File
@@ -10,9 +10,9 @@
#define _S390_TYPES_H
#ifndef __s390x__
# include <asm-generic/int-l64.h>
#else
# include <asm-generic/int-ll64.h>
#else
# include <asm-generic/int-l64.h>
#endif
#ifndef __ASSEMBLY__
include/asm-sh/cpu-sh3/dma.h
+5 -5
View File
@@ -3,19 +3,19 @@
#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
defined(CONFIG_CPU_SUBTYPE_SH7721)
#define SH_DMAC_BASE 0xa4010020
#else
#define SH_DMAC_BASE 0xa4000020
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
#define DMTE0_IRQ 48
#define DMTE1_IRQ 49
#define DMTE2_IRQ 50
#define DMTE3_IRQ 51
#define DMTE4_IRQ 76
#define DMTE5_IRQ 77
#else
#define SH_DMAC_BASE 0xa4000020
#endif
/* Definitions for the SuperH DMAC */
include/asm-sh/hw_irq.h
+19
View File
@@ -79,6 +79,10 @@ struct intc_desc {
struct intc_sense_reg *sense_regs;
unsigned int nr_sense_regs;
char *name;
#ifdef CONFIG_CPU_SH3
struct intc_mask_reg *ack_regs;
unsigned int nr_ack_regs;
#endif
};
#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
@@ -91,10 +95,25 @@ struct intc_desc symbol __initdata = { \
chipname, \
}
#ifdef CONFIG_CPU_SH3
#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups, \
mask_regs, prio_regs, sense_regs, ack_regs) \
struct intc_desc symbol __initdata = { \
_INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
_INTC_ARRAY(sense_regs), \
chipname, \
_INTC_ARRAY(ack_regs), \
}
#endif
void __init register_intc_controller(struct intc_desc *desc);
int intc_set_priority(unsigned int irq, unsigned int prio);
void __init plat_irq_setup(void);
#ifdef CONFIG_CPU_SH3
void __init plat_irq_setup_sh3(void);
#endif
enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
include/asm-sh/io.h
+7 -5
View File
@@ -268,11 +268,6 @@ unsigned long long peek_real_address_q(unsigned long long addr);
unsigned long long poke_real_address_q(unsigned long long addr,
unsigned long long val);
/* arch/sh/mm/ioremap_64.c */
unsigned long onchip_remap(unsigned long addr, unsigned long size,
const char *name);
extern void onchip_unmap(unsigned long vaddr);
#if !defined(CONFIG_MMU)
#define virt_to_phys(address) ((unsigned long)(address))
#define phys_to_virt(address) ((void *)(address))
@@ -302,9 +297,16 @@ extern void onchip_unmap(unsigned long vaddr);
void __iomem *__ioremap(unsigned long offset, unsigned long size,
unsigned long flags);
void __iounmap(void __iomem *addr);
/* arch/sh/mm/ioremap_64.c */
unsigned long onchip_remap(unsigned long addr, unsigned long size,
const char *name);
extern void onchip_unmap(unsigned long vaddr);
#else
#define __ioremap(offset, size, flags) ((void __iomem *)(offset))
#define __iounmap(addr) do { } while (0)
#define onchip_remap(addr, size, name) (addr)
#define onchip_unmap(addr) do { } while (0)
#endif /* CONFIG_MMU */
static inline void __iomem *
include/asm-sh/keyboard.h
-13
View File
@@ -1,13 +0,0 @@
#ifndef __ASM_SH_KEYBOARD_H
#define __ASM_SH_KEYBOARD_H
/*
* $Id: keyboard.h,v 1.1.1.1 2001/10/15 20:45:09 mrbrown Exp $
*/
#include <linux/kd.h>
#include <asm/machvec.h>
#ifdef CONFIG_SH_MPC1211
#include <asm/mpc1211/keyboard-mpc1211.h>
#endif
#endif
include/asm-sh/mmu_context.h
+3 -1
View File
@@ -27,6 +27,7 @@
/* ASID is 8-bit value, so it can't be 0x100 */
#define MMU_NO_ASID 0x100
#ifdef CONFIG_MMU
#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
#define cpu_context(cpu, mm) ((mm)->context.id[cpu])
@@ -38,7 +39,6 @@
*/
#define MMU_VPN_MASK 0xfffff000
#ifdef CONFIG_MMU
#if defined(CONFIG_SUPERH32)
#include "mmu_context_32.h"
#else
@@ -129,6 +129,8 @@ static inline void switch_mm(struct mm_struct *prev,
#define destroy_context(mm) do { } while (0)
#define set_asid(asid) do { } while (0)
#define get_asid() (0)
#define cpu_asid(cpu, mm) ({ (void)cpu; 0; })
#define switch_and_save_asid(asid) (0)
#define set_TTB(pgd) do { } while (0)
#define get_TTB() (0)
#define activate_context(mm,cpu) do { } while (0)
include/asm-sh/mmzone.h
+2
View File
@@ -41,6 +41,8 @@ void __init plat_mem_setup(void);
/* arch/sh/kernel/setup.c */
void __init setup_bootmem_allocator(unsigned long start_pfn);
void __init __add_active_range(unsigned int nid, unsigned long start_pfn,
unsigned long end_pfn);
#endif /* __KERNEL__ */
#endif /* __ASM_SH_MMZONE_H */
include/asm-sh/mpc1211/dma.h
-303
View File
@@ -1,303 +0,0 @@
/* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
* linux/include/asm/dma.h: Defines for using and allocating dma channels.
* Written by Hennus Bergman, 1992.
* High DMA channel support & info by Hannu Savolainen
* and John Boyd, Nov. 1992.
*/
#ifndef _ASM_MPC1211_DMA_H
#define _ASM_MPC1211_DMA_H
#include <linux/spinlock.h> /* And spinlocks */
#include <asm/io.h> /* need byte IO */
#include <linux/delay.h>
#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
#define dma_outb outb_p
#else
#define dma_outb outb
#endif
#define dma_inb inb
/*
* NOTES about DMA transfers:
*
* controller 1: channels 0-3, byte operations, ports 00-1F
* controller 2: channels 4-7, word operations, ports C0-DF
*
* - ALL registers are 8 bits only, regardless of transfer size
* - channel 4 is not used - cascades 1 into 2.
* - channels 0-3 are byte - addresses/counts are for physical bytes
* - channels 5-7 are word - addresses/counts are for physical words
* - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
* - transfer count loaded to registers is 1 less than actual count
* - controller 2 offsets are all even (2x offsets for controller 1)
* - page registers for 5-7 don't use data bit 0, represent 128K pages
* - page registers for 0-3 use bit 0, represent 64K pages
*
* DMA transfers are limited to the lower 16MB of _physical_ memory.
* Note that addresses loaded into registers must be _physical_ addresses,
* not logical addresses (which may differ if paging is active).
*
* Address mapping for channels 0-3:
*
* A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
* | ... | | ... | | ... |
* | ... | | ... | | ... |
* | ... | | ... | | ... |
* P7 ... P0 A7 ... A0 A7 ... A0
* | Page | Addr MSB | Addr LSB | (DMA registers)
*
* Address mapping for channels 5-7:
*
* A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
* | ... | \ \ ... \ \ \ ... \ \
* | ... | \ \ ... \ \ \ ... \ (not used)
* | ... | \ \ ... \ \ \ ... \
* P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
* | Page | Addr MSB | Addr LSB | (DMA registers)
*
* Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
* and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
* the hardware level, so odd-byte transfers aren't possible).
*
* Transfer count (_not # bytes_) is limited to 64K, represented as actual
* count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
* and up to 128K bytes may be transferred on channels 5-7 in one operation.
*
*/
#define MAX_DMA_CHANNELS 8
/* The maximum address that we can perform a DMA transfer to on this platform */
#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
/* 8237 DMA controllers */
#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
/* DMA controller registers */
#define DMA1_CMD_REG 0x08 /* command register (w) */
#define DMA1_STAT_REG 0x08 /* status register (r) */
#define DMA1_REQ_REG 0x09 /* request register (w) */
#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
#define DMA1_MODE_REG 0x0B /* mode register (w) */
#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
#define DMA2_CMD_REG 0xD0 /* command register (w) */
#define DMA2_STAT_REG 0xD0 /* status register (r) */
#define DMA2_REQ_REG 0xD2 /* request register (w) */
#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
#define DMA2_MODE_REG 0xD6 /* mode register (w) */
#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
#define DMA_ADDR_0 0x00 /* DMA address registers */
#define DMA_ADDR_1 0x02
#define DMA_ADDR_2 0x04
#define DMA_ADDR_3 0x06
#define DMA_ADDR_4 0xC0
#define DMA_ADDR_5 0xC4
#define DMA_ADDR_6 0xC8
#define DMA_ADDR_7 0xCC
#define DMA_CNT_0 0x01 /* DMA count registers */
#define DMA_CNT_1 0x03
#define DMA_CNT_2 0x05
#define DMA_CNT_3 0x07
#define DMA_CNT_4 0xC2
#define DMA_CNT_5 0xC6
#define DMA_CNT_6 0xCA
#define DMA_CNT_7 0xCE
#define DMA_PAGE_0 0x87 /* DMA page registers */
#define DMA_PAGE_1 0x83
#define DMA_PAGE_2 0x81
#define DMA_PAGE_3 0x82
#define DMA_PAGE_5 0x8B
#define DMA_PAGE_6 0x89
#define DMA_PAGE_7 0x8A
#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
#define DMA_AUTOINIT 0x10
extern spinlock_t dma_spin_lock;
static __inline__ unsigned long claim_dma_lock(void)
{
unsigned long flags;
spin_lock_irqsave(&dma_spin_lock, flags);
return flags;
}
static __inline__ void release_dma_lock(unsigned long flags)
{
spin_unlock_irqrestore(&dma_spin_lock, flags);
}
/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
if (dmanr<=3)
dma_outb(dmanr, DMA1_MASK_REG);
else
dma_outb(dmanr & 3, DMA2_MASK_REG);
}
static __inline__ void disable_dma(unsigned int dmanr)
{
if (dmanr<=3)
dma_outb(dmanr | 4, DMA1_MASK_REG);
else
dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
}
/* Clear the 'DMA Pointer Flip Flop'.
* Write 0 for LSB/MSB, 1 for MSB/LSB access.
* Use this once to initialize the FF to a known state.
* After that, keep track of it. :-)
* --- In order to do that, the DMA routines below should ---
* --- only be used while holding the DMA lock ! ---
*/
static __inline__ void clear_dma_ff(unsigned int dmanr)
{
if (dmanr<=3)
dma_outb(0, DMA1_CLEAR_FF_REG);
else
dma_outb(0, DMA2_CLEAR_FF_REG);
}
/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{
if (dmanr<=3)
dma_outb(mode | dmanr, DMA1_MODE_REG);
else
dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
}
/* Set only the page register bits of the transfer address.
* This is used for successive transfers when we know the contents of
* the lower 16 bits of the DMA current address register, but a 64k boundary
* may have been crossed.
*/
static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
{
switch(dmanr) {
case 0:
dma_outb( pagenr & 0xff, DMA_PAGE_0);
dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_0 + 0x400);
break;
case 1:
dma_outb( pagenr & 0xff, DMA_PAGE_1);
dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_1 + 0x400);
break;
case 2:
dma_outb( pagenr & 0xff, DMA_PAGE_2);
dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_2 + 0x400);
break;
case 3:
dma_outb( pagenr & 0xff, DMA_PAGE_3);
dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_3 + 0x400);
break;
case 5:
dma_outb( pagenr & 0xfe, DMA_PAGE_5);
dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_5 + 0x400);
break;
case 6:
dma_outb( pagenr & 0xfe, DMA_PAGE_6);
dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_6 + 0x400);
break;
case 7:
dma_outb( pagenr & 0xfe, DMA_PAGE_7);
dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_7 + 0x400);
break;
}
}
/* Set transfer address & page bits for specific DMA channel.
* Assumes dma flipflop is clear.
*/
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
{
set_dma_page(dmanr, a>>16);
if (dmanr <= 3) {
dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
} else {
dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
}
}
/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
* a specific DMA channel.
* You must ensure the parameters are valid.
* NOTE: from a manual: "the number of transfers is one more
* than the initial word count"! This is taken into account.
* Assumes dma flip-flop is clear.
* NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
*/
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
count--;
if (dmanr <= 3) {
dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
} else {
dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
}
}
/* Get DMA residue count. After a DMA transfer, this
* should return zero. Reading this while a DMA transfer is
* still in progress will return unpredictable results.
* If called before the channel has been used, it may return 1.
* Otherwise, it returns the number of _bytes_ left to transfer.
*
* Assumes DMA flip-flop is clear.
*/
static __inline__ int get_dma_residue(unsigned int dmanr)
{
unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
: ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
/* using short to get 16-bit wrap around */
unsigned short count;
count = 1 + dma_inb(io_port);
count += dma_inb(io_port) << 8;
return (dmanr<=3)? count : (count<<1);
}
/* These are in kernel/dma.c: */
extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
extern void free_dma(unsigned int dmanr); /* release it again */
/* From PCI */
#ifdef CONFIG_PCI
extern int isa_dma_bridge_buggy;
#else
#define isa_dma_bridge_buggy (0)
#endif
#endif /* _ASM_MPC1211_DMA_H */
include/asm-sh/mpc1211/io.h
-22
View File
@@ -1,22 +0,0 @@
/*
* include/asm-sh/mpc1211/io.h
*
* Copyright 2001 Saito.K & Jeanne
*
* IO functions for an Interface MPC-1211
*/
#ifndef _ASM_SH_IO_MPC1211_H
#define _ASM_SH_IO_MPC1211_H
#include <linux/time.h>
extern int mpc1211_irq_demux(int irq);
extern void init_mpc1211_IRQ(void);
extern void heartbeat_mpc1211(void);
extern void mpc1211_rtc_gettimeofday(struct timeval *tv);
extern int mpc1211_rtc_settimeofday(const struct timeval *tv);
#endif /* _ASM_SH_IO_MPC1211_H */
include/asm-sh/mpc1211/keyboard.h
-60
View File
@@ -1,60 +0,0 @@
/*
* MPC1211 specific keybord definitions
* Taken from the old asm-i386/keybord.h for PC/AT-style definitions
* created 3 Nov 1996 by Geert Uytterhoeven.
*/
#ifdef __KERNEL__
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/kd.h>
#include <linux/pm.h>
#include <asm/io.h>
#define KEYBOARD_IRQ 1
#define DISABLE_KBD_DURING_INTERRUPTS 0
extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
extern int pckbd_getkeycode(unsigned int scancode);
extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
char raw_mode);
extern char pckbd_unexpected_up(unsigned char keycode);
extern void pckbd_leds(unsigned char leds);
extern void pckbd_init_hw(void);
extern int pckbd_pm_resume(struct pm_dev *, pm_request_t, void *);
extern pm_callback pm_kbd_request_override;
#define kbd_setkeycode pckbd_setkeycode
#define kbd_getkeycode pckbd_getkeycode
#define kbd_translate pckbd_translate
#define kbd_unexpected_up pckbd_unexpected_up
#define kbd_leds pckbd_leds
#define kbd_init_hw pckbd_init_hw
/* resource allocation */
#define kbd_request_region()
#define kbd_request_irq(handler) request_irq(KEYBOARD_IRQ, handler, 0, \
"keyboard", NULL)
/* How to access the keyboard macros on this platform. */
#define kbd_read_input() inb(KBD_DATA_REG)
#define kbd_read_status() inb(KBD_STATUS_REG)
#define kbd_write_output(val) outb(val, KBD_DATA_REG)
#define kbd_write_command(val) outb(val, KBD_CNTL_REG)
/* Some stoneage hardware needs delays after some operations. */
#define kbd_pause() do { } while(0)
/*
* Machine specific bits for the PS/2 driver
*/
#define AUX_IRQ 12
#define aux_request_irq(hand, dev_id) \
request_irq(AUX_IRQ, hand, IRQF_SHARED, "PS2 Mouse", dev_id)
#define aux_free_irq(dev_id) free_irq(AUX_IRQ, dev_id)
#endif /* __KERNEL__ */
include/asm-sh/mpc1211/m1543c.h
-200
View File
@@ -1,200 +0,0 @@
#ifndef __ASM_SH_M1543C_H
#define __ASM_SH_M1543C_H
/*
* linux/include/asm-sh/m1543c.h
* Copyright (C) 2001 Nobuhiro Sakawa
* M1543C:PCI-ISA Bus Bridge with Super IO Chip support
*
* from
*
* linux/include/asm-sh/smc37c93x.h
*
* Copyright (C) 2000 Kazumoto Kojima
*
* SMSC 37C93x Super IO Chip support
*/
/* Default base I/O address */
#define FDC_PRIMARY_BASE 0x3f0
#define IDE1_PRIMARY_BASE 0x1f0
#define IDE1_SECONDARY_BASE 0x170
#define PARPORT_PRIMARY_BASE 0x378
#define COM1_PRIMARY_BASE 0x2f8
#define COM2_PRIMARY_BASE 0x3f8
#define COM3_PRIMARY_BASE 0x3e8
#define RTC_PRIMARY_BASE 0x070
#define KBC_PRIMARY_BASE 0x060
#define AUXIO_PRIMARY_BASE 0x000 /* XXX */
#define I8259_M_CR 0x20
#define I8259_M_MR 0x21
#define I8259_S_CR 0xa0
#define I8259_S_MR 0xa1
/* Logical device number */
#define LDN_FDC 0
#define LDN_IDE1 1
#define LDN_IDE2 2
#define LDN_PARPORT 3
#define LDN_COM1 4
#define LDN_COM2 5
#define LDN_COM3 11
#define LDN_RTC 6
#define LDN_KBC 7
/* Configuration port and key */
#define CONFIG_PORT 0x3f0
#define INDEX_PORT CONFIG_PORT
#define DATA_PORT 0x3f1
#define CONFIG_ENTER1 0x51
#define CONFIG_ENTER2 0x23
#define CONFIG_EXIT 0xbb
/* Configuration index */
#define CURRENT_LDN_INDEX 0x07
#define POWER_CONTROL_INDEX 0x22
#define ACTIVATE_INDEX 0x30
#define IO_BASE_HI_INDEX 0x60
#define IO_BASE_LO_INDEX 0x61
#define IRQ_SELECT_INDEX 0x70
#define PS2_IRQ_INDEX 0x72
#define DMA_SELECT_INDEX 0x74
/* UART stuff. Only for debugging. */
/* UART Register */
#define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */
#define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */
#define UART_IER 0x2 /* Interrupt Enable Register */
#define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */
#define UART_FCR 0x4 /* FIFO Control Register (Write Only) */
#define UART_LCR 0x6 /* Line Control Register */
#define UART_MCR 0x8 /* MODEM Control Register */
#define UART_LSR 0xa /* Line Status Register */
#define UART_MSR 0xc /* MODEM Status Register */
#define UART_SCR 0xe /* Scratch Register */
#define UART_DLL 0x0 /* Divisor Latch (LS) */
#define UART_DLM 0x2 /* Divisor Latch (MS) */
#ifndef __ASSEMBLY__
typedef struct uart_reg {
volatile __u16 rbr;
volatile __u16 ier;
volatile __u16 iir;
volatile __u16 lcr;
volatile __u16 mcr;
volatile __u16 lsr;
volatile __u16 msr;
volatile __u16 scr;
} uart_reg;
#endif /* ! __ASSEMBLY__ */
/* Alias for Write Only Register */
#define thr rbr
#define tcr iir
/* Alias for Divisor Latch Register */
#define dll rbr
#define dlm ier
#define fcr iir
/* Interrupt Enable Register */
#define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */
#define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */
#define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */
#define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */
/* Interrupt Ident Register */
#define IIR_IP 0x0100 /* "0" if Interrupt Pending */
#define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */
#define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */
#define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */
#define IIR_FIFO 0xc000 /* FIFOs enabled */
/* FIFO Control Register */
#define FCR_FEN 0x0100 /* FIFO enable */
#define FCR_RFRES 0x0200 /* Receiver FIFO reset */
#define FCR_TFRES 0x0400 /* Transmitter FIFO reset */
#define FCR_DMA 0x0800 /* DMA mode select */
#define FCR_RTL 0x4000 /* Receiver triger (LSB) */
#define FCR_RTM 0x8000 /* Receiver triger (MSB) */
/* Line Control Register */
#define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */
#define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */
#define LCR_STB 0x0400 /* Number of Stop Bits */
#define LCR_PEN 0x0800 /* Parity Enable */
#define LCR_EPS 0x1000 /* Even Parity Select */
#define LCR_SP 0x2000 /* Stick Parity */
#define LCR_SB 0x4000 /* Set Break */
#define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */
/* MODEM Control Register */
#define MCR_DTR 0x0100 /* Data Terminal Ready */
#define MCR_RTS 0x0200 /* Request to Send */
#define MCR_OUT1 0x0400 /* Out 1 */
#define MCR_IRQEN 0x0800 /* IRQ Enable */
#define MCR_LOOP 0x1000 /* Loop */
/* Line Status Register */
#define LSR_DR 0x0100 /* Data Ready */
#define LSR_OE 0x0200 /* Overrun Error */
#define LSR_PE 0x0400 /* Parity Error */
#define LSR_FE 0x0800 /* Framing Error */
#define LSR_BI 0x1000 /* Break Interrupt */
#define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */
#define LSR_TEMT 0x4000 /* Transmitter Empty */
#define LSR_FIFOE 0x8000 /* Receiver FIFO error */
/* MODEM Status Register */
#define MSR_DCTS 0x0100 /* Delta Clear to Send */
#define MSR_DDSR 0x0200 /* Delta Data Set Ready */
#define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */
#define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */
#define MSR_CTS 0x1000 /* Clear to Send */
#define MSR_DSR 0x2000 /* Data Set Ready */
#define MSR_RI 0x4000 /* Ring Indicator */
#define MSR_DCD 0x8000 /* Data Carrier Detect */
/* Baud Rate Divisor */
#define UART_CLK (1843200) /* 1.8432 MHz */
#define UART_BAUD(x) (UART_CLK / (16 * (x)))
/* RTC register definition */
#define RTC_SECONDS 0
#define RTC_SECONDS_ALARM 1
#define RTC_MINUTES 2
#define RTC_MINUTES_ALARM 3
#define RTC_HOURS 4
#define RTC_HOURS_ALARM 5
#define RTC_DAY_OF_WEEK 6
#define RTC_DAY_OF_MONTH 7
#define RTC_MONTH 8
#define RTC_YEAR 9
#define RTC_FREQ_SELECT 10
# define RTC_UIP 0x80
# define RTC_DIV_CTL 0x70
/* This RTC can work under 32.768KHz clock only. */
# define RTC_OSC_ENABLE 0x20
# define RTC_OSC_DISABLE 0x00
#define RTC_CONTROL 11
# define RTC_SET 0x80
# define RTC_PIE 0x40
# define RTC_AIE 0x20
# define RTC_UIE 0x10
# define RTC_SQWE 0x08
# define RTC_DM_BINARY 0x04
# define RTC_24H 0x02
# define RTC_DST_EN 0x01
#endif /* __ASM_SH_M1543C_H */
include/asm-sh/mpc1211/mc146818rtc.h
-6
View File
@@ -1,6 +0,0 @@
/*
* MPC1211 uses PC/AT style RTC definitions.
*/
#include <asm-x86/mc146818rtc_32.h>
include/asm-sh/mpc1211/mpc1211.h
-18
View File
@@ -1,18 +0,0 @@
#ifndef __ASM_SH_MPC1211_H
#define __ASM_SH_MPC1211_H
/*
* linux/include/asm-sh/mpc1211.h
*
* Copyright (C) 2001 Saito.K & Jeanne
*
* Interface MPC-1211 support
*/
#define PA_PCI_IO (0xa4000000) /* PCI I/O space */
#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */
#define PCIPAR (0xa4000cf8) /* PCI Config address */
#define PCIPDR (0xa4000cfc) /* PCI Config data */
#endif /* __ASM_SH_MPC1211_H */
include/asm-sh/mpc1211/pci.h
-38
View File
@@ -1,38 +0,0 @@
/*
* Low-Level PCI Support for MPC-1211
*
* (c) 2002 Saito.K & Jeanne
*
*/
#ifndef _PCI_MPC1211_H_
#define _PCI_MPC1211_H_
#include <linux/pci.h>
/* set debug level 4=verbose...1=terse */
//#define DEBUG_PCI 3
#undef DEBUG_PCI
#ifdef DEBUG_PCI
#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); }
#else
#define PCIDBG(n, x...)
#endif
/* startup values */
#define PCI_PROBE_BIOS 1
#define PCI_PROBE_CONF1 2
#define PCI_PROBE_CONF2 4
#define PCI_NO_CHECKS 0x400
#define PCI_ASSIGN_ROMS 0x1000
#define PCI_BIOS_IRQ_SCAN 0x2000
/* MPC-1211 Specific Values */
#define PCIPAR (0xa4000cf8) /* PCI Config address */
#define PCIPDR (0xa4000cfc) /* PCI Config data */
#define PA_PCI_IO (0xa4000000) /* PCI I/O space */
#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */
#endif /* _PCI_MPC1211_H_ */
include/asm-sh/r7780rp.h
+1 -3
View File
@@ -193,8 +193,6 @@
#define IRQ_SCIF0 (HL_FPGA_IRQ_BASE + 15)
#define IRQ_SCIF1 (HL_FPGA_IRQ_BASE + 16)
unsigned char *highlander_init_irq_r7780mp(void);
unsigned char *highlander_init_irq_r7780rp(void);
unsigned char *highlander_init_irq_r7785rp(void);
unsigned char *highlander_plat_irq_setup(void);
#endif /* __ASM_SH_RENESAS_R7780RP */
include/asm-sh/tlb_64.h
+9 -1
View File
@@ -56,6 +56,7 @@ static inline void __flush_tlb_slot(unsigned long long slot)
__asm__ __volatile__ ("putcfg %0, 0, r63\n" : : "r" (slot));
}
#ifdef CONFIG_MMU
/* arch/sh64/mm/tlb.c */
int sh64_tlb_init(void);
unsigned long long sh64_next_free_dtlb_entry(void);
@@ -64,6 +65,13 @@ int sh64_put_wired_dtlb_entry(unsigned long long entry);
void sh64_setup_tlb_slot(unsigned long long config_addr, unsigned long eaddr,
unsigned long asid, unsigned long paddr);
void sh64_teardown_tlb_slot(unsigned long long config_addr);
#else
#define sh64_tlb_init() do { } while (0)
#define sh64_next_free_dtlb_entry() (0)
#define sh64_get_wired_dtlb_entry() (0)
#define sh64_put_wired_dtlb_entry(entry) do { } while (0)
#define sh64_setup_tlb_slot(conf, virt, asid, phys) do { } while (0)
#define sh64_teardown_tlb_slot(addr) do { } while (0)
#endif /* CONFIG_MMU */
#endif /* __ASSEMBLY__ */
#endif /* __ASM_SH_TLB_64_H */
include/asm-sh/topology.h
+11
View File
@@ -29,6 +29,17 @@
.nr_balance_failed = 0, \
}
#define cpu_to_node(cpu) ((void)(cpu),0)
#define parent_node(node) ((void)(node),0)
#define node_to_cpumask(node) ((void)node, cpu_online_map)
#define node_to_first_cpu(node) ((void)(node),0)
#define pcibus_to_node(bus) ((void)(bus), -1)
#define pcibus_to_cpumask(bus) (pcibus_to_node(bus) == -1 ? \
CPU_MASK_ALL : \
node_to_cpumask(pcibus_to_node(bus)) \
)
#endif
#include <asm-generic/topology.h>
include/asm-sh/uaccess_64.h
+2
View File
@@ -274,7 +274,9 @@ struct exception_table_entry
unsigned long insn, fixup;
};
#ifdef CONFIG_MMU
#define ARCH_HAS_SEARCH_EXTABLE
#endif
/* Returns 0 if exception not found and fixup.unit otherwise. */
extern unsigned long search_exception_table(unsigned long addr);
include/asm-sparc/mman.h
+2 -3
View File
@@ -24,9 +24,8 @@
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
#define arch_mmap_check sparc_mmap_check
int sparc_mmap_check(unsigned long addr, unsigned long len,
unsigned long flags);
#define arch_mmap_check(addr,len,flags) sparc_mmap_check(addr,len)
int sparc_mmap_check(unsigned long addr, unsigned long len);
#endif
#endif
include/asm-sparc/psr.h
+1
View File
@@ -25,6 +25,7 @@
#define PSR_PIL 0x00000f00 /* processor interrupt level */
#define PSR_EF 0x00001000 /* enable floating point */
#define PSR_EC 0x00002000 /* enable co-processor */
#define PSR_SYSCALL 0x00004000 /* inside of a syscall */
#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
#define PSR_ICC 0x00f00000 /* integer condition codes */
#define PSR_C 0x00100000 /* carry bit */
include/asm-sparc/ptrace.h
+13
View File
@@ -10,6 +10,8 @@
#ifndef __ASSEMBLY__
#include <linux/types.h>
struct pt_regs {
unsigned long psr;
unsigned long pc;
@@ -39,6 +41,16 @@ struct pt_regs {
#define UREG_FP UREG_I6
#define UREG_RETPC UREG_I7
static inline bool pt_regs_is_syscall(struct pt_regs *regs)
{
return (regs->psr & PSR_SYSCALL);
}
static inline bool pt_regs_clear_syscall(struct pt_regs *regs)
{
return (regs->psr &= ~PSR_SYSCALL);
}
/* A register window */
struct reg_window {
unsigned long locals[8];
@@ -149,6 +161,7 @@ extern void show_regs(struct pt_regs *);
#define SF_XXARG 0x5c
/* Stuff for the ptrace system call */
#define PTRACE_SPARC_DETACH 11
#define PTRACE_GETREGS 12
#define PTRACE_SETREGS 13
#define PTRACE_GETFPREGS 14
include/asm-sparc/signal.h
+1 -7
View File
@@ -199,13 +199,7 @@ typedef struct sigaltstack {
size_t ss_size;
} stack_t;
struct sparc_deliver_cookie {
int restart_syscall;
unsigned long orig_i0;
};
struct pt_regs;
extern void ptrace_signal_deliver(struct pt_regs *regs, void *cookie);
#define ptrace_signal_deliver(regs, cookie) do { } while (0)
#endif /* !(__KERNEL__) */
include/asm-sparc64/mman.h
+2 -3
View File
@@ -24,9 +24,8 @@
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
#define arch_mmap_check sparc64_mmap_check
int sparc64_mmap_check(unsigned long addr, unsigned long len,
unsigned long flags);
#define arch_mmap_check(addr,len,flags) sparc64_mmap_check(addr,len)
int sparc64_mmap_check(unsigned long addr, unsigned long len);
#endif
#endif
include/asm-sparc64/psrcompat.h
+2
View File
@@ -12,6 +12,7 @@
#define PSR_PIL 0x00000f00 /* processor interrupt level */
#define PSR_EF 0x00001000 /* enable floating point */
#define PSR_EC 0x00002000 /* enable co-processor */
#define PSR_SYSCALL 0x00004000 /* inside of a syscall */
#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
#define PSR_ICC 0x00f00000 /* integer condition codes */
#define PSR_C 0x00100000 /* carry bit */
@@ -30,6 +31,7 @@ static inline unsigned int tstate_to_psr(unsigned long tstate)
PSR_S |
((tstate & TSTATE_ICC) >> 12) |
((tstate & TSTATE_XCC) >> 20) |
((tstate & TSTATE_SYSCALL) ? PSR_SYSCALL : 0) |
PSR_V8PLUS);
}
include/asm-sparc64/pstate.h
+1
View File
@@ -62,6 +62,7 @@
#define TSTATE_PRIV _AC(0x0000000000000400,UL) /* Privilege. */
#define TSTATE_IE _AC(0x0000000000000200,UL) /* Interrupt Enable. */
#define TSTATE_AG _AC(0x0000000000000100,UL) /* Alternate Globals.*/
#define TSTATE_SYSCALL _AC(0x0000000000000020,UL) /* in syscall trap */
#define TSTATE_CWP _AC(0x000000000000001f,UL) /* Curr Win-Pointer. */
/* Floating-Point Registers State Register.
include/asm-sparc64/ptrace.h
+6 -7
View File
@@ -42,16 +42,14 @@ static inline int pt_regs_trap_type(struct pt_regs *regs)
return regs->magic & 0x1ff;
}
static inline int pt_regs_clear_trap_type(struct pt_regs *regs)
{
return regs->magic &= ~0x1ff;
}
static inline bool pt_regs_is_syscall(struct pt_regs *regs)
{
int tt = pt_regs_trap_type(regs);
return (regs->tstate & TSTATE_SYSCALL);
}
return (tt == 0x110 || tt == 0x111 || tt == 0x16d);
static inline bool pt_regs_clear_syscall(struct pt_regs *regs)
{
return (regs->tstate &= ~TSTATE_SYSCALL);
}
struct pt_regs32 {
@@ -298,6 +296,7 @@ extern void __show_regs(struct pt_regs *);
#define SF_XXARG 0x5c
/* Stuff for the ptrace system call */
#define PTRACE_SPARC_DETACH 11
#define PTRACE_GETREGS 12
#define PTRACE_SETREGS 13
#define PTRACE_GETFPREGS 14
include/asm-sparc64/signal.h
+1 -7
View File
@@ -186,13 +186,7 @@ struct k_sigaction {
void __user *ka_restorer;
};
struct signal_deliver_cookie {
int restart_syscall;
unsigned long orig_i0;
};
struct pt_regs;
extern void ptrace_signal_deliver(struct pt_regs *regs, void *cookie);
#define ptrace_signal_deliver(regs, cookie) do { } while (0)
#endif /* !(__KERNEL__) */
include/asm-sparc64/thread_info.h
+24 -4
View File
@@ -38,7 +38,7 @@ struct thread_info {
struct task_struct *task;
unsigned long flags;
__u8 fpsaved[7];
__u8 pad;
__u8 status;
unsigned long ksp;
/* D$ line 2 */
@@ -217,7 +217,7 @@ register struct thread_info *current_thread_info_reg asm("g6");
* nop
*/
#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
#define TIF_RESTORE_SIGMASK 1 /* restore signal mask in do_signal() */
/* flags bit 1 is available */
#define TIF_SIGPENDING 2 /* signal pending */
#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
#define TIF_PERFCTR 4 /* performance counters active */
@@ -244,14 +244,34 @@ register struct thread_info *current_thread_info_reg asm("g6");
#define _TIF_32BIT (1<<TIF_32BIT)
#define _TIF_SECCOMP (1<<TIF_SECCOMP)
#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING)
#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
#define _TIF_USER_WORK_MASK ((0xff << TI_FLAG_WSAVED_SHIFT) | \
(_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK | \
(_TIF_SIGPENDING | \
_TIF_NEED_RESCHED | _TIF_PERFCTR))
/*
* Thread-synchronous status.
*
* This is different from the flags in that nobody else
* ever touches our thread-synchronous status, so we don't
* have to worry about atomic accesses.
*
* Note that there are only 8 bits available.
*/
#define TS_RESTORE_SIGMASK 0x0001 /* restore signal mask in do_signal() */
#ifndef __ASSEMBLY__
#define HAVE_SET_RESTORE_SIGMASK 1
static inline void set_restore_sigmask(void)
{
struct thread_info *ti = current_thread_info();
ti->status |= TS_RESTORE_SIGMASK;
set_bit(TIF_SIGPENDING, &ti->flags);
}
#endif /* !__ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* _ASM_THREAD_INFO_H */
include/asm-sparc64/ttable.h
+4 -3
View File
@@ -91,13 +91,14 @@
nop;
#define SYSCALL_TRAP(routine, systbl) \
rdpr %pil, %g2; \
mov TSTATE_SYSCALL, %g3; \
sethi %hi(109f), %g7; \
ba,pt %xcc, etrap; \
ba,pt %xcc, etrap_syscall; \
109: or %g7, %lo(109b), %g7; \
sethi %hi(systbl), %l7; \
ba,pt %xcc, routine; \
or %l7, %lo(systbl), %l7; \
nop; nop;
or %l7, %lo(systbl), %l7;
#define TRAP_UTRAP(handler,lvl) \
mov handler, %g3; \
include/asm-um/irq.h
+2 -1
View File
@@ -15,8 +15,9 @@
#define SIGIO_WRITE_IRQ 11
#define TELNETD_IRQ 12
#define XTERM_IRQ 13
#define RANDOM_IRQ 14
#define LAST_IRQ XTERM_IRQ
#define LAST_IRQ RANDOM_IRQ
#define NR_IRQS (LAST_IRQ + 1)
#endif
include/asm-um/keyboard.h
-6
View File
@@ -1,6 +0,0 @@
#ifndef __UM_KEYBOARD_H
#define __UM_KEYBOARD_H
#include "asm/arch/keyboard.h"
#endif
include/asm-um/page.h
+11 -6
View File
@@ -7,16 +7,20 @@
#ifndef __UM_PAGE_H
#define __UM_PAGE_H
#include <linux/const.h>
/* PAGE_SHIFT determines the page size */
#define PAGE_SHIFT 12
#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
#define PAGE_MASK (~(PAGE_SIZE-1))
#ifndef __ASSEMBLY__
struct page;
#include <linux/types.h>
#include <asm/vm-flags.h>
/* PAGE_SHIFT determines the page size */
#define PAGE_SHIFT 12
#define PAGE_SIZE (1UL << PAGE_SHIFT)
#define PAGE_MASK (~(PAGE_SIZE-1))
/*
* These are used to make use of C type-checking..
*/
@@ -120,4 +124,5 @@ extern struct page *arch_validate(struct page *page, gfp_t mask, int order);
#include <asm-generic/memory_model.h>
#include <asm-generic/page.h>
#endif
#endif /* __ASSEMBLY__ */
#endif /* __UM_PAGE_H */
include/asm-um/param.h
+2
View File
@@ -13,6 +13,8 @@
#define HZ CONFIG_HZ
#define USER_HZ 100 /* .. some user interfaces are in "ticks" */
#define CLOCKS_PER_SEC (USER_HZ) /* frequency at which times() counts */
#else
#define HZ 100
#endif
#endif
include/asm-v850/param.h
+2
View File
@@ -26,6 +26,8 @@
# define HZ CONFIG_HZ
# define USER_HZ 100
# define CLOCKS_PER_SEC USER_HZ
#else
# define HZ 100
#endif
#endif /* __V850_PARAM_H__ */
include/asm-x86/bitops.h
+17 -20
View File
@@ -23,13 +23,10 @@
#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 1)
/* Technically wrong, but this avoids compilation errors on some gcc
versions. */
#define ADDR "=m" (*(volatile long *)addr)
#define BIT_ADDR "=m" (((volatile int *)addr)[nr >> 5])
#define ADDR "=m" (*(volatile long *) addr)
#else
#define ADDR "+m" (*(volatile long *) addr)
#define BIT_ADDR "+m" (((volatile int *)addr)[nr >> 5])
#endif
#define BASE_ADDR "m" (*(volatile int *)addr)
/**
* set_bit - Atomically set a bit in memory
@@ -77,7 +74,7 @@ static inline void __set_bit(int nr, volatile void *addr)
*/
static inline void clear_bit(int nr, volatile void *addr)
{
asm volatile(LOCK_PREFIX "btr %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
asm volatile(LOCK_PREFIX "btr %1,%0" : ADDR : "Ir" (nr));
}
/*
@@ -96,7 +93,7 @@ static inline void clear_bit_unlock(unsigned nr, volatile void *addr)
static inline void __clear_bit(int nr, volatile void *addr)
{
asm volatile("btr %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
asm volatile("btr %1,%0" : ADDR : "Ir" (nr));
}
/*
@@ -131,7 +128,7 @@ static inline void __clear_bit_unlock(unsigned nr, volatile void *addr)
*/
static inline void __change_bit(int nr, volatile void *addr)
{
asm volatile("btc %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
asm volatile("btc %1,%0" : ADDR : "Ir" (nr));
}
/**
@@ -145,7 +142,7 @@ static inline void __change_bit(int nr, volatile void *addr)
*/
static inline void change_bit(int nr, volatile void *addr)
{
asm volatile(LOCK_PREFIX "btc %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
asm volatile(LOCK_PREFIX "btc %1,%0" : ADDR : "Ir" (nr));
}
/**
@@ -191,9 +188,10 @@ static inline int __test_and_set_bit(int nr, volatile void *addr)
{
int oldbit;
asm volatile("bts %2,%3\n\t"
"sbb %0,%0"
: "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR);
asm("bts %2,%1\n\t"
"sbb %0,%0"
: "=r" (oldbit), ADDR
: "Ir" (nr));
return oldbit;
}
@@ -229,9 +227,10 @@ static inline int __test_and_clear_bit(int nr, volatile void *addr)
{
int oldbit;
asm volatile("btr %2,%3\n\t"
asm volatile("btr %2,%1\n\t"
"sbb %0,%0"
: "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR);
: "=r" (oldbit), ADDR
: "Ir" (nr));
return oldbit;
}
@@ -240,9 +239,10 @@ static inline int __test_and_change_bit(int nr, volatile void *addr)
{
int oldbit;
asm volatile("btc %2,%3\n\t"
asm volatile("btc %2,%1\n\t"
"sbb %0,%0"
: "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR);
: "=r" (oldbit), ADDR
: "Ir" (nr) : "memory");
return oldbit;
}
@@ -276,11 +276,10 @@ static inline int variable_test_bit(int nr, volatile const void *addr)
{
int oldbit;
asm volatile("bt %2,%3\n\t"
asm volatile("bt %2,%1\n\t"
"sbb %0,%0"
: "=r" (oldbit)
: "m" (((volatile const int *)addr)[nr >> 5]),
"Ir" (nr), BASE_ADDR);
: "m" (*(unsigned long *)addr), "Ir" (nr));
return oldbit;
}
@@ -397,8 +396,6 @@ static inline int fls(int x)
}
#endif /* __KERNEL__ */
#undef BASE_ADDR
#undef BIT_ADDR
#undef ADDR
static inline void set_bit_string(unsigned long *bitmap,
include/asm-x86/geode.h
+5 -7
View File
@@ -185,16 +185,14 @@ static inline int is_geode(void)
return (is_geode_gx() || is_geode_lx());
}
/*
* The VSA has virtual registers that we can query for a signature.
*/
#ifdef CONFIG_MGEODE_LX
extern int geode_has_vsa2(void);
#else
static inline int geode_has_vsa2(void)
{
outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
outw(VSA_VR_SIGNATURE, VSA_VRC_INDEX);
return (inw(VSA_VRC_DATA) == VSA_SIG);
return 0;
}
#endif
/* MFGPTs */
include/asm-x86/i387.h
+9 -1
View File
@@ -175,7 +175,15 @@ static inline int save_i387(struct _fpstate __user *buf)
*/
static inline int restore_i387(struct _fpstate __user *buf)
{
set_used_math();
struct task_struct *tsk = current;
int err;
if (!used_math()) {
err = init_fpu(tsk);
if (err)
return err;
}
if (!(task_thread_info(current)->status & TS_USEDFPU)) {
clts();
task_thread_info(current)->status |= TS_USEDFPU;
include/asm-x86/pat.h
+8
View File
@@ -4,7 +4,13 @@
#include <linux/types.h>
#ifdef CONFIG_X86_PAT
extern int pat_wc_enabled;
extern void validate_pat_support(struct cpuinfo_x86 *c);
#else
static const int pat_wc_enabled = 0;
static inline void validate_pat_support(struct cpuinfo_x86 *c) { }
#endif
extern void pat_init(void);
@@ -12,5 +18,7 @@ extern int reserve_memtype(u64 start, u64 end,
unsigned long req_type, unsigned long *ret_type);
extern int free_memtype(u64 start, u64 end);
extern void pat_disable(char *reason);
#endif
include/asm-x86/pgtable.h
+13 -3
View File
@@ -57,7 +57,8 @@
#define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | \
_PAGE_DIRTY)
#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_PCD | _PAGE_PWT | \
_PAGE_ACCESSED | _PAGE_DIRTY)
#define _PAGE_CACHE_MASK (_PAGE_PCD | _PAGE_PWT)
#define _PAGE_CACHE_WB (0)
@@ -288,12 +289,21 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
* Chop off the NX bit (if present), and add the NX portion of
* the newprot (if present):
*/
val &= _PAGE_CHG_MASK & ~_PAGE_NX;
val |= pgprot_val(newprot) & __supported_pte_mask;
val &= _PAGE_CHG_MASK;
val |= pgprot_val(newprot) & (~_PAGE_CHG_MASK) & __supported_pte_mask;
return __pte(val);
}
/* mprotect needs to preserve PAT bits when updating vm_page_prot */
#define pgprot_modify pgprot_modify
static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot)
{
pgprotval_t preservebits = pgprot_val(oldprot) & _PAGE_CHG_MASK;
pgprotval_t addbits = pgprot_val(newprot);
return __pgprot(preservebits | addbits);
}
#define pte_pgprot(x) __pgprot(pte_val(x) & (0xfff | _PAGE_NX))
#define canon_pgprot(p) __pgprot(pgprot_val(p) & __supported_pte_mask)
include/asm-x86/pgtable_32.h
+1 -8
View File
@@ -88,14 +88,7 @@ extern unsigned long pg0[];
/* To avoid harmful races, pmd_none(x) should check only the lower when PAE */
#define pmd_none(x) (!(unsigned long)pmd_val((x)))
#define pmd_present(x) (pmd_val((x)) & _PAGE_PRESENT)
extern int pmd_bad(pmd_t pmd);
#define pmd_bad_v1(x) \
(_KERNPG_TABLE != (pmd_val((x)) & ~(PAGE_MASK | _PAGE_USER)))
#define pmd_bad_v2(x) \
(_KERNPG_TABLE != (pmd_val((x)) & ~(PAGE_MASK | _PAGE_USER | \
_PAGE_PSE | _PAGE_NX)))
#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
include/asm-x86/pgtable_64.h
+2 -4
View File
@@ -158,14 +158,12 @@ static inline unsigned long pgd_bad(pgd_t pgd)
static inline unsigned long pud_bad(pud_t pud)
{
return pud_val(pud) &
~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER | _PAGE_PSE | _PAGE_NX);
return pud_val(pud) & ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER);
}
static inline unsigned long pmd_bad(pmd_t pmd)
{
return pmd_val(pmd) &
~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER | _PAGE_PSE | _PAGE_NX);
return pmd_val(pmd) & ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER);
}
#define pte_none(x) (!pte_val((x)))
include/asm-x86/spinlock.h
+4 -14
View File
@@ -20,18 +20,8 @@
*/
#ifdef CONFIG_X86_32
typedef char _slock_t;
# define LOCK_INS_DEC "decb"
# define LOCK_INS_XCH "xchgb"
# define LOCK_INS_MOV "movb"
# define LOCK_INS_CMP "cmpb"
# define LOCK_PTR_REG "a"
#else
typedef int _slock_t;
# define LOCK_INS_DEC "decl"
# define LOCK_INS_XCH "xchgl"
# define LOCK_INS_MOV "movl"
# define LOCK_INS_CMP "cmpl"
# define LOCK_PTR_REG "D"
#endif
@@ -66,14 +56,14 @@ typedef int _slock_t;
#if (NR_CPUS < 256)
static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
{
int tmp = *(volatile signed int *)(&(lock)->slock);
int tmp = ACCESS_ONCE(lock->slock);
return (((tmp >> 8) & 0xff) != (tmp & 0xff));
}
static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
{
int tmp = *(volatile signed int *)(&(lock)->slock);
int tmp = ACCESS_ONCE(lock->slock);
return (((tmp >> 8) & 0xff) - (tmp & 0xff)) > 1;
}
@@ -130,14 +120,14 @@ static __always_inline void __raw_spin_unlock(raw_spinlock_t *lock)
#else
static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
{
int tmp = *(volatile signed int *)(&(lock)->slock);
int tmp = ACCESS_ONCE(lock->slock);
return (((tmp >> 16) & 0xffff) != (tmp & 0xffff));
}
static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
{
int tmp = *(volatile signed int *)(&(lock)->slock);
int tmp = ACCESS_ONCE(lock->slock);
return (((tmp >> 16) & 0xffff) - (tmp & 0xffff)) > 1;
}
include/asm-x86/topology.h
+10 -8
View File
@@ -25,6 +25,16 @@
#ifndef _ASM_X86_TOPOLOGY_H
#define _ASM_X86_TOPOLOGY_H
#ifdef CONFIG_X86_32
# ifdef CONFIG_X86_HT
# define ENABLE_TOPO_DEFINES
# endif
#else
# ifdef CONFIG_SMP
# define ENABLE_TOPO_DEFINES
# endif
#endif
#ifdef CONFIG_NUMA
#include <linux/cpumask.h>
#include <asm/mpspec.h>
@@ -130,10 +140,6 @@ extern unsigned long node_end_pfn[];
extern unsigned long node_remap_size[];
#define node_has_online_mem(nid) (node_start_pfn[nid] != node_end_pfn[nid])
# ifdef CONFIG_X86_HT
# define ENABLE_TOPO_DEFINES
# endif
# define SD_CACHE_NICE_TRIES 1
# define SD_IDLE_IDX 1
# define SD_NEWIDLE_IDX 2
@@ -141,10 +147,6 @@ extern unsigned long node_remap_size[];
#else
# ifdef CONFIG_SMP
# define ENABLE_TOPO_DEFINES
# endif
# define SD_CACHE_NICE_TRIES 2
# define SD_IDLE_IDX 2
# define SD_NEWIDLE_IDX 2
include/asm-xtensa/param.h
+2
View File
@@ -15,6 +15,8 @@
# define HZ CONFIG_HZ /* internal timer frequency */
# define USER_HZ 100 /* for user interfaces in "ticks" */
# define CLOCKS_PER_SEC (USER_HZ) /* frequnzy at which times() counts */
#else
# define HZ 100
#endif
#define EXEC_PAGESIZE 4096
include/linux/atm.h
+2 -5
View File
@@ -16,14 +16,11 @@
* documentation. Do not change them.
*/
#ifdef __KERNEL__
#include <linux/socket.h>
#include <linux/types.h>
#endif
#include <linux/compiler.h>
#include <linux/atmapi.h>
#include <linux/atmsap.h>
#include <linux/atmioc.h>
#include <linux/types.h>
/* general ATM constants */
@@ -212,7 +209,7 @@ struct sockaddr_atmsvc {
char pub[ATM_E164_LEN+1]; /* public address (E.164) */
/* unused addresses must be bzero'ed */
char lij_type; /* role in LIJ call; one of ATM_LIJ* */
uint32_t lij_id; /* LIJ call identifier */
__u32 lij_id; /* LIJ call identifier */
} sas_addr __ATM_API_ALIGN; /* SVC address */
};
include/linux/atm_tcp.h
+5 -7
View File
@@ -8,11 +8,9 @@
#define LINUX_ATM_TCP_H
#include <linux/atmapi.h>
#ifdef __KERNEL__
#include <linux/types.h>
#endif
#include <linux/atm.h>
#include <linux/atmioc.h>
#include <linux/types.h>
/*
@@ -20,9 +18,9 @@
*/
struct atmtcp_hdr {
uint16_t vpi;
uint16_t vci;
uint32_t length; /* ... of data part */
__u16 vpi;
__u16 vci;
__u32 length; /* ... of data part */
};
/*
include/linux/bitmap.h
-1
View File
@@ -110,7 +110,6 @@ extern int __bitmap_weight(const unsigned long *bitmap, int bits);
extern int bitmap_scnprintf(char *buf, unsigned int len,
const unsigned long *src, int nbits);
extern int bitmap_scnprintf_len(unsigned int len);
extern int __bitmap_parse(const char *buf, unsigned int buflen, int is_user,
unsigned long *dst, int nbits);
extern int bitmap_parse_user(const char __user *ubuf, unsigned int ulen,
include/linux/compiler.h
+12
View File
@@ -182,4 +182,16 @@ extern void __chk_io_ptr(const volatile void __iomem *);
# define __section(S) __attribute__ ((__section__(#S)))
#endif
/*
* Prevent the compiler from merging or refetching accesses. The compiler
* is also forbidden from reordering successive instances of ACCESS_ONCE(),
* but only when the compiler is aware of some particular ordering. One way
* to make the compiler aware of ordering is to put the two invocations of
* ACCESS_ONCE() in different C statements.
*
* This macro does absolutely -nothing- to prevent the CPU from reordering,
* merging, or refetching absolutely anything at any time.
*/
#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))
#endif /* __LINUX_COMPILER_H */
include/linux/cpumask.h
-7
View File
@@ -289,13 +289,6 @@ static inline int __cpumask_scnprintf(char *buf, int len,
return bitmap_scnprintf(buf, len, srcp->bits, nbits);
}
#define cpumask_scnprintf_len(len) \
__cpumask_scnprintf_len((len))
static inline int __cpumask_scnprintf_len(int len)
{
return bitmap_scnprintf_len(len);
}
#define cpumask_parse_user(ubuf, ulen, dst) \
__cpumask_parse_user((ubuf), (ulen), &(dst), NR_CPUS)
static inline int __cpumask_parse_user(const char __user *buf, int len,

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