Merge branch 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: (23 commits) drm/i915: remove full registers dump debug drm/i915: Add DP dpll limit on ironlake and use existing DPLL search function drm/i915: Select the correct BPC for LVDS on Ironlake drm/i915: Make the BPC in FDI rx/transcoder be consistent with that in pipeconf on Ironlake drm/i915: Enable/disable the dithering for LVDS based on VBT setting drm/i915: Permit pinning whilst the device is 'suspended' drm/i915: Hold struct mutex whilst pinning power context bo. drm/i915: fix unused var drm/i915: Storage class should be before const qualifier drm/i915: remove render reclock support drm/i915: Fix RC6 suspend/resume drm/i915: execbuf2 support drm/i915: Reload hangcheck timer too for Ironlake drm/i915: only enable hotplug for detected outputs drm/i915: Track whether cursor needs physical address in intel_device_info drm/i915: Implement IS_* macros using static tables drm/i915: Move PCI IDs into i915 driver drm/i915: Update LVDS connector status when receiving ACPI LID event drm/i915: Add MALATA PC-81005 to ACPI LID quirk list drm/i915: implement new pm ops for i915 ...
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@@ -188,6 +188,7 @@ typedef struct _drm_i915_sarea {
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#define DRM_I915_GEM_MADVISE 0x26
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#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
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#define DRM_I915_OVERLAY_ATTRS 0x28
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#define DRM_I915_GEM_EXECBUFFER2 0x29
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#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
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#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
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@@ -207,6 +208,7 @@ typedef struct _drm_i915_sarea {
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#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
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#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
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#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
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#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
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#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
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#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
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#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
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@@ -272,6 +274,7 @@ typedef struct drm_i915_irq_wait {
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#define I915_PARAM_NUM_FENCES_AVAIL 6
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#define I915_PARAM_HAS_OVERLAY 7
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#define I915_PARAM_HAS_PAGEFLIPPING 8
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#define I915_PARAM_HAS_EXECBUF2 9
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typedef struct drm_i915_getparam {
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int param;
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@@ -567,6 +570,57 @@ struct drm_i915_gem_execbuffer {
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__u64 cliprects_ptr;
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};
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struct drm_i915_gem_exec_object2 {
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/**
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* User's handle for a buffer to be bound into the GTT for this
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* operation.
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*/
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__u32 handle;
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/** Number of relocations to be performed on this buffer */
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__u32 relocation_count;
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/**
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* Pointer to array of struct drm_i915_gem_relocation_entry containing
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* the relocations to be performed in this buffer.
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*/
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__u64 relocs_ptr;
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/** Required alignment in graphics aperture */
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__u64 alignment;
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/**
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* Returned value of the updated offset of the object, for future
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* presumed_offset writes.
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*/
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__u64 offset;
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#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
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__u64 flags;
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__u64 rsvd1;
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__u64 rsvd2;
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};
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struct drm_i915_gem_execbuffer2 {
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/**
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* List of gem_exec_object2 structs
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*/
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__u64 buffers_ptr;
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__u32 buffer_count;
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/** Offset in the batchbuffer to start execution from. */
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__u32 batch_start_offset;
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/** Bytes used in batchbuffer from batch_start_offset */
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__u32 batch_len;
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__u32 DR1;
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__u32 DR4;
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__u32 num_cliprects;
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/** This is a struct drm_clip_rect *cliprects */
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__u64 cliprects_ptr;
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__u64 flags; /* currently unused */
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__u64 rsvd1;
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__u64 rsvd2;
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};
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struct drm_i915_gem_pin {
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/** Handle of the buffer to be pinned. */
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__u32 handle;
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