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Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6

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* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: (26 commits)
  sh: intc - add support for SH7750 and its variants
  sh: Move entry point code to .text.head.
  sh: heartbeat: Shut up resource size warning.
  sh: update r2d defconfig and fix SH7751R pci compliation
  sh: Many symbol exports for nommu allmodconfig.
  sh: zero terminate 8250 platform data for r2d board
  sh: cpufreq: Fix up the build for SH-2.
  sh: Make on-chip DMA channel selection explicit.
  sh: Fix up CPU dependencies for on-chip DMAC.
  sh: cpufreq: clock framework support.
  sh: Support rate rounding for SH7722 FRQCR clocks.
  sh: Implement clk_round_rate() in the clock framework.
  sh: Fix up PCI section mismatch warnings.
  sh: Wire up fallocate() syscall.
  sh: intc - add support for 7780
  sh: intc - improve group support
  sh: Fix up SH-3 and SH-4 driver dependencies.
  sh: push-switch: Correct license string.
  sh: cpufreq: Fix driver dependencies and flag as broken.
  sh: IPR/INTC2 IRQ setup consolidation.
  ...
This commit is contained in:
Linus Torvalds
2007-07-20 08:52:53 -07:00
parent 7f46e6ca01 56386f6424
commit 5f7e08ca7b
56 changed files with 1329 additions and 574 deletions
Download Patch File Download Diff File Expand all files Collapse all files
include/asm-sh/clock.h
+1
View File
@@ -14,6 +14,7 @@ struct clk_ops {
void (*disable)(struct clk *clk);
void (*recalc)(struct clk *clk);
int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
long (*round_rate)(struct clk *clk, unsigned long rate);
};
struct clk {
include/asm-sh/hw_irq.h
+74 -3
View File
@@ -1,6 +1,7 @@
#ifndef __ASM_SH_HW_IRQ_H
#define __ASM_SH_HW_IRQ_H
#include <linux/init.h>
#include <asm/atomic.h>
extern atomic_t irq_err_count;
@@ -22,7 +23,6 @@ struct intc2_desc {
};
void register_intc2_controller(struct intc2_desc *);
void init_IRQ_intc2(void);
struct ipr_data {
unsigned char irq;
@@ -40,11 +40,82 @@ struct ipr_desc {
};
void register_ipr_controller(struct ipr_desc *);
void init_IRQ_ipr(void);
/*
* Enable individual interrupt mode for external IPR IRQs.
*/
void ipr_irq_enable_irlm(void);
void __init ipr_irq_enable_irlm(void);
typedef unsigned char intc_enum;
struct intc_vect {
intc_enum enum_id;
unsigned short vect;
};
#define INTC_VECT(enum_id, vect) { enum_id, vect }
struct intc_prio {
intc_enum enum_id;
unsigned char priority;
};
#define INTC_PRIO(enum_id, prio) { enum_id, prio }
struct intc_group {
intc_enum enum_id;
intc_enum *enum_ids;
};
#define INTC_GROUP(enum_id, ids...) { enum_id, (intc_enum []) { ids, 0 } }
struct intc_mask_reg {
unsigned long set_reg, clr_reg, reg_width;
intc_enum enum_ids[32];
};
struct intc_prio_reg {
unsigned long reg, reg_width, field_width;
intc_enum enum_ids[16];
};
struct intc_sense_reg {
unsigned long reg, reg_width, field_width;
intc_enum enum_ids[16];
};
struct intc_desc {
struct intc_vect *vectors;
unsigned int nr_vectors;
struct intc_group *groups;
unsigned int nr_groups;
struct intc_prio *priorities;
unsigned int nr_priorities;
struct intc_mask_reg *mask_regs;
unsigned int nr_mask_regs;
struct intc_prio_reg *prio_regs;
unsigned int nr_prio_regs;
struct intc_sense_reg *sense_regs;
unsigned int nr_sense_regs;
struct irq_chip chip;
};
#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
priorities, mask_regs, prio_regs, sense_regs) \
struct intc_desc symbol = { \
_INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
_INTC_ARRAY(priorities), \
_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
_INTC_ARRAY(sense_regs), \
.chip.name = chipname, \
}
void __init register_intc_controller(struct intc_desc *desc);
void __init plat_irq_setup(void);
enum { IRQ_MODE_IRQ, IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
void __init plat_irq_setup_pins(int mode);
#endif /* __ASM_SH_HW_IRQ_H */
include/asm-sh/se7722.h
+17 -21
View File
@@ -81,36 +81,32 @@
/* IRQ */
#define IRQ0_IRQ 32
#define IRQ1_IRQ 33
#define INTC_ICR0 0xA4140000UL
#define INTC_ICR1 0xA414001CUL
#define INTMSK0 0xa4140044
#define INTMSKCLR0 0xa4140064
#define INTC_INTPRI0 0xa4140010
#define IRQ01_MODE 0xb1800000
#define IRQ01_STS 0xb1800004
#define IRQ01_MASK 0xb1800008
#define EXT_BIT (0x3fc0) /* SH IRQ1 */
#define MRSHPC_BIT0 (0x0004) /* SH IRQ1 */
#define MRSHPC_BIT1 (0x0008) /* SH IRQ1 */
#define MRSHPC_BIT2 (0x0010) /* SH IRQ1 */
#define MRSHPC_BIT3 (0x0020) /* SH IRQ1 */
#define SMC_BIT (0x0002) /* SH IRQ0 */
#define USB_BIT (0x0001) /* SH IRQ0 */
#define MRSHPC_IRQ3 11
#define MRSHPC_IRQ2 12
#define MRSHPC_IRQ1 13
#define MRSHPC_IRQ0 14
#define SMC_IRQ 10
#define EXT_IRQ 5
#define USB_IRQ 6
/* Bits in IRQ01_* registers */
#define SE7722_FPGA_IRQ_USB 0 /* IRQ0 */
#define SE7722_FPGA_IRQ_SMC 1 /* IRQ0 */
#define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */
#define SE7722_FPGA_IRQ_MRSHPC1 3 /* IRQ1 */
#define SE7722_FPGA_IRQ_MRSHPC2 4 /* IRQ1 */
#define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */
#define SE7722_FPGA_IRQ_NR 6
#define SE7722_FPGA_IRQ_BASE 110
#define MRSHPC_IRQ3 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC3)
#define MRSHPC_IRQ2 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC2)
#define MRSHPC_IRQ1 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC1)
#define MRSHPC_IRQ0 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC0)
#define SMC_IRQ (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_SMC)
#define USB_IRQ (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_USB)
/* arch/sh/boards/se/7722/irq.c */
void init_se7722_IRQ(void);
int se7722_irq_demux(int);
#define __IO_PREFIX se7722
#include <asm/io_generic.h>
include/asm-sh/unistd.h
+2 -1
View File
@@ -332,8 +332,9 @@
#define __NR_signalfd 321
#define __NR_timerfd 322
#define __NR_eventfd 323
#define __NR_fallocate 324
#define NR_syscalls 324
#define NR_syscalls 325
#ifdef __KERNEL__