Merge tag 'amd-drm-next-5.14-2021-06-02' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-5.14-2021-06-02: amdgpu: - GC/MM register access macro clean up for SR-IOV - Beige Goby updates - W=1 Fixes - Aldebaran fixes - Misc display fixes - ACPI ATCS/ATIF handling rework - SR-IOV fixes - RAS fixes - 16bpc fixed point format support - Initial smartshift support - RV/PCO power tuning fixes for suspend/resume - More buffer object subclassing work - Add new INFO query for additional vbios information - Add new placement for preemptable SG buffers amdkfd: - Misc fixes radeon: - W=1 Fixes - Misc cleanups UAPI: - Add new INFO query for additional vbios information Useful for debugging vbios related issues. Proposed umr patch: https://patchwork.freedesktop.org/patch/433297/ - 16bpc fixed point format support IGT test: https://lists.freedesktop.org/archives/igt-dev/2021-May/031507.html Proposed Vulkan patch: https://github.com/kleinerm/pal/commit/a25d4802074b13a8d5f7edc96ae45469ecbac3c4 - Add a new GEM flag which is only used internally in the kernel driver. Userspace is not allowed to set it. drm: - 16bpc fixed point format fourcc Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210602214009.4553-1-alexander.deucher@amd.com
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@@ -136,6 +136,10 @@ extern "C" {
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* accessing it with various hw blocks
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*/
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#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)
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/* Flag that BO will be used only in preemptible context, which does
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* not require GTT memory accounting
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*/
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#define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11)
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struct drm_amdgpu_gem_create_in {
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/** the requested memory size */
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@@ -753,6 +757,8 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_VBIOS_SIZE 0x1
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/* Subquery id: Query vbios image */
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#define AMDGPU_INFO_VBIOS_IMAGE 0x2
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/* Subquery id: Query vbios info */
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#define AMDGPU_INFO_VBIOS_INFO 0x3
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/* Query UVD handles */
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#define AMDGPU_INFO_NUM_HANDLES 0x1C
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/* Query sensor related information */
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@@ -946,6 +952,15 @@ struct drm_amdgpu_info_firmware {
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__u32 feature;
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};
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struct drm_amdgpu_info_vbios {
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__u8 name[64];
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__u8 vbios_pn[64];
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__u32 version;
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__u32 pad;
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__u8 vbios_ver_str[32];
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__u8 date[32];
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};
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#define AMDGPU_VRAM_TYPE_UNKNOWN 0
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#define AMDGPU_VRAM_TYPE_GDDR1 1
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#define AMDGPU_VRAM_TYPE_DDR2 2
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@@ -168,6 +168,13 @@ extern "C" {
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#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
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#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
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/* 64 bpp RGB */
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#define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */
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#define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */
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#define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */
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#define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */
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/*
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* Floating point 64bpp RGB
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* IEEE 754-2008 binary16 half-precision float
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