Merge tag 'char-misc-3.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc into next
Pull char/misc driver patches from Greg KH: "Here is the big char / misc driver update for 3.16-rc1. Lots of different driver updates for a variety of different drivers and minor driver subsystems. All have been in linux-next with no reported issues" * tag 'char-misc-3.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (79 commits) hv: use correct order when freeing monitor_pages spmi: of: fixup generic SPMI devicetree binding example applicom: dereferencing NULL on error path misc: genwqe: fix uninitialized return value in genwqe_free_sync_sgl() miscdevice.h: Simple syntax fix to make pointers consistent. MAINTAINERS: Add miscdevice.h to file list for char/misc drivers. mcb: Add support for shared PCI IRQs drivers: Remove duplicate conditionally included subdirs misc: atmel_pwm: only build for supported platforms mei: me: move probe quirk to cfg structure mei: add per device configuration mei: me: read H_CSR after asserting reset mei: me: drop harmful wait optimization mei: me: fix hw ready reset flow mei: fix memory leak of mei_clients array uio: fix vma io range check in mmap drivers: uio_dmem_genirq: Fix memory leak in uio_dmem_genirq_probe() w1: do not unlock unheld list_mutex in __w1_remove_master_device() w1: optional bundling of netlink kernel replies connector: allow multiple messages to be sent in one packet ...
This commit is contained in:
Linus Torvalds
@@ -71,6 +71,7 @@ struct cn_dev {
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int cn_add_callback(struct cb_id *id, const char *name,
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void (*callback)(struct cn_msg *, struct netlink_skb_parms *));
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void cn_del_callback(struct cb_id *);
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int cn_netlink_send_mult(struct cn_msg *msg, u16 len, u32 portid, u32 group, gfp_t gfp_mask);
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int cn_netlink_send(struct cn_msg *msg, u32 portid, u32 group, gfp_t gfp_mask);
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int cn_queue_add_callback(struct cn_queue_dev *dev, const char *name,
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@@ -185,8 +185,21 @@ struct extcon_specific_cable_nb {
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*/
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extern int extcon_dev_register(struct extcon_dev *edev);
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extern void extcon_dev_unregister(struct extcon_dev *edev);
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extern int devm_extcon_dev_register(struct device *dev,
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struct extcon_dev *edev);
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extern void devm_extcon_dev_unregister(struct device *dev,
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struct extcon_dev *edev);
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extern struct extcon_dev *extcon_get_extcon_dev(const char *extcon_name);
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/*
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* Following APIs control the memory of extcon device.
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*/
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extern struct extcon_dev *extcon_dev_allocate(const char **cables);
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extern void extcon_dev_free(struct extcon_dev *edev);
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extern struct extcon_dev *devm_extcon_dev_allocate(struct device *dev,
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const char **cables);
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extern void devm_extcon_dev_free(struct device *dev, struct extcon_dev *edev);
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/*
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* get/set/update_state access the 32b encoded state value, which represents
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* states of all possible cables of the multistate port. For example, if one
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@@ -254,6 +267,30 @@ static inline int extcon_dev_register(struct extcon_dev *edev)
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static inline void extcon_dev_unregister(struct extcon_dev *edev) { }
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static inline int devm_extcon_dev_register(struct device *dev,
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struct extcon_dev *edev)
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{
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return -EINVAL;
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}
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static inline void devm_extcon_dev_unregister(struct device *dev,
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struct extcon_dev *edev) { }
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static inline struct extcon_dev *extcon_dev_allocate(const char **cables)
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{
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return ERR_PTR(-ENOSYS);
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}
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static inline void extcon_dev_free(struct extcon_dev *edev) { }
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static inline struct extcon_dev *devm_extcon_dev_allocate(struct device *dev,
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const char **cables)
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{
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return ERR_PTR(-ENOSYS);
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}
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static inline void devm_extcon_dev_free(struct extcon_dev *edev) { }
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static inline u32 extcon_get_state(struct extcon_dev *edev)
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{
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return 0;
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@@ -696,6 +696,8 @@ struct vmbus_channel {
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* preserve the earlier behavior.
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*/
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u32 target_vp;
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/* The corresponding CPUID in the guest */
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u32 target_cpu;
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/*
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* Support for sub-channels. For high performance devices,
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* it will be useful to have multiple sub-channels to support
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@@ -732,6 +734,11 @@ struct vmbus_channel {
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* Support per-channel state for use by vmbus drivers.
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*/
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void *per_channel_state;
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/*
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* To support per-cpu lookup mapping of relid to channel,
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* link up channels based on their CPU affinity.
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*/
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struct list_head percpu_list;
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};
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static inline void set_channel_read_state(struct vmbus_channel *c, bool state)
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+5
-1
@@ -16,6 +16,7 @@
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#include <linux/irqreturn.h>
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struct mcb_driver;
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struct mcb_device;
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/**
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* struct mcb_bus - MEN Chameleon Bus
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@@ -23,11 +24,14 @@ struct mcb_driver;
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* @dev: pointer to carrier device
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* @children: the child busses
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* @bus_nr: mcb bus number
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* @get_irq: callback to get IRQ number
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*/
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struct mcb_bus {
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struct list_head children;
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struct device dev;
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struct device *carrier;
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int bus_nr;
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int (*get_irq)(struct mcb_device *dev);
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};
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#define to_mcb_bus(b) container_of((b), struct mcb_bus, dev)
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@@ -105,7 +109,7 @@ extern void mcb_unregister_driver(struct mcb_driver *driver);
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module_driver(__mcb_driver, mcb_register_driver, mcb_unregister_driver);
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extern void mcb_bus_add_devices(const struct mcb_bus *bus);
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extern int mcb_device_register(struct mcb_bus *bus, struct mcb_device *dev);
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extern struct mcb_bus *mcb_alloc_bus(void);
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extern struct mcb_bus *mcb_alloc_bus(struct device *carrier);
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extern struct mcb_bus *mcb_bus_get(struct mcb_bus *bus);
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extern void mcb_bus_put(struct mcb_bus *bus);
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extern struct mcb_device *mcb_alloc_dev(struct mcb_bus *bus);
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@@ -1,7 +1,7 @@
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/*
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* max14577-private.h - Common API for the Maxim 14577 internal sub chip
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* max14577-private.h - Common API for the Maxim 14577/77836 internal sub chip
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*
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* Copyright (C) 2013 Samsung Electrnoics
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* Copyright (C) 2014 Samsung Electrnoics
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* Chanwoo Choi <cw00.choi@samsung.com>
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* Krzysztof Kozlowski <k.kozlowski@samsung.com>
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*
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@@ -22,9 +22,19 @@
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#include <linux/i2c.h>
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#include <linux/regmap.h>
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#define MAX14577_REG_INVALID (0xff)
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#define I2C_ADDR_PMIC (0x46 >> 1)
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#define I2C_ADDR_MUIC (0x4A >> 1)
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#define I2C_ADDR_FG (0x6C >> 1)
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/* Slave addr = 0x4A: Interrupt */
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enum maxim_device_type {
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MAXIM_DEVICE_TYPE_UNKNOWN = 0,
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MAXIM_DEVICE_TYPE_MAX14577,
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MAXIM_DEVICE_TYPE_MAX77836,
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MAXIM_DEVICE_TYPE_NUM,
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};
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/* Slave addr = 0x4A: MUIC and Charger */
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enum max14577_reg {
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MAX14577_REG_DEVICEID = 0x00,
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MAX14577_REG_INT1 = 0x01,
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@@ -74,20 +84,22 @@ enum max14577_muic_charger_type {
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};
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/* MAX14577 interrupts */
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#define INT1_ADC_MASK (0x1 << 0)
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#define INT1_ADCLOW_MASK (0x1 << 1)
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#define INT1_ADCERR_MASK (0x1 << 2)
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#define MAX14577_INT1_ADC_MASK BIT(0)
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#define MAX14577_INT1_ADCLOW_MASK BIT(1)
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#define MAX14577_INT1_ADCERR_MASK BIT(2)
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#define MAX77836_INT1_ADC1K_MASK BIT(3)
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#define INT2_CHGTYP_MASK (0x1 << 0)
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#define INT2_CHGDETRUN_MASK (0x1 << 1)
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#define INT2_DCDTMR_MASK (0x1 << 2)
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#define INT2_DBCHG_MASK (0x1 << 3)
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#define INT2_VBVOLT_MASK (0x1 << 4)
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#define MAX14577_INT2_CHGTYP_MASK BIT(0)
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#define MAX14577_INT2_CHGDETRUN_MASK BIT(1)
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#define MAX14577_INT2_DCDTMR_MASK BIT(2)
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#define MAX14577_INT2_DBCHG_MASK BIT(3)
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#define MAX14577_INT2_VBVOLT_MASK BIT(4)
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#define MAX77836_INT2_VIDRM_MASK BIT(5)
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#define INT3_EOC_MASK (0x1 << 0)
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#define INT3_CGMBC_MASK (0x1 << 1)
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#define INT3_OVP_MASK (0x1 << 2)
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#define INT3_MBCCHGERR_MASK (0x1 << 3)
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#define MAX14577_INT3_EOC_MASK BIT(0)
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#define MAX14577_INT3_CGMBC_MASK BIT(1)
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#define MAX14577_INT3_OVP_MASK BIT(2)
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#define MAX14577_INT3_MBCCHGERR_MASK BIT(3)
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/* MAX14577 DEVICE ID register */
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#define DEVID_VENDORID_SHIFT 0
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@@ -99,9 +111,11 @@ enum max14577_muic_charger_type {
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#define STATUS1_ADC_SHIFT 0
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#define STATUS1_ADCLOW_SHIFT 5
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#define STATUS1_ADCERR_SHIFT 6
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#define MAX77836_STATUS1_ADC1K_SHIFT 7
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#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
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#define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
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#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
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#define STATUS1_ADCLOW_MASK BIT(STATUS1_ADCLOW_SHIFT)
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#define STATUS1_ADCERR_MASK BIT(STATUS1_ADCERR_SHIFT)
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#define MAX77836_STATUS1_ADC1K_MASK BIT(MAX77836_STATUS1_ADC1K_SHIFT)
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/* MAX14577 STATUS2 register */
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#define STATUS2_CHGTYP_SHIFT 0
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@@ -109,11 +123,13 @@ enum max14577_muic_charger_type {
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#define STATUS2_DCDTMR_SHIFT 4
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#define STATUS2_DBCHG_SHIFT 5
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#define STATUS2_VBVOLT_SHIFT 6
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#define MAX77836_STATUS2_VIDRM_SHIFT 7
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#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
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#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
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#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
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#define STATUS2_DBCHG_MASK (0x1 << STATUS2_DBCHG_SHIFT)
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#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
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#define STATUS2_CHGDETRUN_MASK BIT(STATUS2_CHGDETRUN_SHIFT)
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#define STATUS2_DCDTMR_MASK BIT(STATUS2_DCDTMR_SHIFT)
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#define STATUS2_DBCHG_MASK BIT(STATUS2_DBCHG_SHIFT)
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#define STATUS2_VBVOLT_MASK BIT(STATUS2_VBVOLT_SHIFT)
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#define MAX77836_STATUS2_VIDRM_MASK BIT(MAX77836_STATUS2_VIDRM_SHIFT)
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/* MAX14577 CONTROL1 register */
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#define COMN1SW_SHIFT 0
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@@ -122,8 +138,8 @@ enum max14577_muic_charger_type {
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#define IDBEN_SHIFT 7
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#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
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#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
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#define MICEN_MASK (0x1 << MICEN_SHIFT)
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#define IDBEN_MASK (0x1 << IDBEN_SHIFT)
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#define MICEN_MASK BIT(MICEN_SHIFT)
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#define IDBEN_MASK BIT(IDBEN_SHIFT)
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#define CLEAR_IDBEN_MICEN_MASK (COMN1SW_MASK | COMP2SW_MASK)
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#define CTRL1_SW_USB ((1 << COMP2SW_SHIFT) \
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| (1 << COMN1SW_SHIFT))
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@@ -143,14 +159,14 @@ enum max14577_muic_charger_type {
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#define CTRL2_ACCDET_SHIFT (5)
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#define CTRL2_USBCPINT_SHIFT (6)
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#define CTRL2_RCPS_SHIFT (7)
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#define CTRL2_LOWPWR_MASK (0x1 << CTRL2_LOWPWR_SHIFT)
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#define CTRL2_ADCEN_MASK (0x1 << CTRL2_ADCEN_SHIFT)
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#define CTRL2_CPEN_MASK (0x1 << CTRL2_CPEN_SHIFT)
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#define CTRL2_SFOUTASRT_MASK (0x1 << CTRL2_SFOUTASRT_SHIFT)
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#define CTRL2_SFOUTORD_MASK (0x1 << CTRL2_SFOUTORD_SHIFT)
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#define CTRL2_ACCDET_MASK (0x1 << CTRL2_ACCDET_SHIFT)
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#define CTRL2_USBCPINT_MASK (0x1 << CTRL2_USBCPINT_SHIFT)
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#define CTRL2_RCPS_MASK (0x1 << CTR2_RCPS_SHIFT)
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#define CTRL2_LOWPWR_MASK BIT(CTRL2_LOWPWR_SHIFT)
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#define CTRL2_ADCEN_MASK BIT(CTRL2_ADCEN_SHIFT)
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#define CTRL2_CPEN_MASK BIT(CTRL2_CPEN_SHIFT)
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#define CTRL2_SFOUTASRT_MASK BIT(CTRL2_SFOUTASRT_SHIFT)
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#define CTRL2_SFOUTORD_MASK BIT(CTRL2_SFOUTORD_SHIFT)
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#define CTRL2_ACCDET_MASK BIT(CTRL2_ACCDET_SHIFT)
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#define CTRL2_USBCPINT_MASK BIT(CTRL2_USBCPINT_SHIFT)
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#define CTRL2_RCPS_MASK BIT(CTRL2_RCPS_SHIFT)
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#define CTRL2_CPEN1_LOWPWR0 ((1 << CTRL2_CPEN_SHIFT) | \
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(0 << CTRL2_LOWPWR_SHIFT))
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@@ -198,14 +214,14 @@ enum max14577_charger_reg {
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#define CDETCTRL1_DBEXIT_SHIFT 5
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#define CDETCTRL1_DBIDLE_SHIFT 6
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#define CDETCTRL1_CDPDET_SHIFT 7
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#define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT)
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#define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
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#define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT)
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#define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT)
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#define CDETCTRL1_DCHKTM_MASK (0x1 << CDETCTRL1_DCHKTM_SHIFT)
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#define CDETCTRL1_DBEXIT_MASK (0x1 << CDETCTRL1_DBEXIT_SHIFT)
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#define CDETCTRL1_DBIDLE_MASK (0x1 << CDETCTRL1_DBIDLE_SHIFT)
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#define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT)
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#define CDETCTRL1_CHGDETEN_MASK BIT(CDETCTRL1_CHGDETEN_SHIFT)
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#define CDETCTRL1_CHGTYPMAN_MASK BIT(CDETCTRL1_CHGTYPMAN_SHIFT)
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#define CDETCTRL1_DCDEN_MASK BIT(CDETCTRL1_DCDEN_SHIFT)
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#define CDETCTRL1_DCD2SCT_MASK BIT(CDETCTRL1_DCD2SCT_SHIFT)
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#define CDETCTRL1_DCHKTM_MASK BIT(CDETCTRL1_DCHKTM_SHIFT)
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#define CDETCTRL1_DBEXIT_MASK BIT(CDETCTRL1_DBEXIT_SHIFT)
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#define CDETCTRL1_DBIDLE_MASK BIT(CDETCTRL1_DBIDLE_SHIFT)
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#define CDETCTRL1_CDPDET_MASK BIT(CDETCTRL1_CDPDET_SHIFT)
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/* MAX14577 CHGCTRL1 register */
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#define CHGCTRL1_TCHW_SHIFT 4
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@@ -213,9 +229,9 @@ enum max14577_charger_reg {
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/* MAX14577 CHGCTRL2 register */
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#define CHGCTRL2_MBCHOSTEN_SHIFT 6
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#define CHGCTRL2_MBCHOSTEN_MASK (0x1 << CHGCTRL2_MBCHOSTEN_SHIFT)
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#define CHGCTRL2_MBCHOSTEN_MASK BIT(CHGCTRL2_MBCHOSTEN_SHIFT)
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#define CHGCTRL2_VCHGR_RC_SHIFT 7
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#define CHGCTRL2_VCHGR_RC_MASK (0x1 << CHGCTRL2_VCHGR_RC_SHIFT)
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#define CHGCTRL2_VCHGR_RC_MASK BIT(CHGCTRL2_VCHGR_RC_SHIFT)
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/* MAX14577 CHGCTRL3 register */
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#define CHGCTRL3_MBCCVWRC_SHIFT 0
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@@ -225,7 +241,7 @@ enum max14577_charger_reg {
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#define CHGCTRL4_MBCICHWRCH_SHIFT 0
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#define CHGCTRL4_MBCICHWRCH_MASK (0xf << CHGCTRL4_MBCICHWRCH_SHIFT)
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#define CHGCTRL4_MBCICHWRCL_SHIFT 4
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#define CHGCTRL4_MBCICHWRCL_MASK (0x1 << CHGCTRL4_MBCICHWRCL_SHIFT)
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#define CHGCTRL4_MBCICHWRCL_MASK BIT(CHGCTRL4_MBCICHWRCL_SHIFT)
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/* MAX14577 CHGCTRL5 register */
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#define CHGCTRL5_EOCS_SHIFT 0
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@@ -233,7 +249,7 @@ enum max14577_charger_reg {
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/* MAX14577 CHGCTRL6 register */
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#define CHGCTRL6_AUTOSTOP_SHIFT 5
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#define CHGCTRL6_AUTOSTOP_MASK (0x1 << CHGCTRL6_AUTOSTOP_SHIFT)
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#define CHGCTRL6_AUTOSTOP_MASK BIT(CHGCTRL6_AUTOSTOP_SHIFT)
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||||
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/* MAX14577 CHGCTRL7 register */
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#define CHGCTRL7_OTPCGHCVS_SHIFT 0
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@@ -245,14 +261,111 @@ enum max14577_charger_reg {
|
||||
#define MAX14577_REGULATOR_CURRENT_LIMIT_HIGH_STEP 50000
|
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#define MAX14577_REGULATOR_CURRENT_LIMIT_MAX 950000
|
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|
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/* MAX77836 regulator current limits (as in CHGCTRL4 register), uA */
|
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#define MAX77836_REGULATOR_CURRENT_LIMIT_MIN 45000
|
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#define MAX77836_REGULATOR_CURRENT_LIMIT_HIGH_START 100000
|
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#define MAX77836_REGULATOR_CURRENT_LIMIT_HIGH_STEP 25000
|
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#define MAX77836_REGULATOR_CURRENT_LIMIT_MAX 475000
|
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|
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/* MAX14577 regulator SFOUT LDO voltage, fixed, uV */
|
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#define MAX14577_REGULATOR_SAFEOUT_VOLTAGE 4900000
|
||||
|
||||
/* MAX77836 regulator LDOx voltage, uV */
|
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#define MAX77836_REGULATOR_LDO_VOLTAGE_MIN 800000
|
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#define MAX77836_REGULATOR_LDO_VOLTAGE_MAX 3950000
|
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#define MAX77836_REGULATOR_LDO_VOLTAGE_STEP 50000
|
||||
#define MAX77836_REGULATOR_LDO_VOLTAGE_STEPS_NUM 64
|
||||
|
||||
/* Slave addr = 0x46: PMIC */
|
||||
enum max77836_pmic_reg {
|
||||
MAX77836_PMIC_REG_PMIC_ID = 0x20,
|
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MAX77836_PMIC_REG_PMIC_REV = 0x21,
|
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MAX77836_PMIC_REG_INTSRC = 0x22,
|
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MAX77836_PMIC_REG_INTSRC_MASK = 0x23,
|
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MAX77836_PMIC_REG_TOPSYS_INT = 0x24,
|
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MAX77836_PMIC_REG_TOPSYS_INT_MASK = 0x26,
|
||||
MAX77836_PMIC_REG_TOPSYS_STAT = 0x28,
|
||||
MAX77836_PMIC_REG_MRSTB_CNTL = 0x2A,
|
||||
MAX77836_PMIC_REG_LSCNFG = 0x2B,
|
||||
|
||||
MAX77836_LDO_REG_CNFG1_LDO1 = 0x51,
|
||||
MAX77836_LDO_REG_CNFG2_LDO1 = 0x52,
|
||||
MAX77836_LDO_REG_CNFG1_LDO2 = 0x53,
|
||||
MAX77836_LDO_REG_CNFG2_LDO2 = 0x54,
|
||||
MAX77836_LDO_REG_CNFG_LDO_BIAS = 0x55,
|
||||
|
||||
MAX77836_COMP_REG_COMP1 = 0x60,
|
||||
|
||||
MAX77836_PMIC_REG_END,
|
||||
};
|
||||
|
||||
#define MAX77836_INTSRC_MASK_TOP_INT_SHIFT 1
|
||||
#define MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT 3
|
||||
#define MAX77836_INTSRC_MASK_TOP_INT_MASK BIT(MAX77836_INTSRC_MASK_TOP_INT_SHIFT)
|
||||
#define MAX77836_INTSRC_MASK_MUIC_CHG_INT_MASK BIT(MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT)
|
||||
|
||||
/* MAX77836 PMIC interrupts */
|
||||
#define MAX77836_TOPSYS_INT_T120C_SHIFT 0
|
||||
#define MAX77836_TOPSYS_INT_T140C_SHIFT 1
|
||||
#define MAX77836_TOPSYS_INT_T120C_MASK BIT(MAX77836_TOPSYS_INT_T120C_SHIFT)
|
||||
#define MAX77836_TOPSYS_INT_T140C_MASK BIT(MAX77836_TOPSYS_INT_T140C_SHIFT)
|
||||
|
||||
/* LDO1/LDO2 CONFIG1 register */
|
||||
#define MAX77836_CNFG1_LDO_PWRMD_SHIFT 6
|
||||
#define MAX77836_CNFG1_LDO_TV_SHIFT 0
|
||||
#define MAX77836_CNFG1_LDO_PWRMD_MASK (0x3 << MAX77836_CNFG1_LDO_PWRMD_SHIFT)
|
||||
#define MAX77836_CNFG1_LDO_TV_MASK (0x3f << MAX77836_CNFG1_LDO_TV_SHIFT)
|
||||
|
||||
/* LDO1/LDO2 CONFIG2 register */
|
||||
#define MAX77836_CNFG2_LDO_OVCLMPEN_SHIFT 7
|
||||
#define MAX77836_CNFG2_LDO_ALPMEN_SHIFT 6
|
||||
#define MAX77836_CNFG2_LDO_COMP_SHIFT 4
|
||||
#define MAX77836_CNFG2_LDO_POK_SHIFT 3
|
||||
#define MAX77836_CNFG2_LDO_ADE_SHIFT 1
|
||||
#define MAX77836_CNFG2_LDO_SS_SHIFT 0
|
||||
#define MAX77836_CNFG2_LDO_OVCLMPEN_MASK BIT(MAX77836_CNFG2_LDO_OVCLMPEN_SHIFT)
|
||||
#define MAX77836_CNFG2_LDO_ALPMEN_MASK BIT(MAX77836_CNFG2_LDO_ALPMEN_SHIFT)
|
||||
#define MAX77836_CNFG2_LDO_COMP_MASK (0x3 << MAX77836_CNFG2_LDO_COMP_SHIFT)
|
||||
#define MAX77836_CNFG2_LDO_POK_MASK BIT(MAX77836_CNFG2_LDO_POK_SHIFT)
|
||||
#define MAX77836_CNFG2_LDO_ADE_MASK BIT(MAX77836_CNFG2_LDO_ADE_SHIFT)
|
||||
#define MAX77836_CNFG2_LDO_SS_MASK BIT(MAX77836_CNFG2_LDO_SS_SHIFT)
|
||||
|
||||
/* Slave addr = 0x6C: Fuel-Gauge/Battery */
|
||||
enum max77836_fg_reg {
|
||||
MAX77836_FG_REG_VCELL_MSB = 0x02,
|
||||
MAX77836_FG_REG_VCELL_LSB = 0x03,
|
||||
MAX77836_FG_REG_SOC_MSB = 0x04,
|
||||
MAX77836_FG_REG_SOC_LSB = 0x05,
|
||||
MAX77836_FG_REG_MODE_H = 0x06,
|
||||
MAX77836_FG_REG_MODE_L = 0x07,
|
||||
MAX77836_FG_REG_VERSION_MSB = 0x08,
|
||||
MAX77836_FG_REG_VERSION_LSB = 0x09,
|
||||
MAX77836_FG_REG_HIBRT_H = 0x0A,
|
||||
MAX77836_FG_REG_HIBRT_L = 0x0B,
|
||||
MAX77836_FG_REG_CONFIG_H = 0x0C,
|
||||
MAX77836_FG_REG_CONFIG_L = 0x0D,
|
||||
MAX77836_FG_REG_VALRT_MIN = 0x14,
|
||||
MAX77836_FG_REG_VALRT_MAX = 0x15,
|
||||
MAX77836_FG_REG_CRATE_MSB = 0x16,
|
||||
MAX77836_FG_REG_CRATE_LSB = 0x17,
|
||||
MAX77836_FG_REG_VRESET = 0x18,
|
||||
MAX77836_FG_REG_FGID = 0x19,
|
||||
MAX77836_FG_REG_STATUS_H = 0x1A,
|
||||
MAX77836_FG_REG_STATUS_L = 0x1B,
|
||||
/*
|
||||
* TODO: TABLE registers
|
||||
* TODO: CMD register
|
||||
*/
|
||||
|
||||
MAX77836_FG_REG_END,
|
||||
};
|
||||
|
||||
enum max14577_irq {
|
||||
/* INT1 */
|
||||
MAX14577_IRQ_INT1_ADC,
|
||||
MAX14577_IRQ_INT1_ADCLOW,
|
||||
MAX14577_IRQ_INT1_ADCERR,
|
||||
MAX77836_IRQ_INT1_ADC1K,
|
||||
|
||||
/* INT2 */
|
||||
MAX14577_IRQ_INT2_CHGTYP,
|
||||
@@ -260,6 +373,7 @@ enum max14577_irq {
|
||||
MAX14577_IRQ_INT2_DCDTMR,
|
||||
MAX14577_IRQ_INT2_DBCHG,
|
||||
MAX14577_IRQ_INT2_VBVOLT,
|
||||
MAX77836_IRQ_INT2_VIDRM,
|
||||
|
||||
/* INT3 */
|
||||
MAX14577_IRQ_INT3_EOC,
|
||||
@@ -267,21 +381,25 @@ enum max14577_irq {
|
||||
MAX14577_IRQ_INT3_OVP,
|
||||
MAX14577_IRQ_INT3_MBCCHGERR,
|
||||
|
||||
/* TOPSYS_INT, only MAX77836 */
|
||||
MAX77836_IRQ_TOPSYS_T140C,
|
||||
MAX77836_IRQ_TOPSYS_T120C,
|
||||
|
||||
MAX14577_IRQ_NUM,
|
||||
};
|
||||
|
||||
struct max14577 {
|
||||
struct device *dev;
|
||||
struct i2c_client *i2c; /* Slave addr = 0x4A */
|
||||
struct i2c_client *i2c_pmic; /* Slave addr = 0x46 */
|
||||
enum maxim_device_type dev_type;
|
||||
|
||||
struct regmap *regmap;
|
||||
struct regmap *regmap; /* For MUIC and Charger */
|
||||
struct regmap *regmap_pmic;
|
||||
|
||||
struct regmap_irq_chip_data *irq_data;
|
||||
struct regmap_irq_chip_data *irq_data; /* For MUIC and Charger */
|
||||
struct regmap_irq_chip_data *irq_data_pmic;
|
||||
int irq;
|
||||
|
||||
/* Device ID */
|
||||
u8 vendor_id; /* Vendor Identification */
|
||||
u8 device_id; /* Chip Version */
|
||||
};
|
||||
|
||||
/* MAX14577 shared regmap API function */
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
* max14577.h - Driver for the Maxim 14577
|
||||
* max14577.h - Driver for the Maxim 14577/77836
|
||||
*
|
||||
* Copyright (C) 2013 Samsung Electrnoics
|
||||
* Copyright (C) 2014 Samsung Electrnoics
|
||||
* Chanwoo Choi <cw00.choi@samsung.com>
|
||||
* Krzysztof Kozlowski <k.kozlowski@samsung.com>
|
||||
*
|
||||
@@ -20,6 +20,9 @@
|
||||
* MAX14577 has MUIC, Charger devices.
|
||||
* The devices share the same I2C bus and interrupt line
|
||||
* included in this mfd driver.
|
||||
*
|
||||
* MAX77836 has additional PMIC and Fuel-Gauge on different I2C slave
|
||||
* addresses.
|
||||
*/
|
||||
|
||||
#ifndef __MAX14577_H__
|
||||
@@ -32,7 +35,17 @@ enum max14577_regulators {
|
||||
MAX14577_SAFEOUT = 0,
|
||||
MAX14577_CHARGER,
|
||||
|
||||
MAX14577_REG_MAX,
|
||||
MAX14577_REGULATOR_NUM,
|
||||
};
|
||||
|
||||
/* MAX77836 regulator IDs */
|
||||
enum max77836_regulators {
|
||||
MAX77836_SAFEOUT = 0,
|
||||
MAX77836_CHARGER,
|
||||
MAX77836_LDO1,
|
||||
MAX77836_LDO2,
|
||||
|
||||
MAX77836_REGULATOR_NUM,
|
||||
};
|
||||
|
||||
struct max14577_regulator_platform_data {
|
||||
|
||||
@@ -415,7 +415,7 @@ struct palmas_usb {
|
||||
struct palmas *palmas;
|
||||
struct device *dev;
|
||||
|
||||
struct extcon_dev edev;
|
||||
struct extcon_dev *edev;
|
||||
|
||||
int id_otg_irq;
|
||||
int id_irq;
|
||||
|
||||
@@ -64,7 +64,7 @@ struct miscdevice {
|
||||
umode_t mode;
|
||||
};
|
||||
|
||||
extern int misc_register(struct miscdevice * misc);
|
||||
extern int misc_register(struct miscdevice *misc);
|
||||
extern int misc_deregister(struct miscdevice *misc);
|
||||
|
||||
#define MODULE_ALIAS_MISCDEV(minor) \
|
||||
|
||||
Reference in New Issue
Block a user