Merge tag 'clk-for-linus-3.10' of git://git.linaro.org/people/mturquette/linux
Pull clock framework update from Michael Turquette: "The common clock framework changes for 3.10 include many fixes for existing platforms, as well as adoption of the framework by new platforms and devices. Some long-needed fixes to the core framework are here as well as new features such as improved initialization of clocks from DT as well as framework reentrancy for nested clock operations." * tag 'clk-for-linus-3.10' of git://git.linaro.org/people/mturquette/linux: (44 commits) clk: add clk_ignore_unused option to keep boot clocks on clk: ux500: fix mismatched types clk: vexpress: Add separate SP810 driver clk: si5351: make clk-si5351 depend on CONFIG_OF clk: export __clk_get_flags for modular clock providers clk: vt8500: Missing breaks in vtwm_pll_round_rate/_set_rate. clk: sunxi: Unify oscillator clock clk: composite: allow fixed rates & fixed dividers clk: composite: rename 'div' references to 'rate' clk: add si5351 i2c common clock driver clk: add device tree fixed-factor-clock binding support clk: Properly handle notifier return values clk: ux500: abx500: Define clock tree for ab850x clk: ux500: Add support for sysctrl clocks clk: mvebu: Fix valid value range checking for cpu_freq_select clk: Fixup locking issues for clk_set_parent clk: Fixup errorhandling for clk_set_parent clk: Restructure code for __clk_reparent clk: sunxi: drop an unnecesary kmalloc clk: sunxi: drop CLK_IGNORE_UNUSED ...
This commit is contained in:
Linus Torvalds
@@ -152,7 +152,7 @@ struct clk {
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}, \
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.reg = _reg, \
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.shift = _shift, \
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.width = _width, \
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.mask = BIT(_width) - 1, \
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.flags = _mux_flags, \
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.lock = _lock, \
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}; \
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@@ -45,6 +45,14 @@ struct clk_hw;
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* undo any work done in the @prepare callback. Called with
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* prepare_lock held.
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*
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* @is_prepared: Queries the hardware to determine if the clock is prepared.
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* This function is allowed to sleep. Optional, if this op is not
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* set then the prepare count will be used.
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*
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* @unprepare_unused: Unprepare the clock atomically. Only called from
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* clk_disable_unused for prepare clocks with special needs.
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* Called with prepare mutex held. This function may sleep.
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*
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* @enable: Enable the clock atomically. This must not return until the
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* clock is generating a valid clock signal, usable by consumer
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* devices. Called with enable_lock held. This function must not
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@@ -108,6 +116,8 @@ struct clk_hw;
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struct clk_ops {
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int (*prepare)(struct clk_hw *hw);
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void (*unprepare)(struct clk_hw *hw);
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int (*is_prepared)(struct clk_hw *hw);
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void (*unprepare_unused)(struct clk_hw *hw);
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int (*enable)(struct clk_hw *hw);
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void (*disable)(struct clk_hw *hw);
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int (*is_enabled)(struct clk_hw *hw);
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@@ -239,9 +249,14 @@ struct clk_div_table {
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* CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
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* register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
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* the raw value read from the register, with the value of zero considered
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* invalid
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* invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
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* CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
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* the hardware register
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* CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
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* CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
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* Some hardware implementations gracefully handle this case and allow a
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* zero divisor by not modifying their input clock
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* (divide by one / bypass).
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*/
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struct clk_divider {
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struct clk_hw hw;
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@@ -255,6 +270,7 @@ struct clk_divider {
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#define CLK_DIVIDER_ONE_BASED BIT(0)
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#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
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#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
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extern const struct clk_ops clk_divider_ops;
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struct clk *clk_register_divider(struct device *dev, const char *name,
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@@ -274,7 +290,7 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
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* @reg: register controlling multiplexer
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* @shift: shift to multiplexer bit field
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* @width: width of mutliplexer bit field
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* @num_clks: number of parent clocks
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* @flags: hardware-specific flags
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* @lock: register lock
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*
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* Clock with multiple selectable parents. Implements .get_parent, .set_parent
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@@ -287,8 +303,9 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
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struct clk_mux {
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struct clk_hw hw;
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void __iomem *reg;
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u32 *table;
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u32 mask;
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u8 shift;
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u8 width;
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u8 flags;
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spinlock_t *lock;
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};
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@@ -297,11 +314,19 @@ struct clk_mux {
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#define CLK_MUX_INDEX_BIT BIT(1)
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extern const struct clk_ops clk_mux_ops;
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struct clk *clk_register_mux(struct device *dev, const char *name,
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const char **parent_names, u8 num_parents, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_mux_flags, spinlock_t *lock);
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struct clk *clk_register_mux_table(struct device *dev, const char *name,
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const char **parent_names, u8 num_parents, unsigned long flags,
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void __iomem *reg, u8 shift, u32 mask,
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u8 clk_mux_flags, u32 *table, spinlock_t *lock);
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void of_fixed_factor_clk_setup(struct device_node *node);
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/**
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* struct clk_fixed_factor - fixed multiplier and divider clock
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*
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@@ -325,6 +350,37 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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unsigned int mult, unsigned int div);
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/***
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* struct clk_composite - aggregate clock of mux, divider and gate clocks
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*
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* @hw: handle between common and hardware-specific interfaces
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* @mux_hw: handle between composite and hardware-specific mux clock
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* @rate_hw: handle between composite and hardware-specific rate clock
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* @gate_hw: handle between composite and hardware-specific gate clock
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* @mux_ops: clock ops for mux
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* @rate_ops: clock ops for rate
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* @gate_ops: clock ops for gate
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*/
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struct clk_composite {
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struct clk_hw hw;
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struct clk_ops ops;
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struct clk_hw *mux_hw;
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struct clk_hw *rate_hw;
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struct clk_hw *gate_hw;
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const struct clk_ops *mux_ops;
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const struct clk_ops *rate_ops;
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const struct clk_ops *gate_ops;
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};
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struct clk *clk_register_composite(struct device *dev, const char *name,
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const char **parent_names, int num_parents,
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struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
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struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
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struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
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unsigned long flags);
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/**
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* clk_register - allocate a new clock, register it and return an opaque cookie
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* @dev: device that is registering this clock
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@@ -351,6 +407,7 @@ unsigned int __clk_get_enable_count(struct clk *clk);
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unsigned int __clk_get_prepare_count(struct clk *clk);
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unsigned long __clk_get_rate(struct clk *clk);
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unsigned long __clk_get_flags(struct clk *clk);
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bool __clk_is_prepared(struct clk *clk);
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bool __clk_is_enabled(struct clk *clk);
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struct clk *__clk_lookup(const char *name);
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+4
-4
@@ -28,16 +28,16 @@ struct clk;
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* PRE_RATE_CHANGE - called immediately before the clk rate is changed,
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* to indicate that the rate change will proceed. Drivers must
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* immediately terminate any operations that will be affected by the
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* rate change. Callbacks may either return NOTIFY_DONE or
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* NOTIFY_STOP.
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* rate change. Callbacks may either return NOTIFY_DONE, NOTIFY_OK,
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* NOTIFY_STOP or NOTIFY_BAD.
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*
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* ABORT_RATE_CHANGE: called if the rate change failed for some reason
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* after PRE_RATE_CHANGE. In this case, all registered notifiers on
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* the clk will be called with ABORT_RATE_CHANGE. Callbacks must
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* always return NOTIFY_DONE.
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* always return NOTIFY_DONE or NOTIFY_OK.
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*
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* POST_RATE_CHANGE - called after the clk rate change has successfully
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* completed. Callbacks must always return NOTIFY_DONE.
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* completed. Callbacks must always return NOTIFY_DONE or NOTIFY_OK.
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*
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*/
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#define PRE_RATE_CHANGE BIT(0)
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@@ -0,0 +1,22 @@
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/*
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* Copyright 2012 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __LINUX_CLK_SUNXI_H_
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#define __LINUX_CLK_SUNXI_H_
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void __init sunxi_init_clocks(void);
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#endif
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@@ -0,0 +1,114 @@
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/*
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* Si5351A/B/C programmable clock generator platform_data.
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*/
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#ifndef __LINUX_PLATFORM_DATA_SI5351_H__
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#define __LINUX_PLATFORM_DATA_SI5351_H__
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struct clk;
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/**
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* enum si5351_variant - SiLabs Si5351 chip variant
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* @SI5351_VARIANT_A: Si5351A (8 output clocks, XTAL input)
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* @SI5351_VARIANT_A3: Si5351A MSOP10 (3 output clocks, XTAL input)
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* @SI5351_VARIANT_B: Si5351B (8 output clocks, XTAL/VXCO input)
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* @SI5351_VARIANT_C: Si5351C (8 output clocks, XTAL/CLKIN input)
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*/
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enum si5351_variant {
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SI5351_VARIANT_A = 1,
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SI5351_VARIANT_A3 = 2,
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SI5351_VARIANT_B = 3,
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SI5351_VARIANT_C = 4,
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};
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/**
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* enum si5351_pll_src - Si5351 pll clock source
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* @SI5351_PLL_SRC_DEFAULT: default, do not change eeprom config
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* @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input
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* @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only)
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*/
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enum si5351_pll_src {
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SI5351_PLL_SRC_DEFAULT = 0,
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SI5351_PLL_SRC_XTAL = 1,
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SI5351_PLL_SRC_CLKIN = 2,
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};
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/**
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* enum si5351_multisynth_src - Si5351 multisynth clock source
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* @SI5351_MULTISYNTH_SRC_DEFAULT: default, do not change eeprom config
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* @SI5351_MULTISYNTH_SRC_VCO0: multisynth source clock is VCO0
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* @SI5351_MULTISYNTH_SRC_VCO1: multisynth source clock is VCO1/VXCO
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*/
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enum si5351_multisynth_src {
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SI5351_MULTISYNTH_SRC_DEFAULT = 0,
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SI5351_MULTISYNTH_SRC_VCO0 = 1,
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SI5351_MULTISYNTH_SRC_VCO1 = 2,
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};
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/**
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* enum si5351_clkout_src - Si5351 clock output clock source
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* @SI5351_CLKOUT_SRC_DEFAULT: default, do not change eeprom config
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* @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N
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* @SI5351_CLKOUT_SRC_MSYNTH_0_4: clkout N source clock is multisynth 0 (N<4)
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* or 4 (N>=4)
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* @SI5351_CLKOUT_SRC_XTAL: clkout N source clock is XTAL
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* @SI5351_CLKOUT_SRC_CLKIN: clkout N source clock is CLKIN (Si5351C only)
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*/
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enum si5351_clkout_src {
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SI5351_CLKOUT_SRC_DEFAULT = 0,
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SI5351_CLKOUT_SRC_MSYNTH_N = 1,
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SI5351_CLKOUT_SRC_MSYNTH_0_4 = 2,
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SI5351_CLKOUT_SRC_XTAL = 3,
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SI5351_CLKOUT_SRC_CLKIN = 4,
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};
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/**
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* enum si5351_drive_strength - Si5351 clock output drive strength
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* @SI5351_DRIVE_DEFAULT: default, do not change eeprom config
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* @SI5351_DRIVE_2MA: 2mA clock output drive strength
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* @SI5351_DRIVE_4MA: 4mA clock output drive strength
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* @SI5351_DRIVE_6MA: 6mA clock output drive strength
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* @SI5351_DRIVE_8MA: 8mA clock output drive strength
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*/
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enum si5351_drive_strength {
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SI5351_DRIVE_DEFAULT = 0,
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SI5351_DRIVE_2MA = 2,
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SI5351_DRIVE_4MA = 4,
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SI5351_DRIVE_6MA = 6,
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SI5351_DRIVE_8MA = 8,
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};
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/**
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* struct si5351_clkout_config - Si5351 clock output configuration
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* @clkout: clkout number
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* @multisynth_src: multisynth source clock
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* @clkout_src: clkout source clock
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* @pll_master: if true, clkout can also change pll rate
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* @drive: output drive strength
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* @rate: initial clkout rate, or default if 0
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*/
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struct si5351_clkout_config {
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enum si5351_multisynth_src multisynth_src;
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enum si5351_clkout_src clkout_src;
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enum si5351_drive_strength drive;
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bool pll_master;
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unsigned long rate;
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};
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/**
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* struct si5351_platform_data - Platform data for the Si5351 clock driver
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* @variant: Si5351 chip variant
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* @clk_xtal: xtal input clock
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* @clk_clkin: clkin input clock
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* @pll_src: array of pll source clock setting
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* @clkout: array of clkout configuration
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*/
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struct si5351_platform_data {
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enum si5351_variant variant;
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struct clk *clk_xtal;
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struct clk *clk_clkin;
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enum si5351_pll_src pll_src[2];
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struct si5351_clkout_config clkout[8];
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};
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#endif
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