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iommu/tegra241-cmdqv: Add IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV support

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Add a new vEVENTQ type for VINTFs that are assigned to the user space.
Simply report the two 64-bit LVCMDQ_ERR_MAPs register values.

Link: https://patch.msgid.link/r/68161a980da41fa5022841209638aeff258557b5.1752126748.git.nicolinc@nvidia.com
Reviewed-by: Alok Tiwari <alok.a.tiwari@oracle.com>
Reviewed-by: Pranjal Shrivastava <praan@google.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Nicolin Chen
2025-07-11 14:34:36 -03:00
committed by Jason Gunthorpe
parent 4dc0d12474
commit 32b2d3a57e
2 changed files with 37 additions and 0 deletions
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include/uapi/linux/iommufd.h
+15
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@@ -1146,10 +1146,12 @@ struct iommufd_vevent_header {
* enum iommu_veventq_type - Virtual Event Queue Type
* @IOMMU_VEVENTQ_TYPE_DEFAULT: Reserved for future use
* @IOMMU_VEVENTQ_TYPE_ARM_SMMUV3: ARM SMMUv3 Virtual Event Queue
* @IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV Extension IRQ
*/
enum iommu_veventq_type {
IOMMU_VEVENTQ_TYPE_DEFAULT = 0,
IOMMU_VEVENTQ_TYPE_ARM_SMMUV3 = 1,
IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV = 2,
};
/**
@@ -1173,6 +1175,19 @@ struct iommu_vevent_arm_smmuv3 {
__aligned_le64 evt[4];
};
/**
* struct iommu_vevent_tegra241_cmdqv - Tegra241 CMDQV IRQ
* (IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV)
* @lvcmdq_err_map: 128-bit logical vcmdq error map, little-endian.
* (Refer to register LVCMDQ_ERR_MAPs per VINTF )
*
* The 128-bit register value from HW exclusively reflect the error bits for a
* Virtual Interface represented by a vIOMMU object. Read and report directly.
*/
struct iommu_vevent_tegra241_cmdqv {
__aligned_le64 lvcmdq_err_map[2];
};
/**
* struct iommu_veventq_alloc - ioctl(IOMMU_VEVENTQ_ALLOC)
* @size: sizeof(struct iommu_veventq_alloc)