Merge tag 'char-misc-3.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char / misc driver patches from Greg KH: "Here's the big driver misc / char pull request for 3.17-rc1. Lots of things in here, the thunderbolt support for Apple laptops, some other new drivers, testing fixes, and other good things. All have been in linux-next for a long time" * tag 'char-misc-3.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (119 commits) misc: bh1780: Introduce the use of devm_kzalloc Lattice ECP3 FPGA: Correct endianness drivers/misc/ti-st: Load firmware from ti-connectivity directory. dt-bindings: extcon: Add support for SM5502 MUIC device extcon: sm5502: Change internal hardware switch according to cable type extcon: sm5502: Detect cable state after completing platform booting extcon: sm5502: Add support new SM5502 extcon device driver extcon: arizona: Get MICVDD against extcon device extcon: Remove unnecessary OOM messages misc: vexpress: Fix sparse non static symbol warnings mei: drop unused hw dependent fw status functions misc: bh1770glc: Use managed functions pcmcia: remove DEFINE_PCI_DEVICE_TABLE usage misc: remove DEFINE_PCI_DEVICE_TABLE usage ipack: Replace DEFINE_PCI_DEVICE_TABLE macro use drivers/char/dsp56k.c: drop check for negativity of unsigned parameter mei: fix return value on disconnect timeout mei: don't schedule suspend in pm idle mei: start disconnect request timer consistently mei: reset client connection state on timeout ...
This commit is contained in:
Linus Torvalds
@@ -268,6 +268,9 @@
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VMLINUX_SYMBOL(__start_pci_fixups_suspend) = .; \
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*(.pci_fixup_suspend) \
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VMLINUX_SYMBOL(__end_pci_fixups_suspend) = .; \
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VMLINUX_SYMBOL(__start_pci_fixups_suspend_late) = .; \
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*(.pci_fixup_suspend_late) \
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VMLINUX_SYMBOL(__end_pci_fixups_suspend_late) = .; \
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} \
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\
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/* Built-in firmware blobs */ \
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@@ -0,0 +1,287 @@
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/*
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* sm5502.h
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __LINUX_EXTCON_SM5502_H
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#define __LINUX_EXTCON_SM5502_H
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enum sm5502_types {
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TYPE_SM5502,
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};
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/* SM5502 registers */
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enum sm5502_reg {
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SM5502_REG_DEVICE_ID = 0x01,
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SM5502_REG_CONTROL,
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SM5502_REG_INT1,
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SM5502_REG_INT2,
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SM5502_REG_INTMASK1,
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SM5502_REG_INTMASK2,
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SM5502_REG_ADC,
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SM5502_REG_TIMING_SET1,
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SM5502_REG_TIMING_SET2,
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SM5502_REG_DEV_TYPE1,
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SM5502_REG_DEV_TYPE2,
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SM5502_REG_BUTTON1,
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SM5502_REG_BUTTON2,
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SM5502_REG_CAR_KIT_STATUS,
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SM5502_REG_RSVD1,
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SM5502_REG_RSVD2,
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SM5502_REG_RSVD3,
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SM5502_REG_RSVD4,
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SM5502_REG_MANUAL_SW1,
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SM5502_REG_MANUAL_SW2,
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SM5502_REG_DEV_TYPE3,
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SM5502_REG_RSVD5,
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SM5502_REG_RSVD6,
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SM5502_REG_RSVD7,
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SM5502_REG_RSVD8,
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SM5502_REG_RSVD9,
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SM5502_REG_RESET,
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SM5502_REG_RSVD10,
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SM5502_REG_RESERVED_ID1,
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SM5502_REG_RSVD11,
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SM5502_REG_RSVD12,
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SM5502_REG_RESERVED_ID2,
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SM5502_REG_RSVD13,
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SM5502_REG_OCP,
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SM5502_REG_RSVD14,
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SM5502_REG_RSVD15,
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SM5502_REG_RSVD16,
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SM5502_REG_RSVD17,
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SM5502_REG_RSVD18,
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SM5502_REG_RSVD19,
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SM5502_REG_RSVD20,
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SM5502_REG_RSVD21,
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SM5502_REG_RSVD22,
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SM5502_REG_RSVD23,
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SM5502_REG_RSVD24,
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SM5502_REG_RSVD25,
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SM5502_REG_RSVD26,
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SM5502_REG_RSVD27,
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SM5502_REG_RSVD28,
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SM5502_REG_RSVD29,
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SM5502_REG_RSVD30,
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SM5502_REG_RSVD31,
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SM5502_REG_RSVD32,
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SM5502_REG_RSVD33,
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SM5502_REG_RSVD34,
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SM5502_REG_RSVD35,
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SM5502_REG_RSVD36,
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SM5502_REG_RESERVED_ID3,
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SM5502_REG_END,
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};
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/* Define SM5502 MASK/SHIFT constant */
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#define SM5502_REG_DEVICE_ID_VENDOR_SHIFT 0
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#define SM5502_REG_DEVICE_ID_VERSION_SHIFT 3
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#define SM5502_REG_DEVICE_ID_VENDOR_MASK (0x3 << SM5502_REG_DEVICE_ID_VENDOR_SHIFT)
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#define SM5502_REG_DEVICE_ID_VERSION_MASK (0x1f << SM5502_REG_DEVICE_ID_VERSION_SHIFT)
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#define SM5502_REG_CONTROL_MASK_INT_SHIFT 0
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#define SM5502_REG_CONTROL_WAIT_SHIFT 1
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#define SM5502_REG_CONTROL_MANUAL_SW_SHIFT 2
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#define SM5502_REG_CONTROL_RAW_DATA_SHIFT 3
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#define SM5502_REG_CONTROL_SW_OPEN_SHIFT 4
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#define SM5502_REG_CONTROL_MASK_INT_MASK (0x1 << SM5502_REG_CONTROL_MASK_INT_SHIFT)
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#define SM5502_REG_CONTROL_WAIT_MASK (0x1 << SM5502_REG_CONTROL_WAIT_SHIFT)
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#define SM5502_REG_CONTROL_MANUAL_SW_MASK (0x1 << SM5502_REG_CONTROL_MANUAL_SW_SHIFT)
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#define SM5502_REG_CONTROL_RAW_DATA_MASK (0x1 << SM5502_REG_CONTROL_RAW_DATA_SHIFT)
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#define SM5502_REG_CONTROL_SW_OPEN_MASK (0x1 << SM5502_REG_CONTROL_SW_OPEN_SHIFT)
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#define SM5502_REG_INTM1_ATTACH_SHIFT 0
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#define SM5502_REG_INTM1_DETACH_SHIFT 1
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#define SM5502_REG_INTM1_KP_SHIFT 2
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#define SM5502_REG_INTM1_LKP_SHIFT 3
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#define SM5502_REG_INTM1_LKR_SHIFT 4
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#define SM5502_REG_INTM1_OVP_EVENT_SHIFT 5
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#define SM5502_REG_INTM1_OCP_EVENT_SHIFT 6
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#define SM5502_REG_INTM1_OVP_OCP_DIS_SHIFT 7
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#define SM5502_REG_INTM1_ATTACH_MASK (0x1 << SM5502_REG_INTM1_ATTACH_SHIFT)
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#define SM5502_REG_INTM1_DETACH_MASK (0x1 << SM5502_REG_INTM1_DETACH_SHIFT)
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#define SM5502_REG_INTM1_KP_MASK (0x1 << SM5502_REG_INTM1_KP_SHIFT)
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#define SM5502_REG_INTM1_LKP_MASK (0x1 << SM5502_REG_INTM1_LKP_SHIFT)
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#define SM5502_REG_INTM1_LKR_MASK (0x1 << SM5502_REG_INTM1_LKR_SHIFT)
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#define SM5502_REG_INTM1_OVP_EVENT_MASK (0x1 << SM5502_REG_INTM1_OVP_EVENT_SHIFT)
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#define SM5502_REG_INTM1_OCP_EVENT_MASK (0x1 << SM5502_REG_INTM1_OCP_EVENT_SHIFT)
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#define SM5502_REG_INTM1_OVP_OCP_DIS_MASK (0x1 << SM5502_REG_INTM1_OVP_OCP_DIS_SHIFT)
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#define SM5502_REG_INTM2_VBUS_DET_SHIFT 0
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#define SM5502_REG_INTM2_REV_ACCE_SHIFT 1
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#define SM5502_REG_INTM2_ADC_CHG_SHIFT 2
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#define SM5502_REG_INTM2_STUCK_KEY_SHIFT 3
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#define SM5502_REG_INTM2_STUCK_KEY_RCV_SHIFT 4
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#define SM5502_REG_INTM2_MHL_SHIFT 5
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#define SM5502_REG_INTM2_VBUS_DET_MASK (0x1 << SM5502_REG_INTM2_VBUS_DET_SHIFT)
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#define SM5502_REG_INTM2_REV_ACCE_MASK (0x1 << SM5502_REG_INTM2_REV_ACCE_SHIFT)
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#define SM5502_REG_INTM2_ADC_CHG_MASK (0x1 << SM5502_REG_INTM2_ADC_CHG_SHIFT)
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#define SM5502_REG_INTM2_STUCK_KEY_MASK (0x1 << SM5502_REG_INTM2_STUCK_KEY_SHIFT)
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#define SM5502_REG_INTM2_STUCK_KEY_RCV_MASK (0x1 << SM5502_REG_INTM2_STUCK_KEY_RCV_SHIFT)
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#define SM5502_REG_INTM2_MHL_MASK (0x1 << SM5502_REG_INTM2_MHL_SHIFT)
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#define SM5502_REG_ADC_SHIFT 0
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#define SM5502_REG_ADC_MASK (0x1f << SM5502_REG_ADC_SHIFT)
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#define SM5502_REG_TIMING_SET1_KEY_PRESS_SHIFT 4
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#define SM5502_REG_TIMING_SET1_KEY_PRESS_MASK (0xf << SM5502_REG_TIMING_SET1_KEY_PRESS_SHIFT)
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#define TIMING_KEY_PRESS_100MS 0x0
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#define TIMING_KEY_PRESS_200MS 0x1
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#define TIMING_KEY_PRESS_300MS 0x2
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#define TIMING_KEY_PRESS_400MS 0x3
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#define TIMING_KEY_PRESS_500MS 0x4
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#define TIMING_KEY_PRESS_600MS 0x5
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#define TIMING_KEY_PRESS_700MS 0x6
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#define TIMING_KEY_PRESS_800MS 0x7
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#define TIMING_KEY_PRESS_900MS 0x8
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#define TIMING_KEY_PRESS_1000MS 0x9
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#define SM5502_REG_TIMING_SET1_ADC_DET_SHIFT 0
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#define SM5502_REG_TIMING_SET1_ADC_DET_MASK (0xf << SM5502_REG_TIMING_SET1_ADC_DET_SHIFT)
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#define TIMING_ADC_DET_50MS 0x0
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#define TIMING_ADC_DET_100MS 0x1
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#define TIMING_ADC_DET_150MS 0x2
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#define TIMING_ADC_DET_200MS 0x3
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#define TIMING_ADC_DET_300MS 0x4
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#define TIMING_ADC_DET_400MS 0x5
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#define TIMING_ADC_DET_500MS 0x6
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#define TIMING_ADC_DET_600MS 0x7
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#define TIMING_ADC_DET_700MS 0x8
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#define TIMING_ADC_DET_800MS 0x9
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#define TIMING_ADC_DET_900MS 0xA
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#define TIMING_ADC_DET_1000MS 0xB
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#define SM5502_REG_TIMING_SET2_SW_WAIT_SHIFT 4
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#define SM5502_REG_TIMING_SET2_SW_WAIT_MASK (0xf << SM5502_REG_TIMING_SET2_SW_WAIT_SHIFT)
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#define TIMING_SW_WAIT_10MS 0x0
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#define TIMING_SW_WAIT_30MS 0x1
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#define TIMING_SW_WAIT_50MS 0x2
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#define TIMING_SW_WAIT_70MS 0x3
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#define TIMING_SW_WAIT_90MS 0x4
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#define TIMING_SW_WAIT_110MS 0x5
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#define TIMING_SW_WAIT_130MS 0x6
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#define TIMING_SW_WAIT_150MS 0x7
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#define TIMING_SW_WAIT_170MS 0x8
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#define TIMING_SW_WAIT_190MS 0x9
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#define TIMING_SW_WAIT_210MS 0xA
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#define SM5502_REG_TIMING_SET2_LONG_KEY_SHIFT 0
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#define SM5502_REG_TIMING_SET2_LONG_KEY_MASK (0xf << SM5502_REG_TIMING_SET2_LONG_KEY_SHIFT)
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#define TIMING_LONG_KEY_300MS 0x0
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#define TIMING_LONG_KEY_400MS 0x1
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#define TIMING_LONG_KEY_500MS 0x2
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#define TIMING_LONG_KEY_600MS 0x3
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#define TIMING_LONG_KEY_700MS 0x4
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#define TIMING_LONG_KEY_800MS 0x5
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#define TIMING_LONG_KEY_900MS 0x6
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#define TIMING_LONG_KEY_1000MS 0x7
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#define TIMING_LONG_KEY_1100MS 0x8
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#define TIMING_LONG_KEY_1200MS 0x9
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#define TIMING_LONG_KEY_1300MS 0xA
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#define TIMING_LONG_KEY_1400MS 0xB
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#define TIMING_LONG_KEY_1500MS 0xC
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#define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_SHIFT 0
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#define SM5502_REG_DEV_TYPE1_AUDIO_TYPE2_SHIFT 1
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#define SM5502_REG_DEV_TYPE1_USB_SDP_SHIFT 2
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#define SM5502_REG_DEV_TYPE1_UART_SHIFT 3
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#define SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_SHIFT 4
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#define SM5502_REG_DEV_TYPE1_USB_CHG_SHIFT 5
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#define SM5502_REG_DEV_TYPE1_DEDICATED_CHG_SHIFT 6
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#define SM5502_REG_DEV_TYPE1_USB_OTG_SHIFT 7
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#define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_MASK (0x1 << SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_SHIFT)
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#define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1__MASK (0x1 << SM5502_REG_DEV_TYPE1_AUDIO_TYPE2_SHIFT)
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#define SM5502_REG_DEV_TYPE1_USB_SDP_MASK (0x1 << SM5502_REG_DEV_TYPE1_USB_SDP_SHIFT)
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#define SM5502_REG_DEV_TYPE1_UART_MASK (0x1 << SM5502_REG_DEV_TYPE1_UART_SHIFT)
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#define SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_MASK (0x1 << SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_SHIFT)
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#define SM5502_REG_DEV_TYPE1_USB_CHG_MASK (0x1 << SM5502_REG_DEV_TYPE1_USB_CHG_SHIFT)
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#define SM5502_REG_DEV_TYPE1_DEDICATED_CHG_MASK (0x1 << SM5502_REG_DEV_TYPE1_DEDICATED_CHG_SHIFT)
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#define SM5502_REG_DEV_TYPE1_USB_OTG_MASK (0x1 << SM5502_REG_DEV_TYPE1_USB_OTG_SHIFT)
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#define SM5502_REG_DEV_TYPE2_JIG_USB_ON_SHIFT 0
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#define SM5502_REG_DEV_TYPE2_JIG_USB_OFF_SHIFT 1
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#define SM5502_REG_DEV_TYPE2_JIG_UART_ON_SHIFT 2
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#define SM5502_REG_DEV_TYPE2_JIG_UART_OFF_SHIFT 3
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#define SM5502_REG_DEV_TYPE2_PPD_SHIFT 4
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#define SM5502_REG_DEV_TYPE2_TTY_SHIFT 5
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#define SM5502_REG_DEV_TYPE2_AV_CABLE_SHIFT 6
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#define SM5502_REG_DEV_TYPE2_JIG_USB_ON_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_USB_ON_SHIFT)
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#define SM5502_REG_DEV_TYPE2_JIG_USB_OFF_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_USB_OFF_SHIFT)
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#define SM5502_REG_DEV_TYPE2_JIG_UART_ON_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_UART_ON_SHIFT)
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#define SM5502_REG_DEV_TYPE2_JIG_UART_OFF_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_UART_OFF_SHIFT)
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#define SM5502_REG_DEV_TYPE2_PPD_MASK (0x1 << SM5502_REG_DEV_TYPE2_PPD_SHIFT)
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#define SM5502_REG_DEV_TYPE2_TTY_MASK (0x1 << SM5502_REG_DEV_TYPE2_TTY_SHIFT)
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#define SM5502_REG_DEV_TYPE2_AV_CABLE_MASK (0x1 << SM5502_REG_DEV_TYPE2_AV_CABLE_SHIFT)
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#define SM5502_REG_MANUAL_SW1_VBUSIN_SHIFT 0
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#define SM5502_REG_MANUAL_SW1_DP_SHIFT 2
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#define SM5502_REG_MANUAL_SW1_DM_SHIFT 5
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#define SM5502_REG_MANUAL_SW1_VBUSIN_MASK (0x3 << SM5502_REG_MANUAL_SW1_VBUSIN_SHIFT)
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#define SM5502_REG_MANUAL_SW1_DP_MASK (0x7 << SM5502_REG_MANUAL_SW1_DP_SHIFT)
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#define SM5502_REG_MANUAL_SW1_DM_MASK (0x7 << SM5502_REG_MANUAL_SW1_DM_SHIFT)
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#define VBUSIN_SWITCH_OPEN 0x0
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#define VBUSIN_SWITCH_VBUSOUT 0x1
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#define VBUSIN_SWITCH_MIC 0x2
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#define VBUSIN_SWITCH_VBUSOUT_WITH_USB 0x3
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#define DM_DP_CON_SWITCH_OPEN 0x0
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#define DM_DP_CON_SWITCH_USB 0x1
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#define DM_DP_CON_SWITCH_AUDIO 0x2
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#define DM_DP_CON_SWITCH_UART 0x3
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#define DM_DP_SWITCH_OPEN ((DM_DP_CON_SWITCH_OPEN <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
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| (DM_DP_CON_SWITCH_OPEN <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
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#define DM_DP_SWITCH_USB ((DM_DP_CON_SWITCH_USB <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
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| (DM_DP_CON_SWITCH_USB <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
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#define DM_DP_SWITCH_AUDIO ((DM_DP_CON_SWITCH_AUDIO <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
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| (DM_DP_CON_SWITCH_AUDIO <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
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#define DM_DP_SWITCH_UART ((DM_DP_CON_SWITCH_UART <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
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| (DM_DP_CON_SWITCH_UART <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
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/* SM5502 Interrupts */
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enum sm5502_irq {
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/* INT1 */
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SM5502_IRQ_INT1_ATTACH,
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SM5502_IRQ_INT1_DETACH,
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SM5502_IRQ_INT1_KP,
|
||||
SM5502_IRQ_INT1_LKP,
|
||||
SM5502_IRQ_INT1_LKR,
|
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SM5502_IRQ_INT1_OVP_EVENT,
|
||||
SM5502_IRQ_INT1_OCP_EVENT,
|
||||
SM5502_IRQ_INT1_OVP_OCP_DIS,
|
||||
|
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/* INT2 */
|
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SM5502_IRQ_INT2_VBUS_DET,
|
||||
SM5502_IRQ_INT2_REV_ACCE,
|
||||
SM5502_IRQ_INT2_ADC_CHG,
|
||||
SM5502_IRQ_INT2_STUCK_KEY,
|
||||
SM5502_IRQ_INT2_STUCK_KEY_RCV,
|
||||
SM5502_IRQ_INT2_MHL,
|
||||
|
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SM5502_IRQ_NUM,
|
||||
};
|
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|
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#define SM5502_IRQ_INT1_ATTACH_MASK BIT(0)
|
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#define SM5502_IRQ_INT1_DETACH_MASK BIT(1)
|
||||
#define SM5502_IRQ_INT1_KP_MASK BIT(2)
|
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#define SM5502_IRQ_INT1_LKP_MASK BIT(3)
|
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#define SM5502_IRQ_INT1_LKR_MASK BIT(4)
|
||||
#define SM5502_IRQ_INT1_OVP_EVENT_MASK BIT(5)
|
||||
#define SM5502_IRQ_INT1_OCP_EVENT_MASK BIT(6)
|
||||
#define SM5502_IRQ_INT1_OVP_OCP_DIS_MASK BIT(7)
|
||||
#define SM5502_IRQ_INT2_VBUS_DET_MASK BIT(0)
|
||||
#define SM5502_IRQ_INT2_REV_ACCE_MASK BIT(1)
|
||||
#define SM5502_IRQ_INT2_ADC_CHG_MASK BIT(2)
|
||||
#define SM5502_IRQ_INT2_STUCK_KEY_MASK BIT(3)
|
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#define SM5502_IRQ_INT2_STUCK_KEY_RCV_MASK BIT(4)
|
||||
#define SM5502_IRQ_INT2_MHL_MASK BIT(5)
|
||||
|
||||
#endif /* __LINUX_EXTCON_SM5502_H */
|
||||
@@ -127,6 +127,9 @@ struct arizona_pdata {
|
||||
/** Internal pull on GPIO5 is disabled when used for jack detection */
|
||||
bool jd_gpio5_nopull;
|
||||
|
||||
/** set to true if jackdet contact opens on insert */
|
||||
bool jd_invert;
|
||||
|
||||
/** Use the headphone detect circuit to identify the accessory */
|
||||
bool hpdet_acc_id;
|
||||
|
||||
|
||||
@@ -262,6 +262,41 @@ enum max77693_irq_source {
|
||||
MAX77693_IRQ_GROUP_NR,
|
||||
};
|
||||
|
||||
#define LED_IRQ_FLED2_OPEN BIT(0)
|
||||
#define LED_IRQ_FLED2_SHORT BIT(1)
|
||||
#define LED_IRQ_FLED1_OPEN BIT(2)
|
||||
#define LED_IRQ_FLED1_SHORT BIT(3)
|
||||
#define LED_IRQ_MAX_FLASH BIT(4)
|
||||
|
||||
#define TOPSYS_IRQ_T120C_INT BIT(0)
|
||||
#define TOPSYS_IRQ_T140C_INT BIT(1)
|
||||
#define TOPSYS_IRQ_LOWSYS_INT BIT(3)
|
||||
|
||||
#define CHG_IRQ_BYP_I BIT(0)
|
||||
#define CHG_IRQ_THM_I BIT(2)
|
||||
#define CHG_IRQ_BAT_I BIT(3)
|
||||
#define CHG_IRQ_CHG_I BIT(4)
|
||||
#define CHG_IRQ_CHGIN_I BIT(6)
|
||||
|
||||
#define MUIC_IRQ_INT1_ADC BIT(0)
|
||||
#define MUIC_IRQ_INT1_ADC_LOW BIT(1)
|
||||
#define MUIC_IRQ_INT1_ADC_ERR BIT(2)
|
||||
#define MUIC_IRQ_INT1_ADC1K BIT(3)
|
||||
|
||||
#define MUIC_IRQ_INT2_CHGTYP BIT(0)
|
||||
#define MUIC_IRQ_INT2_CHGDETREUN BIT(1)
|
||||
#define MUIC_IRQ_INT2_DCDTMR BIT(2)
|
||||
#define MUIC_IRQ_INT2_DXOVP BIT(3)
|
||||
#define MUIC_IRQ_INT2_VBVOLT BIT(4)
|
||||
#define MUIC_IRQ_INT2_VIDRM BIT(5)
|
||||
|
||||
#define MUIC_IRQ_INT3_EOC BIT(0)
|
||||
#define MUIC_IRQ_INT3_CGMBC BIT(1)
|
||||
#define MUIC_IRQ_INT3_OVP BIT(2)
|
||||
#define MUIC_IRQ_INT3_MBCCHG_ERR BIT(3)
|
||||
#define MUIC_IRQ_INT3_CHG_ENABLED BIT(4)
|
||||
#define MUIC_IRQ_INT3_BAT_DET BIT(5)
|
||||
|
||||
enum max77693_irq {
|
||||
/* PMIC - FLASH */
|
||||
MAX77693_LED_IRQ_FLED2_OPEN,
|
||||
@@ -282,6 +317,10 @@ enum max77693_irq {
|
||||
MAX77693_CHG_IRQ_CHG_I,
|
||||
MAX77693_CHG_IRQ_CHGIN_I,
|
||||
|
||||
MAX77693_IRQ_NR,
|
||||
};
|
||||
|
||||
enum max77693_irq_muic {
|
||||
/* MUIC INT1 */
|
||||
MAX77693_MUIC_IRQ_INT1_ADC,
|
||||
MAX77693_MUIC_IRQ_INT1_ADC_LOW,
|
||||
@@ -304,7 +343,7 @@ enum max77693_irq {
|
||||
MAX77693_MUIC_IRQ_INT3_CHG_ENABLED,
|
||||
MAX77693_MUIC_IRQ_INT3_BAT_DET,
|
||||
|
||||
MAX77693_IRQ_NR,
|
||||
MAX77693_MUIC_IRQ_NR,
|
||||
};
|
||||
|
||||
struct max77693_dev {
|
||||
@@ -319,7 +358,10 @@ struct max77693_dev {
|
||||
struct regmap *regmap_muic;
|
||||
struct regmap *regmap_haptic;
|
||||
|
||||
struct irq_domain *irq_domain;
|
||||
struct regmap_irq_chip_data *irq_data_led;
|
||||
struct regmap_irq_chip_data *irq_data_topsys;
|
||||
struct regmap_irq_chip_data *irq_data_charger;
|
||||
struct regmap_irq_chip_data *irq_data_muic;
|
||||
|
||||
int irq;
|
||||
int irq_gpio;
|
||||
@@ -332,14 +374,6 @@ enum max77693_types {
|
||||
TYPE_MAX77693,
|
||||
};
|
||||
|
||||
extern int max77693_read_reg(struct regmap *map, u8 reg, u8 *dest);
|
||||
extern int max77693_bulk_read(struct regmap *map, u8 reg, int count,
|
||||
u8 *buf);
|
||||
extern int max77693_write_reg(struct regmap *map, u8 reg, u8 value);
|
||||
extern int max77693_bulk_write(struct regmap *map, u8 reg, int count,
|
||||
u8 *buf);
|
||||
extern int max77693_update_reg(struct regmap *map, u8 reg, u8 val, u8 mask);
|
||||
|
||||
extern int max77693_irq_init(struct max77693_dev *max77686);
|
||||
extern void max77693_irq_exit(struct max77693_dev *max77686);
|
||||
extern int max77693_irq_resume(struct max77693_dev *max77686);
|
||||
|
||||
@@ -0,0 +1,110 @@
|
||||
/*
|
||||
* Intel MIC Platform Software Stack (MPSS)
|
||||
*
|
||||
* Copyright(c) 2014 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, version 2, as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
* Intel MIC Bus driver.
|
||||
*
|
||||
* This implementation is very similar to the the virtio bus driver
|
||||
* implementation @ include/linux/virtio.h.
|
||||
*/
|
||||
#ifndef _MIC_BUS_H_
|
||||
#define _MIC_BUS_H_
|
||||
/*
|
||||
* Everything a mbus driver needs to work with any particular mbus
|
||||
* implementation.
|
||||
*/
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
|
||||
struct mbus_device_id {
|
||||
__u32 device;
|
||||
__u32 vendor;
|
||||
};
|
||||
|
||||
#define MBUS_DEV_DMA_HOST 2
|
||||
#define MBUS_DEV_DMA_MIC 3
|
||||
#define MBUS_DEV_ANY_ID 0xffffffff
|
||||
|
||||
/**
|
||||
* mbus_device - representation of a device using mbus
|
||||
* @mmio_va: virtual address of mmio space
|
||||
* @hw_ops: the hardware ops supported by this device.
|
||||
* @id: the device type identification (used to match it with a driver).
|
||||
* @dev: underlying device.
|
||||
* be used to communicate with.
|
||||
* @index: unique position on the mbus bus
|
||||
*/
|
||||
struct mbus_device {
|
||||
void __iomem *mmio_va;
|
||||
struct mbus_hw_ops *hw_ops;
|
||||
struct mbus_device_id id;
|
||||
struct device dev;
|
||||
int index;
|
||||
};
|
||||
|
||||
/**
|
||||
* mbus_driver - operations for a mbus I/O driver
|
||||
* @driver: underlying device driver (populate name and owner).
|
||||
* @id_table: the ids serviced by this driver.
|
||||
* @probe: the function to call when a device is found. Returns 0 or -errno.
|
||||
* @remove: the function to call when a device is removed.
|
||||
*/
|
||||
struct mbus_driver {
|
||||
struct device_driver driver;
|
||||
const struct mbus_device_id *id_table;
|
||||
int (*probe)(struct mbus_device *dev);
|
||||
void (*scan)(struct mbus_device *dev);
|
||||
void (*remove)(struct mbus_device *dev);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct mic_irq - opaque pointer used as cookie
|
||||
*/
|
||||
struct mic_irq;
|
||||
|
||||
/**
|
||||
* mbus_hw_ops - Hardware operations for accessing a MIC device on the MIC bus.
|
||||
*/
|
||||
struct mbus_hw_ops {
|
||||
struct mic_irq* (*request_threaded_irq)(struct mbus_device *mbdev,
|
||||
irq_handler_t handler,
|
||||
irq_handler_t thread_fn,
|
||||
const char *name, void *data,
|
||||
int intr_src);
|
||||
void (*free_irq)(struct mbus_device *mbdev,
|
||||
struct mic_irq *cookie, void *data);
|
||||
void (*ack_interrupt)(struct mbus_device *mbdev, int num);
|
||||
};
|
||||
|
||||
struct mbus_device *
|
||||
mbus_register_device(struct device *pdev, int id, struct dma_map_ops *dma_ops,
|
||||
struct mbus_hw_ops *hw_ops, void __iomem *mmio_va);
|
||||
void mbus_unregister_device(struct mbus_device *mbdev);
|
||||
|
||||
int mbus_register_driver(struct mbus_driver *drv);
|
||||
void mbus_unregister_driver(struct mbus_driver *drv);
|
||||
|
||||
static inline struct mbus_device *dev_to_mbus(struct device *_dev)
|
||||
{
|
||||
return container_of(_dev, struct mbus_device, dev);
|
||||
}
|
||||
|
||||
static inline struct mbus_driver *drv_to_mbus(struct device_driver *drv)
|
||||
{
|
||||
return container_of(drv, struct mbus_driver, driver);
|
||||
}
|
||||
|
||||
#endif /* _MIC_BUS_H */
|
||||
+11
-1
@@ -1477,8 +1477,9 @@ enum pci_fixup_pass {
|
||||
pci_fixup_final, /* Final phase of device fixups */
|
||||
pci_fixup_enable, /* pci_enable_device() time */
|
||||
pci_fixup_resume, /* pci_device_resume() */
|
||||
pci_fixup_suspend, /* pci_device_suspend */
|
||||
pci_fixup_suspend, /* pci_device_suspend() */
|
||||
pci_fixup_resume_early, /* pci_device_resume_early() */
|
||||
pci_fixup_suspend_late, /* pci_device_suspend_late() */
|
||||
};
|
||||
|
||||
/* Anonymous variables would be nice... */
|
||||
@@ -1519,6 +1520,11 @@ enum pci_fixup_pass {
|
||||
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
|
||||
suspend##hook, vendor, device, class, \
|
||||
class_shift, hook)
|
||||
#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
|
||||
class_shift, hook) \
|
||||
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
|
||||
suspend_late##hook, vendor, device, \
|
||||
class, class_shift, hook)
|
||||
|
||||
#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
|
||||
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
|
||||
@@ -1544,6 +1550,10 @@ enum pci_fixup_pass {
|
||||
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
|
||||
suspend##hook, vendor, device, \
|
||||
PCI_ANY_ID, 0, hook)
|
||||
#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
|
||||
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
|
||||
suspend_late##hook, vendor, device, \
|
||||
PCI_ANY_ID, 0, hook)
|
||||
|
||||
#ifdef CONFIG_PCI_QUIRKS
|
||||
void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
|
||||
|
||||
@@ -328,6 +328,7 @@ enum genwqe_card_state {
|
||||
GENWQE_CARD_UNUSED = 0,
|
||||
GENWQE_CARD_USED = 1,
|
||||
GENWQE_CARD_FATAL_ERROR = 2,
|
||||
GENWQE_CARD_RELOAD_BITSTREAM = 3,
|
||||
GENWQE_CARD_STATE_MAX,
|
||||
};
|
||||
|
||||
|
||||
@@ -34,7 +34,8 @@
|
||||
#define I8K_FAN_OFF 0
|
||||
#define I8K_FAN_LOW 1
|
||||
#define I8K_FAN_HIGH 2
|
||||
#define I8K_FAN_MAX I8K_FAN_HIGH
|
||||
#define I8K_FAN_TURBO 3
|
||||
#define I8K_FAN_MAX I8K_FAN_TURBO
|
||||
|
||||
#define I8K_VOL_UP 1
|
||||
#define I8K_VOL_DOWN 2
|
||||
|
||||
Reference in New Issue
Block a user