Merge tag 'vfio-v5.13-rc1' of git://github.com/awilliam/linux-vfio
Pull VFIO updates from Alex Williamson: - Embed struct vfio_device into vfio driver structures (Jason Gunthorpe) - Make vfio_mdev type safe (Jason Gunthorpe) - Remove vfio-pci NVLink2 extensions for POWER9 (Christoph Hellwig) - Update vfio-pci IGD extensions for OpRegion 2.1+ (Fred Gao) - Various spelling/blank line fixes (Zhen Lei, Zhou Wang, Bhaskar Chowdhury) - Simplify unpin_pages error handling (Shenming Lu) - Fix i915 mdev Kconfig dependency (Arnd Bergmann) - Remove unused structure member (Keqian Zhu) * tag 'vfio-v5.13-rc1' of git://github.com/awilliam/linux-vfio: (43 commits) vfio/gvt: fix DRM_I915_GVT dependency on VFIO_MDEV vfio/iommu_type1: Remove unused pinned_page_dirty_scope in vfio_iommu vfio/mdev: Correct the function signatures for the mdev_type_attributes vfio/mdev: Remove kobj from mdev_parent_ops->create() vfio/gvt: Use mdev_get_type_group_id() vfio/gvt: Make DRM_I915_GVT depend on VFIO_MDEV vfio/mbochs: Use mdev_get_type_group_id() vfio/mdpy: Use mdev_get_type_group_id() vfio/mtty: Use mdev_get_type_group_id() vfio/mdev: Add mdev/mtype_get_type_group_id() vfio/mdev: Remove duplicate storage of parent in mdev_device vfio/mdev: Add missing error handling to dev_set_name() vfio/mdev: Reorganize mdev_device_create() vfio/mdev: Add missing reference counting to mdev_type vfio/mdev: Expose mdev_get/put_parent to mdev_private.h vfio/mdev: Use struct mdev_type in struct mdev_device vfio/mdev: Simplify driver registration vfio/mdev: Add missing typesafety around mdev_device vfio/mdev: Do not allow a mdev_type to have a NULL parent pointer vfio/mdev: Fix missing static's on MDEV_TYPE_ATTR's ...
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@@ -333,17 +333,10 @@ struct vfio_region_info_cap_type {
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#define VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG (3)
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/* 10de vendor PCI sub-types */
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/*
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* NVIDIA GPU NVlink2 RAM is coherent RAM mapped onto the host address space.
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*/
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#define VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM (1)
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/* subtype 1 was VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM, don't use */
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/* 1014 vendor PCI sub-types */
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/*
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* IBM NPU NVlink2 ATSD (Address Translation Shootdown) register of NPU
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* to do TLB invalidation on a GPU.
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*/
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#define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD (1)
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/* subtype 1 was VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD, don't use */
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/* sub-types for VFIO_REGION_TYPE_GFX */
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#define VFIO_REGION_SUBTYPE_GFX_EDID (1)
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@@ -637,32 +630,9 @@ struct vfio_device_migration_info {
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*/
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#define VFIO_REGION_INFO_CAP_MSIX_MAPPABLE 3
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/*
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* Capability with compressed real address (aka SSA - small system address)
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* where GPU RAM is mapped on a system bus. Used by a GPU for DMA routing
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* and by the userspace to associate a NVLink bridge with a GPU.
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*/
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#define VFIO_REGION_INFO_CAP_NVLINK2_SSATGT 4
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/* subtype 4 was VFIO_REGION_INFO_CAP_NVLINK2_SSATGT, don't use */
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struct vfio_region_info_cap_nvlink2_ssatgt {
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struct vfio_info_cap_header header;
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__u64 tgt;
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};
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/*
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* Capability with an NVLink link speed. The value is read by
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* the NVlink2 bridge driver from the bridge's "ibm,nvlink-speed"
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* property in the device tree. The value is fixed in the hardware
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* and failing to provide the correct value results in the link
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* not working with no indication from the driver why.
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*/
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#define VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD 5
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struct vfio_region_info_cap_nvlink2_lnkspd {
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struct vfio_info_cap_header header;
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__u32 link_speed;
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__u32 __pad;
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};
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/* subtype 5 was VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD, don't use */
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/**
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* VFIO_DEVICE_GET_IRQ_INFO - _IOWR(VFIO_TYPE, VFIO_BASE + 9,
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