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Linux-2.6.12-rc2

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Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!
This commit is contained in:
Linus Torvalds
2005-04-16 15:20:36 -07:00
commit 1da177e4c3
17291 changed files with 6718755 additions and 0 deletions
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include/asm-mips/sn/addrs.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 1999, 2000 by Ralf Baechle
*/
#ifndef _ASM_SN_ADDRS_H
#define _ASM_SN_ADDRS_H
#include <linux/config.h>
#ifndef __ASSEMBLY__
#include <linux/types.h>
#endif /* !__ASSEMBLY__ */
#include <asm/addrspace.h>
#include <asm/sn/kldir.h>
#if defined(CONFIG_SGI_IP27)
#include <asm/sn/sn0/addrs.h>
#elif defined(CONFIG_SGI_IP35)
#include <asm/sn/sn1/addrs.h>
#endif
#ifndef __ASSEMBLY__
#if defined(CONFIG_SGI_IO) /* FIXME */
#define PS_UINT_CAST (__psunsigned_t)
#define UINT64_CAST (__uint64_t)
#else /* CONFIG_SGI_IO */
#define PS_UINT_CAST (unsigned long)
#define UINT64_CAST (unsigned long)
#endif /* CONFIG_SGI_IO */
#define HUBREG_CAST (volatile hubreg_t *)
#else /* __ASSEMBLY__ */
#define PS_UINT_CAST
#define UINT64_CAST
#define HUBREG_CAST
#endif /* __ASSEMBLY__ */
#define NASID_GET_META(_n) ((_n) >> NASID_LOCAL_BITS)
#ifdef CONFIG_SGI_IP27
#define NASID_GET_LOCAL(_n) ((_n) & 0xf)
#endif
#define NASID_MAKE(_m, _l) (((_m) << NASID_LOCAL_BITS) | (_l))
#define NODE_ADDRSPACE_MASK (NODE_ADDRSPACE_SIZE - 1)
#define TO_NODE_ADDRSPACE(_pa) (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK)
#define CHANGE_ADDR_NASID(_pa, _nasid) \
((UINT64_CAST (_pa) & ~NASID_MASK) | \
(UINT64_CAST(_nasid) << NASID_SHFT))
/*
* The following macros are used to index to the beginning of a specific
* node's address space.
*/
#define NODE_OFFSET(_n) (UINT64_CAST (_n) << NODE_SIZE_BITS)
#define NODE_CAC_BASE(_n) (CAC_BASE + NODE_OFFSET(_n))
#define NODE_HSPEC_BASE(_n) (HSPEC_BASE + NODE_OFFSET(_n))
#define NODE_IO_BASE(_n) (IO_BASE + NODE_OFFSET(_n))
#define NODE_MSPEC_BASE(_n) (MSPEC_BASE + NODE_OFFSET(_n))
#define NODE_UNCAC_BASE(_n) (UNCAC_BASE + NODE_OFFSET(_n))
#define TO_NODE(_n, _x) (NODE_OFFSET(_n) | ((_x) ))
#define TO_NODE_CAC(_n, _x) (NODE_CAC_BASE(_n) | ((_x) & TO_PHYS_MASK))
#define TO_NODE_UNCAC(_n, _x) (NODE_UNCAC_BASE(_n) | ((_x) & TO_PHYS_MASK))
#define TO_NODE_MSPEC(_n, _x) (NODE_MSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK))
#define TO_NODE_HSPEC(_n, _x) (NODE_HSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK))
#define RAW_NODE_SWIN_BASE(nasid, widget) \
(NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
#define WIDGETID_GET(addr) ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff))
/*
* The following definitions pertain to the IO special address
* space. They define the location of the big and little windows
* of any given node.
*/
#define SWIN_SIZE_BITS 24
#define SWIN_SIZE (UINT64_CAST 1 << 24)
#define SWIN_SIZEMASK (SWIN_SIZE - 1)
#define SWIN_WIDGET_MASK 0xF
/*
* Convert smallwindow address to xtalk address.
*
* 'addr' can be physical or virtual address, but will be converted
* to Xtalk address in the range 0 -> SWINZ_SIZEMASK
*/
#define SWIN_WIDGETADDR(addr) ((addr) & SWIN_SIZEMASK)
#define SWIN_WIDGETNUM(addr) (((addr) >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
/*
* Verify if addr belongs to small window address on node with "nasid"
*
*
* NOTE: "addr" is expected to be XKPHYS address, and NOT physical
* address
*
*
*/
#define NODE_SWIN_ADDR(nasid, addr) \
(((addr) >= NODE_SWIN_BASE(nasid, 0)) && \
((addr) < (NODE_SWIN_BASE(nasid, HUB_NUM_WIDGET) + SWIN_SIZE)\
))
/*
* The following define the major position-independent aliases used
* in SN.
* UALIAS -- 256MB in size, reads in the UALIAS result in
* uncached references to the memory of the reader's node.
* CPU_UALIAS -- 128kb in size, the bottom part of UALIAS is flipped
* depending on which CPU does the access to provide
* all CPUs with unique uncached memory at low addresses.
* LBOOT -- 256MB in size, reads in the LBOOT area result in
* uncached references to the local hub's boot prom and
* other directory-bus connected devices.
* IALIAS -- 8MB in size, reads in the IALIAS result in uncached
* references to the local hub's registers.
*/
#define UALIAS_BASE HSPEC_BASE
#define UALIAS_SIZE 0x10000000 /* 256 Megabytes */
#define UALIAS_LIMIT (UALIAS_BASE + UALIAS_SIZE)
/*
* The bottom of ualias space is flipped depending on whether you're
* processor 0 or 1 within a node.
*/
#ifdef CONFIG_SGI_IP27
#define UALIAS_FLIP_BASE UALIAS_BASE
#define UALIAS_FLIP_SIZE 0x20000
#define UALIAS_FLIP_BIT 0x10000
#define UALIAS_FLIP_ADDR(_x) (cputoslice(smp_processor_id()) ? \
(_x) ^ UALIAS_FLIP_BIT : (_x))
#define LBOOT_BASE (HSPEC_BASE + 0x10000000)
#define LBOOT_SIZE 0x10000000
#define LBOOT_LIMIT (LBOOT_BASE + LBOOT_SIZE)
#define LBOOT_STRIDE 0 /* IP27 has only one CPU PROM */
#endif
#define HUB_REGISTER_WIDGET 1
#define IALIAS_BASE NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET)
#define IALIAS_SIZE 0x800000 /* 8 Megabytes */
#define IS_IALIAS(_a) (((_a) >= IALIAS_BASE) && \
((_a) < (IALIAS_BASE + IALIAS_SIZE)))
/*
* Macro for referring to Hub's RBOOT space
*/
#ifdef CONFIG_SGI_IP27
#define RBOOT_SIZE 0x10000000 /* 256 Megabytes */
#define NODE_RBOOT_BASE(_n) (NODE_HSPEC_BASE(_n) + 0x30000000)
#define NODE_RBOOT_LIMIT(_n) (NODE_RBOOT_BASE(_n) + RBOOT_SIZE)
#endif
/*
* Macros for referring the Hub's back door space
*
* These macros correctly process addresses in any node's space.
* WARNING: They won't work in assembler.
*
* BDDIR_ENTRY_LO returns the address of the low double-word of the dir
* entry corresponding to a physical (Cac or Uncac) address.
* BDDIR_ENTRY_HI returns the address of the high double-word of the entry.
* BDPRT_ENTRY returns the address of the double-word protection entry
* corresponding to the page containing the physical address.
* BDPRT_ENTRY_S Stores the value into the protection entry.
* BDPRT_ENTRY_L Load the value from the protection entry.
* BDECC_ENTRY returns the address of the ECC byte corresponding to a
* double-word at a specified physical address.
* BDECC_ENTRY_H returns the address of the two ECC bytes corresponding to a
* quad-word at a specified physical address.
*/
#define NODE_BDOOR_BASE(_n) (NODE_HSPEC_BASE(_n) + (NODE_ADDRSPACE_SIZE/2))
#define NODE_BDECC_BASE(_n) (NODE_BDOOR_BASE(_n))
#define NODE_BDDIR_BASE(_n) (NODE_BDOOR_BASE(_n) + (NODE_ADDRSPACE_SIZE/4))
#ifdef CONFIG_SGI_IP27
#define BDDIR_ENTRY_LO(_pa) ((HSPEC_BASE + \
NODE_ADDRSPACE_SIZE * 3 / 4 + \
0x200) | \
UINT64_CAST (_pa) & NASID_MASK | \
UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \
UINT64_CAST (_pa) >> 3 & 0x1f << 4)
#define BDDIR_ENTRY_HI(_pa) ((HSPEC_BASE + \
NODE_ADDRSPACE_SIZE * 3 / 4 + \
0x208) | \
UINT64_CAST (_pa) & NASID_MASK | \
UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \
UINT64_CAST (_pa) >> 3 & 0x1f << 4)
#define BDPRT_ENTRY(_pa, _rgn) ((HSPEC_BASE + \
NODE_ADDRSPACE_SIZE * 3 / 4) | \
UINT64_CAST (_pa) & NASID_MASK | \
UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \
(_rgn) << 3)
#define BDPRT_ENTRY_ADDR(_pa,_rgn) (BDPRT_ENTRY((_pa),(_rgn)))
#define BDPRT_ENTRY_S(_pa,_rgn,_val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))=(_val))
#define BDPRT_ENTRY_L(_pa,_rgn) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn)))
#define BDECC_ENTRY(_pa) ((HSPEC_BASE + \
NODE_ADDRSPACE_SIZE / 2) | \
UINT64_CAST (_pa) & NASID_MASK | \
UINT64_CAST (_pa) >> 2 & BDECC_UPPER_MASK | \
UINT64_CAST (_pa) >> 3 & 3)
/*
* Macro to convert a back door directory or protection address into the
* raw physical address of the associated cache line or protection page.
*/
#define BDADDR_IS_DIR(_ba) ((UINT64_CAST (_ba) & 0x200) != 0)
#define BDADDR_IS_PRT(_ba) ((UINT64_CAST (_ba) & 0x200) == 0)
#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
(UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2 | \
(UINT64_CAST (_ba) & 0x1f << 4) << 3)
#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
(UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2)
#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
(UINT64_CAST (_ba) & BDECC_UPPER_MASK)<<2 | \
(UINT64_CAST (_ba) & 3) << 3)
#endif /* CONFIG_SGI_IP27 */
/*
* The following macros produce the correct base virtual address for
* the hub registers. The LOCAL_HUB_* macros produce the appropriate
* address for the local registers. The REMOTE_HUB_* macro produce
* the address for the specified hub's registers. The intent is
* that the appropriate PI, MD, NI, or II register would be substituted
* for _x.
*/
#ifdef _STANDALONE
/* DO NOT USE THESE DIRECTLY IN THE KERNEL. SEE BELOW. */
#define LOCAL_HUB(_x) (HUBREG_CAST (IALIAS_BASE + (_x)))
#define REMOTE_HUB(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \
0x800000 + (_x)))
#endif /* _STANDALONE */
/*
* WARNING:
* When certain Hub chip workaround are defined, it's not sufficient
* to dereference the *_HUB_ADDR() macros. You should instead use
* HUB_L() and HUB_S() if you must deal with pointers to hub registers.
* Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
* They're always safe.
*/
#define LOCAL_HUB_ADDR(_x) (HUBREG_CAST (IALIAS_BASE + (_x)))
#define REMOTE_HUB_ADDR(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \
0x800000 + (_x)))
#ifdef CONFIG_SGI_IP27
#define REMOTE_HUB_PI_ADDR(_n, _sn, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \
0x800000 + (_x)))
#endif /* CONFIG_SGI_IP27 */
#ifndef __ASSEMBLY__
#define HUB_L(_a) *(_a)
#define HUB_S(_a, _d) *(_a) = (_d)
#define LOCAL_HUB_L(_r) HUB_L(LOCAL_HUB_ADDR(_r))
#define LOCAL_HUB_S(_r, _d) HUB_S(LOCAL_HUB_ADDR(_r), (_d))
#define REMOTE_HUB_L(_n, _r) HUB_L(REMOTE_HUB_ADDR((_n), (_r)))
#define REMOTE_HUB_S(_n, _r, _d) HUB_S(REMOTE_HUB_ADDR((_n), (_r)), (_d))
#define REMOTE_HUB_PI_L(_n, _sn, _r) HUB_L(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)))
#define REMOTE_HUB_PI_S(_n, _sn, _r, _d) HUB_S(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)), (_d))
#endif /* !__ASSEMBLY__ */
/*
* The following macros are used to get to a hub/bridge register, given
* the base of the register space.
*/
#define HUB_REG_PTR(_base, _off) \
(HUBREG_CAST ((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
#define HUB_REG_PTR_L(_base, _off) \
HUB_L(HUB_REG_PTR((_base), (_off)))
#define HUB_REG_PTR_S(_base, _off, _data) \
HUB_S(HUB_REG_PTR((_base), (_off)), (_data))
/*
* Software structure locations -- permanently fixed
* See diagram in kldir.h
*/
#define PHYS_RAMBASE 0x0
#define K0_RAMBASE PHYS_TO_K0(PHYS_RAMBASE)
#define EX_HANDLER_OFFSET(slice) ((slice) << 16)
#define EX_HANDLER_ADDR(nasid, slice) \
PHYS_TO_K0(NODE_OFFSET(nasid) | EX_HANDLER_OFFSET(slice))
#define EX_HANDLER_SIZE 0x0400
#define EX_FRAME_OFFSET(slice) ((slice) << 16 | 0x400)
#define EX_FRAME_ADDR(nasid, slice) \
PHYS_TO_K0(NODE_OFFSET(nasid) | EX_FRAME_OFFSET(slice))
#define EX_FRAME_SIZE 0x0c00
#define ARCS_SPB_OFFSET 0x1000
#define ARCS_SPB_ADDR(nasid) \
PHYS_TO_K0(NODE_OFFSET(nasid) | ARCS_SPB_OFFSET)
#define ARCS_SPB_SIZE 0x0400
#ifdef _STANDALONE
#define ARCS_TVECTOR_OFFSET 0x2800
#define ARCS_PVECTOR_OFFSET 0x2c00
/*
* These addresses are used by the master CPU to install the transfer
* and private vectors. All others use the SPB to find them.
*/
#define TVADDR (NODE_CAC_BASE(get_nasid()) + ARCS_TVECTOR_OFFSET)
#define PVADDR (NODE_CAC_BASE(get_nasid()) + ARCS_PVECTOR_OFFSET)
#endif /* _STANDALONE */
#define KLDIR_OFFSET 0x2000
#define KLDIR_ADDR(nasid) \
TO_NODE_UNCAC((nasid), KLDIR_OFFSET)
#define KLDIR_SIZE 0x0400
/*
* Software structure locations -- indirected through KLDIR
* See diagram in kldir.h
*
* Important: All low memory structures must only be accessed
* uncached, except for the symmon stacks.
*/
#define KLI_LAUNCH 0 /* Dir. entries */
#define KLI_KLCONFIG 1
#define KLI_NMI 2
#define KLI_GDA 3
#define KLI_FREEMEM 4
#define KLI_SYMMON_STK 5
#define KLI_PI_ERROR 6
#define KLI_KERN_VARS 7
#define KLI_KERN_XP 8
#define KLI_KERN_PARTID 9
#ifndef __ASSEMBLY__
#define KLD_BASE(nasid) ((kldir_ent_t *) KLDIR_ADDR(nasid))
#define KLD_LAUNCH(nasid) (KLD_BASE(nasid) + KLI_LAUNCH)
#define KLD_NMI(nasid) (KLD_BASE(nasid) + KLI_NMI)
#define KLD_KLCONFIG(nasid) (KLD_BASE(nasid) + KLI_KLCONFIG)
#define KLD_PI_ERROR(nasid) (KLD_BASE(nasid) + KLI_PI_ERROR)
#define KLD_GDA(nasid) (KLD_BASE(nasid) + KLI_GDA)
#define KLD_SYMMON_STK(nasid) (KLD_BASE(nasid) + KLI_SYMMON_STK)
#define KLD_FREEMEM(nasid) (KLD_BASE(nasid) + KLI_FREEMEM)
#define KLD_KERN_VARS(nasid) (KLD_BASE(nasid) + KLI_KERN_VARS)
#define KLD_KERN_XP(nasid) (KLD_BASE(nasid) + KLI_KERN_XP)
#define KLD_KERN_PARTID(nasid) (KLD_BASE(nasid) + KLI_KERN_PARTID)
#define LAUNCH_OFFSET(nasid, slice) \
(KLD_LAUNCH(nasid)->offset + \
KLD_LAUNCH(nasid)->stride * (slice))
#define LAUNCH_ADDR(nasid, slice) \
TO_NODE_UNCAC((nasid), LAUNCH_OFFSET(nasid, slice))
#define LAUNCH_SIZE(nasid) KLD_LAUNCH(nasid)->size
#define NMI_OFFSET(nasid, slice) \
(KLD_NMI(nasid)->offset + \
KLD_NMI(nasid)->stride * (slice))
#define NMI_ADDR(nasid, slice) \
TO_NODE_UNCAC((nasid), NMI_OFFSET(nasid, slice))
#define NMI_SIZE(nasid) KLD_NMI(nasid)->size
#define KLCONFIG_OFFSET(nasid) KLD_KLCONFIG(nasid)->offset
#define KLCONFIG_ADDR(nasid) \
TO_NODE_UNCAC((nasid), KLCONFIG_OFFSET(nasid))
#define KLCONFIG_SIZE(nasid) KLD_KLCONFIG(nasid)->size
#define GDA_ADDR(nasid) KLD_GDA(nasid)->pointer
#define GDA_SIZE(nasid) KLD_GDA(nasid)->size
#define SYMMON_STK_OFFSET(nasid, slice) \
(KLD_SYMMON_STK(nasid)->offset + \
KLD_SYMMON_STK(nasid)->stride * (slice))
#define SYMMON_STK_STRIDE(nasid) KLD_SYMMON_STK(nasid)->stride
#define SYMMON_STK_ADDR(nasid, slice) \
TO_NODE_CAC((nasid), SYMMON_STK_OFFSET(nasid, slice))
#define SYMMON_STK_SIZE(nasid) KLD_SYMMON_STK(nasid)->stride
#define SYMMON_STK_END(nasid) (SYMMON_STK_ADDR(nasid, 0) + KLD_SYMMON_STK(nasid)->size)
/* loading symmon 4k below UNIX. the arcs loader needs the topaddr for a
* relocatable program
*/
#define UNIX_DEBUG_LOADADDR 0x300000
#define SYMMON_LOADADDR(nasid) \
TO_NODE(nasid, PHYS_TO_K0(UNIX_DEBUG_LOADADDR - 0x1000))
#define FREEMEM_OFFSET(nasid) KLD_FREEMEM(nasid)->offset
#define FREEMEM_ADDR(nasid) SYMMON_STK_END(nasid)
/*
* XXX
* Fix this. FREEMEM_ADDR should be aware of if symmon is loaded.
* Also, it should take into account what prom thinks to be a safe
* address
PHYS_TO_K0(NODE_OFFSET(nasid) + FREEMEM_OFFSET(nasid))
*/
#define FREEMEM_SIZE(nasid) KLD_FREEMEM(nasid)->size
#define PI_ERROR_OFFSET(nasid) KLD_PI_ERROR(nasid)->offset
#define PI_ERROR_ADDR(nasid) \
TO_NODE_UNCAC((nasid), PI_ERROR_OFFSET(nasid))
#define PI_ERROR_SIZE(nasid) KLD_PI_ERROR(nasid)->size
#define NODE_OFFSET_TO_K0(_nasid, _off) \
PHYS_TO_K0((NODE_OFFSET(_nasid) + (_off)) | CAC_BASE)
#define NODE_OFFSET_TO_K1(_nasid, _off) \
TO_UNCAC((NODE_OFFSET(_nasid) + (_off)) | UNCAC_BASE)
#define K0_TO_NODE_OFFSET(_k0addr) \
((__psunsigned_t)(_k0addr) & NODE_ADDRSPACE_MASK)
#define KERN_VARS_ADDR(nasid) KLD_KERN_VARS(nasid)->pointer
#define KERN_VARS_SIZE(nasid) KLD_KERN_VARS(nasid)->size
#define KERN_XP_ADDR(nasid) KLD_KERN_XP(nasid)->pointer
#define KERN_XP_SIZE(nasid) KLD_KERN_XP(nasid)->size
#define GPDA_ADDR(nasid) TO_NODE_CAC(nasid, GPDA_OFFSET)
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_SN_ADDRS_H */
include/asm-mips/sn/agent.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* This file has definitions for the hub and snac interfaces.
*
* Copyright (C) 1992 - 1997, 1999, 2000 Silcon Graphics, Inc.
* Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
*/
#ifndef _ASM_SGI_SN_AGENT_H
#define _ASM_SGI_SN_AGENT_H
#include <linux/config.h>
#include <linux/topology.h>
#include <asm/sn/addrs.h>
#include <asm/sn/arch.h>
#if defined(CONFIG_SGI_IP27)
#include <asm/sn/sn0/hub.h>
#elif defined(CONFIG_SGI_IP35)
#include <asm/sn/sn1/hub.h>
#endif /* !CONFIG_SGI_IP27 && !CONFIG_SGI_IP35 */
/*
* NIC register macros
*/
#if defined(CONFIG_SGI_IP27)
#define HUB_NIC_ADDR(_cpuid) \
REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cpu_to_node(_cpuid)), \
MD_MLAN_CTL)
#endif
#define SET_HUB_NIC(_my_cpuid, _val) \
(HUB_S(HUB_NIC_ADDR(_my_cpuid), (_val)))
#define SET_MY_HUB_NIC(_v) \
SET_HUB_NIC(cpuid(), (_v))
#define GET_HUB_NIC(_my_cpuid) \
(HUB_L(HUB_NIC_ADDR(_my_cpuid)))
#define GET_MY_HUB_NIC() \
GET_HUB_NIC(cpuid())
#endif /* _ASM_SGI_SN_AGENT_H */
include/asm-mips/sn/arch.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* SGI specific setup.
*
* Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
* Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
*/
#ifndef _ASM_SN_ARCH_H
#define _ASM_SN_ARCH_H
#include <linux/config.h>
#include <linux/types.h>
#include <asm/sn/types.h>
#ifdef CONFIG_SGI_IP27
#include <asm/sn/sn0/arch.h>
#endif
typedef u64 hubreg_t;
typedef u64 nic_t;
#define cputonasid(cpu) (cpu_data[(cpu)].p_nasid)
#define cputoslice(cpu) (cpu_data[(cpu)].p_slice)
#define makespnum(_nasid, _slice) \
(((_nasid) << CPUS_PER_NODE_SHFT) | (_slice))
#define INVALID_NASID (nasid_t)-1
#define INVALID_CNODEID (cnodeid_t)-1
#define INVALID_PNODEID (pnodeid_t)-1
#define INVALID_MODULE (moduleid_t)-1
#define INVALID_PARTID (partid_t)-1
extern nasid_t get_nasid(void);
extern cnodeid_t get_cpu_cnode(cpuid_t);
extern int get_cpu_slice(cpuid_t);
/*
* NO ONE should access these arrays directly. The only reason we refer to
* them here is to avoid the procedure call that would be required in the
* macros below. (Really want private data members here :-)
*/
extern cnodeid_t nasid_to_compact_node[MAX_NASIDS];
extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
/*
* These macros are used by various parts of the kernel to convert
* between the three different kinds of node numbering. At least some
* of them may change to procedure calls in the future, but the macros
* will continue to work. Don't use the arrays above directly.
*/
#define NASID_TO_REGION(nnode) \
((nnode) >> \
(is_fine_dirmode() ? NASID_TO_FINEREG_SHFT : NASID_TO_COARSEREG_SHFT))
extern cnodeid_t nasid_to_compact_node[MAX_NASIDS];
extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
extern cnodeid_t cpuid_to_compact_node[MAXCPUS];
#define NASID_TO_COMPACT_NODEID(nnode) (nasid_to_compact_node[nnode])
#define COMPACT_TO_NASID_NODEID(cnode) (compact_to_nasid_node[cnode])
#define CPUID_TO_COMPACT_NODEID(cpu) (cpuid_to_compact_node[(cpu)])
#endif /* _ASM_SN_ARCH_H */
include/asm-mips/sn/gda.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Derived from IRIX <sys/SN/gda.h>.
*
* Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
*
* gda.h -- Contains the data structure for the global data area,
* The GDA contains information communicated between the
* PROM, SYMMON, and the kernel.
*/
#ifndef _ASM_SN_GDA_H
#define _ASM_SN_GDA_H
#include <asm/sn/addrs.h>
#define GDA_MAGIC 0x58464552
/*
* GDA Version History
*
* Version # | Change
* -------------+-------------------------------------------------------
* 1 | Initial SN0 version
* 2 | Prom sets g_partid field to the partition number. 0 IS
* | a valid partition #.
*/
#define GDA_VERSION 2 /* Current GDA version # */
#define G_MAGICOFF 0
#define G_VERSIONOFF 4
#define G_PROMOPOFF 6
#define G_MASTEROFF 8
#define G_VDSOFF 12
#define G_HKDNORMOFF 16
#define G_HKDUTLBOFF 24
#define G_HKDXUTLBOFF 32
#define G_PARTIDOFF 40
#define G_TABLEOFF 128
#ifndef __ASSEMBLY__
typedef struct gda {
u32 g_magic; /* GDA magic number */
u16 g_version; /* Version of this structure */
u16 g_masterid; /* The NASID:CPUNUM of the master cpu */
u32 g_promop; /* Passes requests from the kernel to prom */
u32 g_vds; /* Store the virtual dipswitches here */
void **g_hooked_norm;/* ptr to pda loc for norm hndlr */
void **g_hooked_utlb;/* ptr to pda loc for utlb hndlr */
void **g_hooked_xtlb;/* ptr to pda loc for xtlb hndlr */
int g_partid; /* partition id */
int g_symmax; /* Max symbols in name table. */
void *g_dbstab; /* Address of idbg symbol table */
char *g_nametab; /* Address of idbg name table */
void *g_ktext_repmask;
/* Pointer to a mask of nodes with copies
* of the kernel. */
char g_padding[56]; /* pad out to 128 bytes */
nasid_t g_nasidtable[MAX_COMPACT_NODES]; /* NASID of each node,
* indexed by cnodeid.
*/
} gda_t;
#define GDA ((gda_t*) GDA_ADDR(get_nasid()))
#endif /* !__ASSEMBLY__ */
/*
* Define: PART_GDA_VERSION
* Purpose: Define the minimum version of the GDA required, lower
* revisions assume GDA is NOT set up, and read partition
* information from the board info.
*/
#define PART_GDA_VERSION 2
/*
* The following requests can be sent to the PROM during startup.
*/
#define PROMOP_MAGIC 0x0ead0000
#define PROMOP_MAGIC_MASK 0x0fff0000
#define PROMOP_BIST_SHIFT 11
#define PROMOP_BIST_MASK (0x3 << 11)
#define PROMOP_REG PI_ERR_STACK_ADDR_A
#define PROMOP_INVALID (PROMOP_MAGIC | 0x00)
#define PROMOP_HALT (PROMOP_MAGIC | 0x10)
#define PROMOP_POWERDOWN (PROMOP_MAGIC | 0x20)
#define PROMOP_RESTART (PROMOP_MAGIC | 0x30)
#define PROMOP_REBOOT (PROMOP_MAGIC | 0x40)
#define PROMOP_IMODE (PROMOP_MAGIC | 0x50)
#define PROMOP_CMD_MASK 0x00f0
#define PROMOP_OPTIONS_MASK 0xfff0
#define PROMOP_SKIP_DIAGS 0x0100 /* don't bother running diags */
#define PROMOP_SKIP_MEMINIT 0x0200 /* don't bother initing memory */
#define PROMOP_SKIP_DEVINIT 0x0400 /* don't bother initing devices */
#define PROMOP_BIST1 0x0800 /* keep track of which BIST ran */
#define PROMOP_BIST2 0x1000 /* keep track of which BIST ran */
#endif /* _ASM_SN_GDA_H */
include/asm-mips/sn/hub.h
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#ifndef __ASM_SN_HUB_H
#define __ASM_SN_HUB_H
#include <linux/types.h>
#include <linux/cpumask.h>
#include <asm/sn/types.h>
#include <asm/sn/io.h>
#include <asm/sn/klkernvars.h>
#include <asm/xtalk/xtalk.h>
/* ip27-hubio.c */
extern unsigned long hub_pio_map(cnodeid_t cnode, xwidgetnum_t widget,
unsigned long xtalk_addr, size_t size);
extern void hub_pio_init(cnodeid_t cnode);
#endif /* __ASM_SN_HUB_H */
include/asm-mips/sn/intr.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
*/
#ifndef __ASM_SN_INTR_H
#define __ASM_SN_INTR_H
/* Number of interrupt levels associated with each interrupt register. */
#define N_INTPEND_BITS 64
#define INT_PEND0_BASELVL 0
#define INT_PEND1_BASELVL 64
#define N_INTPENDJUNK_BITS 8
#define INTPENDJUNK_CLRBIT 0x80
/*
* Macros to manipulate the interrupt register on the calling hub chip.
*/
#define LOCAL_HUB_SEND_INTR(level) \
LOCAL_HUB_S(PI_INT_PEND_MOD, (0x100 | (level)))
#define REMOTE_HUB_SEND_INTR(hub, level) \
REMOTE_HUB_S((hub), PI_INT_PEND_MOD, (0x100 | (level)))
/*
* When clearing the interrupt, make sure this clear does make it
* to the hub. Otherwise we could end up losing interrupts.
* We do an uncached load of the int_pend0 register to ensure this.
*/
#define LOCAL_HUB_CLR_INTR(level) \
do { \
LOCAL_HUB_S(PI_INT_PEND_MOD, (level)); \
LOCAL_HUB_L(PI_INT_PEND0); \
} while (0);
#define REMOTE_HUB_CLR_INTR(hub, level) \
do { \
nasid_t __hub = (hub); \
\
REMOTE_HUB_S(__hub, PI_INT_PEND_MOD, (level)); \
REMOTE_HUB_L(__hub, PI_INT_PEND0); \
} while (0);
/*
* Hard-coded interrupt levels:
*/
/*
* L0 = SW1
* L1 = SW2
* L2 = INT_PEND0
* L3 = INT_PEND1
* L4 = RTC
* L5 = Profiling Timer
* L6 = Hub Errors
* L7 = Count/Compare (T5 counters)
*/
/*
* INT_PEND0 hard-coded bits.
*/
/*
* INT_PEND0 bits determined by hardware:
*/
#define RESERVED_INTR 0 /* What is this bit? */
#define GFX_INTR_A 1
#define GFX_INTR_B 2
#define PG_MIG_INTR 3
#define UART_INTR 4
#define CC_PEND_A 5
#define CC_PEND_B 6
/*
* INT_PEND0 used by the kernel for itself ...
*/
#define CPU_RESCHED_A_IRQ 7
#define CPU_RESCHED_B_IRQ 8
#define CPU_CALL_A_IRQ 9
#define CPU_CALL_B_IRQ 10
#define MSC_MESG_INTR 11
#define BASE_PCI_IRQ 12
/*
* INT_PEND0 again, bits determined by hardware / hardcoded:
*/
#define SDISK_INTR 63 /* SABLE name */
#define IP_PEND0_6_63 63 /* What is this bit? */
/*
* INT_PEND1 hard-coded bits:
*/
#define NI_BRDCAST_ERR_A 39
#define NI_BRDCAST_ERR_B 40
#define LLP_PFAIL_INTR_A 41 /* see ml/SN/SN0/sysctlr.c */
#define LLP_PFAIL_INTR_B 42
#define TLB_INTR_A 43 /* used for tlb flush random */
#define TLB_INTR_B 44
#define IP27_INTR_0 45 /* Reserved for PROM use */
#define IP27_INTR_1 46 /* do not use in Kernel */
#define IP27_INTR_2 47
#define IP27_INTR_3 48
#define IP27_INTR_4 49
#define IP27_INTR_5 50
#define IP27_INTR_6 51
#define IP27_INTR_7 52
#define BRIDGE_ERROR_INTR 53 /* Setup by PROM to catch */
/* Bridge Errors */
#define DEBUG_INTR_A 54
#define DEBUG_INTR_B 55 /* Used by symmon to stop all cpus */
#define IO_ERROR_INTR 57 /* Setup by PROM */
#define CLK_ERR_INTR 58
#define COR_ERR_INTR_A 59
#define COR_ERR_INTR_B 60
#define MD_COR_ERR_INTR 61
#define NI_ERROR_INTR 62
#define MSC_PANIC_INTR 63
#endif /* __ASM_SN_INTR_H */
include/asm-mips/sn/io.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000, 2003 Ralf Baechle
* Copyright (C) 2000 Silicon Graphics, Inc.
*/
#ifndef _ASM_SN_IO_H
#define _ASM_SN_IO_H
#include <linux/config.h>
#if defined (CONFIG_SGI_IP27)
#include <asm/sn/sn0/hubio.h>
#endif
#define IIO_ITTE_BASE 0x400160 /* base of translation table entries */
#define IIO_ITTE(bigwin) (IIO_ITTE_BASE + 8*(bigwin))
#define IIO_ITTE_OFFSET_BITS 5 /* size of offset field */
#define IIO_ITTE_OFFSET_MASK ((1<<IIO_ITTE_OFFSET_BITS)-1)
#define IIO_ITTE_OFFSET_SHIFT 0
#define IIO_ITTE_WIDGET_BITS 4 /* size of widget field */
#define IIO_ITTE_WIDGET_MASK ((1<<IIO_ITTE_WIDGET_BITS)-1)
#define IIO_ITTE_WIDGET_SHIFT 8
#define IIO_ITTE_IOSP 1 /* I/O Space bit */
#define IIO_ITTE_IOSP_MASK 1
#define IIO_ITTE_IOSP_SHIFT 12
#define HUB_PIO_MAP_TO_MEM 0
#define HUB_PIO_MAP_TO_IO 1
#define IIO_ITTE_INVALID_WIDGET 3 /* an invalid widget */
#define IIO_ITTE_PUT(nasid, bigwin, io_or_mem, widget, addr) \
REMOTE_HUB_S((nasid), IIO_ITTE(bigwin), \
(((((addr) >> BWIN_SIZE_BITS) & \
IIO_ITTE_OFFSET_MASK) << IIO_ITTE_OFFSET_SHIFT) | \
(io_or_mem << IIO_ITTE_IOSP_SHIFT) | \
(((widget) & IIO_ITTE_WIDGET_MASK) << IIO_ITTE_WIDGET_SHIFT)))
#define IIO_ITTE_DISABLE(nasid, bigwin) \
IIO_ITTE_PUT((nasid), HUB_PIO_MAP_TO_MEM, \
(bigwin), IIO_ITTE_INVALID_WIDGET, 0)
#define IIO_ITTE_GET(nasid, bigwin) REMOTE_HUB_ADDR((nasid), IIO_ITTE(bigwin))
/*
* Macro which takes the widget number, and returns the
* IO PRB address of that widget.
* value _x is expected to be a widget number in the range
* 0, 8 - 0xF
*/
#define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
(_x) : \
(_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
#endif /* _ASM_SN_IO_H */
include/asm-mips/sn/ioc3.h
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/*
* Copyright (C) 1999, 2000 Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
*/
#ifndef _IOC3_H
#define _IOC3_H
/* SUPERIO uart register map */
typedef volatile struct ioc3_uartregs {
union {
volatile u8 rbr; /* read only, DLAB == 0 */
volatile u8 thr; /* write only, DLAB == 0 */
volatile u8 dll; /* DLAB == 1 */
} u1;
union {
volatile u8 ier; /* DLAB == 0 */
volatile u8 dlm; /* DLAB == 1 */
} u2;
union {
volatile u8 iir; /* read only */
volatile u8 fcr; /* write only */
} u3;
volatile u8 iu_lcr;
volatile u8 iu_mcr;
volatile u8 iu_lsr;
volatile u8 iu_msr;
volatile u8 iu_scr;
} ioc3_uregs_t;
#define iu_rbr u1.rbr
#define iu_thr u1.thr
#define iu_dll u1.dll
#define iu_ier u2.ier
#define iu_dlm u2.dlm
#define iu_iir u3.iir
#define iu_fcr u3.fcr
struct ioc3_sioregs {
volatile u8 fill[0x141]; /* starts at 0x141 */
volatile u8 uartc;
volatile u8 kbdcg;
volatile u8 fill0[0x150 - 0x142 - 1];
volatile u8 pp_data;
volatile u8 pp_dsr;
volatile u8 pp_dcr;
volatile u8 fill1[0x158 - 0x152 - 1];
volatile u8 pp_fifa;
volatile u8 pp_cfgb;
volatile u8 pp_ecr;
volatile u8 fill2[0x168 - 0x15a - 1];
volatile u8 rtcad;
volatile u8 rtcdat;
volatile u8 fill3[0x170 - 0x169 - 1];
struct ioc3_uartregs uartb; /* 0x20170 */
struct ioc3_uartregs uarta; /* 0x20178 */
};
/* Register layout of IOC3 in configuration space. */
struct ioc3 {
volatile u32 pad0[7]; /* 0x00000 */
volatile u32 sio_ir; /* 0x0001c */
volatile u32 sio_ies; /* 0x00020 */
volatile u32 sio_iec; /* 0x00024 */
volatile u32 sio_cr; /* 0x00028 */
volatile u32 int_out; /* 0x0002c */
volatile u32 mcr; /* 0x00030 */
/* General Purpose I/O registers */
volatile u32 gpcr_s; /* 0x00034 */
volatile u32 gpcr_c; /* 0x00038 */
volatile u32 gpdr; /* 0x0003c */
volatile u32 gppr_0; /* 0x00040 */
volatile u32 gppr_1; /* 0x00044 */
volatile u32 gppr_2; /* 0x00048 */
volatile u32 gppr_3; /* 0x0004c */
volatile u32 gppr_4; /* 0x00050 */
volatile u32 gppr_5; /* 0x00054 */
volatile u32 gppr_6; /* 0x00058 */
volatile u32 gppr_7; /* 0x0005c */
volatile u32 gppr_8; /* 0x00060 */
volatile u32 gppr_9; /* 0x00064 */
volatile u32 gppr_10; /* 0x00068 */
volatile u32 gppr_11; /* 0x0006c */
volatile u32 gppr_12; /* 0x00070 */
volatile u32 gppr_13; /* 0x00074 */
volatile u32 gppr_14; /* 0x00078 */
volatile u32 gppr_15; /* 0x0007c */
/* Parallel Port Registers */
volatile u32 ppbr_h_a; /* 0x00080 */
volatile u32 ppbr_l_a; /* 0x00084 */
volatile u32 ppcr_a; /* 0x00088 */
volatile u32 ppcr; /* 0x0008c */
volatile u32 ppbr_h_b; /* 0x00090 */
volatile u32 ppbr_l_b; /* 0x00094 */
volatile u32 ppcr_b; /* 0x00098 */
/* Keyboard and Mouse Registers */
volatile u32 km_csr; /* 0x0009c */
volatile u32 k_rd; /* 0x000a0 */
volatile u32 m_rd; /* 0x000a4 */
volatile u32 k_wd; /* 0x000a8 */
volatile u32 m_wd; /* 0x000ac */
/* Serial Port Registers */
volatile u32 sbbr_h; /* 0x000b0 */
volatile u32 sbbr_l; /* 0x000b4 */
volatile u32 sscr_a; /* 0x000b8 */
volatile u32 stpir_a; /* 0x000bc */
volatile u32 stcir_a; /* 0x000c0 */
volatile u32 srpir_a; /* 0x000c4 */
volatile u32 srcir_a; /* 0x000c8 */
volatile u32 srtr_a; /* 0x000cc */
volatile u32 shadow_a; /* 0x000d0 */
volatile u32 sscr_b; /* 0x000d4 */
volatile u32 stpir_b; /* 0x000d8 */
volatile u32 stcir_b; /* 0x000dc */
volatile u32 srpir_b; /* 0x000e0 */
volatile u32 srcir_b; /* 0x000e4 */
volatile u32 srtr_b; /* 0x000e8 */
volatile u32 shadow_b; /* 0x000ec */
/* Ethernet Registers */
volatile u32 emcr; /* 0x000f0 */
volatile u32 eisr; /* 0x000f4 */
volatile u32 eier; /* 0x000f8 */
volatile u32 ercsr; /* 0x000fc */
volatile u32 erbr_h; /* 0x00100 */
volatile u32 erbr_l; /* 0x00104 */
volatile u32 erbar; /* 0x00108 */
volatile u32 ercir; /* 0x0010c */
volatile u32 erpir; /* 0x00110 */
volatile u32 ertr; /* 0x00114 */
volatile u32 etcsr; /* 0x00118 */
volatile u32 ersr; /* 0x0011c */
volatile u32 etcdc; /* 0x00120 */
volatile u32 ebir; /* 0x00124 */
volatile u32 etbr_h; /* 0x00128 */
volatile u32 etbr_l; /* 0x0012c */
volatile u32 etcir; /* 0x00130 */
volatile u32 etpir; /* 0x00134 */
volatile u32 emar_h; /* 0x00138 */
volatile u32 emar_l; /* 0x0013c */
volatile u32 ehar_h; /* 0x00140 */
volatile u32 ehar_l; /* 0x00144 */
volatile u32 micr; /* 0x00148 */
volatile u32 midr_r; /* 0x0014c */
volatile u32 midr_w; /* 0x00150 */
volatile u32 pad1[(0x20000 - 0x00154) / 4];
/* SuperIO Registers XXX */
struct ioc3_sioregs sregs; /* 0x20000 */
volatile u32 pad2[(0x40000 - 0x20180) / 4];
/* SSRAM Diagnostic Access */
volatile u32 ssram[(0x80000 - 0x40000) / 4];
/* Bytebus device offsets
0x80000 - Access to the generic devices selected with DEV0
0x9FFFF bytebus DEV_SEL_0
0xA0000 - Access to the generic devices selected with DEV1
0xBFFFF bytebus DEV_SEL_1
0xC0000 - Access to the generic devices selected with DEV2
0xDFFFF bytebus DEV_SEL_2
0xE0000 - Access to the generic devices selected with DEV3
0xFFFFF bytebus DEV_SEL_3 */
};
/*
* Ethernet RX Buffer
*/
struct ioc3_erxbuf {
u32 w0; /* first word (valid,bcnt,cksum) */
u32 err; /* second word various errors */
/* next comes n bytes of padding */
/* then the received ethernet frame itself */
};
#define ERXBUF_IPCKSUM_MASK 0x0000ffff
#define ERXBUF_BYTECNT_MASK 0x07ff0000
#define ERXBUF_BYTECNT_SHIFT 16
#define ERXBUF_V 0x80000000
#define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */
#define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */
#define ERXBUF_CODERR 0x00000004 /* aka RSV13 */
#define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */
#define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */
#define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */
#define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */
#define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */
#define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */
#define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */
#define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */
#define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */
/*
* Ethernet TX Descriptor
*/
#define ETXD_DATALEN 104
struct ioc3_etxd {
u32 cmd; /* command field */
u32 bufcnt; /* buffer counts field */
u64 p1; /* buffer pointer 1 */
u64 p2; /* buffer pointer 2 */
u8 data[ETXD_DATALEN]; /* opt. tx data */
};
#define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */
#define ETXD_INTWHENDONE 0x00001000 /* intr when done */
#define ETXD_D0V 0x00010000 /* data 0 valid */
#define ETXD_B1V 0x00020000 /* buf 1 valid */
#define ETXD_B2V 0x00040000 /* buf 2 valid */
#define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */
#define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */
#define ETXD_CHKOFF_SHIFT 20
#define ETXD_D0CNT_MASK 0x0000007f
#define ETXD_B1CNT_MASK 0x0007ff00
#define ETXD_B1CNT_SHIFT 8
#define ETXD_B2CNT_MASK 0x7ff00000
#define ETXD_B2CNT_SHIFT 20
/*
* Bytebus device space
*/
#define IOC3_BYTEBUS_DEV0 0x80000L
#define IOC3_BYTEBUS_DEV1 0xa0000L
#define IOC3_BYTEBUS_DEV2 0xc0000L
#define IOC3_BYTEBUS_DEV3 0xe0000L
/* ------------------------------------------------------------------------- */
/* Superio Registers (PIO Access) */
#define IOC3_SIO_BASE 0x20000
#define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141) /* UART Config */
#define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142) /* KBD Config */
#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */
#define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168) /* Real Time Clock */
#define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE) /* UART B */
#define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE) /* UART A */
/* SSRAM Diagnostic Access */
#define IOC3_SSRAM IOC3_RAM_OFF /* base of SSRAM diagnostic access */
#define IOC3_SSRAM_LEN 0x40000 /* 256kb (address space size, may not be fully populated) */
#define IOC3_SSRAM_DM 0x0000ffff /* data mask */
#define IOC3_SSRAM_PM 0x00010000 /* parity mask */
/* bitmasks for PCI_SCR */
#define PCI_SCR_PAR_RESP_EN 0x00000040 /* enb PCI parity checking */
#define PCI_SCR_SERR_EN 0x00000100 /* enable the SERR# driver */
#define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */
#define PCI_SCR_RX_SERR (0x1 << 16)
#define PCI_SCR_DROP_MODE (0x1 << 17)
#define PCI_SCR_SIG_PAR_ERR (0x1 << 24)
#define PCI_SCR_SIG_TAR_ABRT (0x1 << 27)
#define PCI_SCR_RX_TAR_ABRT (0x1 << 28)
#define PCI_SCR_SIG_MST_ABRT (0x1 << 29)
#define PCI_SCR_SIG_SERR (0x1 << 30)
#define PCI_SCR_PAR_ERR (0x1 << 31)
/* bitmasks for IOC3_KM_CSR */
#define KM_CSR_K_WRT_PEND 0x00000001 /* kbd port xmitting or resetting */
#define KM_CSR_M_WRT_PEND 0x00000002 /* mouse port xmitting or resetting */
#define KM_CSR_K_LCB 0x00000004 /* Line Cntrl Bit for last KBD write */
#define KM_CSR_M_LCB 0x00000008 /* same for mouse */
#define KM_CSR_K_DATA 0x00000010 /* state of kbd data line */
#define KM_CSR_K_CLK 0x00000020 /* state of kbd clock line */
#define KM_CSR_K_PULL_DATA 0x00000040 /* pull kbd data line low */
#define KM_CSR_K_PULL_CLK 0x00000080 /* pull kbd clock line low */
#define KM_CSR_M_DATA 0x00000100 /* state of ms data line */
#define KM_CSR_M_CLK 0x00000200 /* state of ms clock line */
#define KM_CSR_M_PULL_DATA 0x00000400 /* pull ms data line low */
#define KM_CSR_M_PULL_CLK 0x00000800 /* pull ms clock line low */
#define KM_CSR_EMM_MODE 0x00001000 /* emulation mode */
#define KM_CSR_SIM_MODE 0x00002000 /* clock X8 */
#define KM_CSR_K_SM_IDLE 0x00004000 /* Keyboard is idle */
#define KM_CSR_M_SM_IDLE 0x00008000 /* Mouse is idle */
#define KM_CSR_K_TO 0x00010000 /* Keyboard trying to send/receive */
#define KM_CSR_M_TO 0x00020000 /* Mouse trying to send/receive */
#define KM_CSR_K_TO_EN 0x00040000 /* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause
SIO_IR to assert */
#define KM_CSR_M_TO_EN 0x00080000 /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause
SIO_IR to assert */
#define KM_CSR_K_CLAMP_ONE 0x00100000 /* Pull K_CLK low after rec. one char */
#define KM_CSR_M_CLAMP_ONE 0x00200000 /* Pull M_CLK low after rec. one char */
#define KM_CSR_K_CLAMP_THREE 0x00400000 /* Pull K_CLK low after rec. three chars */
#define KM_CSR_M_CLAMP_THREE 0x00800000 /* Pull M_CLK low after rec. three char */
/* bitmasks for IOC3_K_RD and IOC3_M_RD */
#define KM_RD_DATA_2 0x000000ff /* 3rd char recvd since last read */
#define KM_RD_DATA_2_SHIFT 0
#define KM_RD_DATA_1 0x0000ff00 /* 2nd char recvd since last read */
#define KM_RD_DATA_1_SHIFT 8
#define KM_RD_DATA_0 0x00ff0000 /* 1st char recvd since last read */
#define KM_RD_DATA_0_SHIFT 16
#define KM_RD_FRAME_ERR_2 0x01000000 /* framing or parity error in byte 2 */
#define KM_RD_FRAME_ERR_1 0x02000000 /* same for byte 1 */
#define KM_RD_FRAME_ERR_0 0x04000000 /* same for byte 0 */
#define KM_RD_KBD_MSE 0x08000000 /* 0 if from kbd, 1 if from mouse */
#define KM_RD_OFLO 0x10000000 /* 4th char recvd before this read */
#define KM_RD_VALID_2 0x20000000 /* DATA_2 valid */
#define KM_RD_VALID_1 0x40000000 /* DATA_1 valid */
#define KM_RD_VALID_0 0x80000000 /* DATA_0 valid */
#define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2)
/* bitmasks for IOC3_K_WD & IOC3_M_WD */
#define KM_WD_WRT_DATA 0x000000ff /* write to keyboard/mouse port */
#define KM_WD_WRT_DATA_SHIFT 0
/* bitmasks for serial RX status byte */
#define RXSB_OVERRUN 0x01 /* char(s) lost */
#define RXSB_PAR_ERR 0x02 /* parity error */
#define RXSB_FRAME_ERR 0x04 /* framing error */
#define RXSB_BREAK 0x08 /* break character */
#define RXSB_CTS 0x10 /* state of CTS */
#define RXSB_DCD 0x20 /* state of DCD */
#define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */
#define RXSB_DATA_VALID 0x80 /* data byte, FRAME_ERR PAR_ERR & BREAK valid */
/* bitmasks for serial TX control byte */
#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */
#define TXCB_INVALID 0x00 /* byte is invalid */
#define TXCB_VALID 0x40 /* byte is valid */
#define TXCB_MCR 0x80 /* data<7:0> to modem control register */
#define TXCB_DELAY 0xc0 /* delay data<7:0> mSec */
/* bitmasks for IOC3_SBBR_L */
#define SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */
#define SBBR_L_BASE 0xfffff000 /* lower serial ring base addr */
/* bitmasks for IOC3_SSCR_<A:B> */
#define SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */
#define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
#define SSCR_HFC_EN 0x00020000 /* hardware flow control enabled */
#define SSCR_RX_RING_DCD 0x00040000 /* post RX record on delta-DCD */
#define SSCR_RX_RING_CTS 0x00080000 /* post RX record on delta-CTS */
#define SSCR_HIGH_SPD 0x00100000 /* 4X speed */
#define SSCR_DIAG 0x00200000 /* bypass clock divider for sim */
#define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */
#define SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */
#define SSCR_DMA_PAUSE 0x20000000 /* pause DMA */
#define SSCR_PAUSE_STATE 0x40000000 /* sets when PAUSE takes effect */
#define SSCR_RESET 0x80000000 /* reset DMA channels */
/* all producer/comsumer pointers are the same bitfield */
#define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */
#define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */
#define PROD_CONS_PTR_OFF 3
/* bitmasks for IOC3_SRCIR_<A:B> */
#define SRCIR_ARM 0x80000000 /* arm RX timer */
/* bitmasks for IOC3_SRPIR_<A:B> */
#define SRPIR_BYTE_CNT 0x07000000 /* bytes in packer */
#define SRPIR_BYTE_CNT_SHIFT 24
/* bitmasks for IOC3_STCIR_<A:B> */
#define STCIR_BYTE_CNT 0x0f000000 /* bytes in unpacker */
#define STCIR_BYTE_CNT_SHIFT 24
/* bitmasks for IOC3_SHADOW_<A:B> */
#define SHADOW_DR 0x00000001 /* data ready */
#define SHADOW_OE 0x00000002 /* overrun error */
#define SHADOW_PE 0x00000004 /* parity error */
#define SHADOW_FE 0x00000008 /* framing error */
#define SHADOW_BI 0x00000010 /* break interrupt */
#define SHADOW_THRE 0x00000020 /* transmit holding register empty */
#define SHADOW_TEMT 0x00000040 /* transmit shift register empty */
#define SHADOW_RFCE 0x00000080 /* char in RX fifo has an error */
#define SHADOW_DCTS 0x00010000 /* delta clear to send */
#define SHADOW_DDCD 0x00080000 /* delta data carrier detect */
#define SHADOW_CTS 0x00100000 /* clear to send */
#define SHADOW_DCD 0x00800000 /* data carrier detect */
#define SHADOW_DTR 0x01000000 /* data terminal ready */
#define SHADOW_RTS 0x02000000 /* request to send */
#define SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
#define SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
#define SHADOW_LOOP 0x10000000 /* loopback enabled */
/* bitmasks for IOC3_SRTR_<A:B> */
#define SRTR_CNT 0x00000fff /* reload value for RX timer */
#define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */
#define SRTR_CNT_VAL_SHIFT 16
#define SRTR_HZ 16000 /* SRTR clock frequency */
/* bitmasks for IOC3_SIO_IR, IOC3_SIO_IEC and IOC3_SIO_IES */
#define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */
#define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */
#define SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */
#define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */
#define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */
#define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */
#define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */
#define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */
#define SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */
#define SIO_IR_SB_TX_MT 0x00000200 /* */
#define SIO_IR_SB_RX_FULL 0x00000400 /* */
#define SIO_IR_SB_RX_HIGH 0x00000800 /* */
#define SIO_IR_SB_RX_TIMER 0x00001000 /* */
#define SIO_IR_SB_DELTA_DCD 0x00002000 /* */
#define SIO_IR_SB_DELTA_CTS 0x00004000 /* */
#define SIO_IR_SB_INT 0x00008000 /* */
#define SIO_IR_SB_TX_EXPLICIT 0x00010000 /* */
#define SIO_IR_SB_MEMERR 0x00020000 /* */
#define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */
#define SIO_IR_PP_INTA 0x00080000 /* PP context A thru */
#define SIO_IR_PP_INTB 0x00100000 /* PP context B thru */
#define SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */
#define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */
#define SIO_IR_RT_INT 0x08000000 /* RT output pulse */
#define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */
#define SIO_IR_GEN_INT_SHIFT 28
/* per device interrupt masks */
#define SIO_IR_SA (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | \
SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | \
SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | \
SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | \
SIO_IR_SA_MEMERR)
#define SIO_IR_SB (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | \
SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | \
SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | \
SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | \
SIO_IR_SB_MEMERR)
#define SIO_IR_PP (SIO_IR_PP_INT | SIO_IR_PP_INTA | \
SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
#define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
/* macro to load pending interrupts */
#define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \
PCI_INW(&((mem)->sio_ies_ro)))
/* bitmasks for SIO_CR */
#define SIO_CR_SIO_RESET 0x00000001 /* reset the SIO */
#define SIO_CR_SER_A_BASE 0x000000fe /* DMA poll addr port A */
#define SIO_CR_SER_A_BASE_SHIFT 1
#define SIO_CR_SER_B_BASE 0x00007f00 /* DMA poll addr port B */
#define SIO_CR_SER_B_BASE_SHIFT 8
#define SIO_SR_CMD_PULSE 0x00078000 /* byte bus strobe length */
#define SIO_CR_CMD_PULSE_SHIFT 15
#define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */
#define SIO_CR_ARB_DIAG_TXA 0x00000000
#define SIO_CR_ARB_DIAG_RXA 0x00080000
#define SIO_CR_ARB_DIAG_TXB 0x00100000
#define SIO_CR_ARB_DIAG_RXB 0x00180000
#define SIO_CR_ARB_DIAG_PP 0x00200000
#define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */
/* bitmasks for INT_OUT */
#define INT_OUT_COUNT 0x0000ffff /* pulse interval timer */
#define INT_OUT_MODE 0x00070000 /* mode mask */
#define INT_OUT_MODE_0 0x00000000 /* set output to 0 */
#define INT_OUT_MODE_1 0x00040000 /* set output to 1 */
#define INT_OUT_MODE_1PULSE 0x00050000 /* send 1 pulse */
#define INT_OUT_MODE_PULSES 0x00060000 /* send 1 pulse every interval */
#define INT_OUT_MODE_SQW 0x00070000 /* toggle output every interval */
#define INT_OUT_DIAG 0x40000000 /* diag mode */
#define INT_OUT_INT_OUT 0x80000000 /* current state of INT_OUT */
/* time constants for INT_OUT */
#define INT_OUT_NS_PER_TICK (30 * 260) /* 30 ns PCI clock, divisor=260 */
#define INT_OUT_TICKS_PER_PULSE 3 /* outgoing pulse lasts 3 ticks */
#define INT_OUT_US_TO_COUNT(x) /* convert uS to a count value */ \
(((x) * 10 + INT_OUT_NS_PER_TICK / 200) * \
100 / INT_OUT_NS_PER_TICK - 1)
#define INT_OUT_COUNT_TO_US(x) /* convert count value to uS */ \
(((x) + 1) * INT_OUT_NS_PER_TICK / 1000)
#define INT_OUT_MIN_TICKS 3 /* min period is width of pulse in "ticks" */
#define INT_OUT_MAX_TICKS INT_OUT_COUNT /* largest possible count */
/* bitmasks for GPCR */
#define GPCR_DIR 0x000000ff /* tristate pin input or output */
#define GPCR_DIR_PIN(x) (1<<(x)) /* access one of the DIR bits */
#define GPCR_EDGE 0x000f0000 /* extint edge or level sensitive */
#define GPCR_EDGE_PIN(x) (1<<((x)+15)) /* access one of the EDGE bits */
/* values for GPCR */
#define GPCR_INT_OUT_EN 0x00100000 /* enable INT_OUT to pin 0 */
#define GPCR_MLAN_EN 0x00200000 /* enable MCR to pin 8 */
#define GPCR_DIR_SERA_XCVR 0x00000080 /* Port A Transceiver select enable */
#define GPCR_DIR_SERB_XCVR 0x00000040 /* Port B Transceiver select enable */
#define GPCR_DIR_PHY_RST 0x00000020 /* ethernet PHY reset enable */
/* defs for some of the generic I/O pins */
#define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */
#define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */
#define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */
#define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */
#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin controlling uart b mode select */
#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin controlling uart a mode select */
#define EMCR_DUPLEX 0x00000001
#define EMCR_PROMISC 0x00000002
#define EMCR_PADEN 0x00000004
#define EMCR_RXOFF_MASK 0x000001f8
#define EMCR_RXOFF_SHIFT 3
#define EMCR_RAMPAR 0x00000200
#define EMCR_BADPAR 0x00000800
#define EMCR_BUFSIZ 0x00001000
#define EMCR_TXDMAEN 0x00002000
#define EMCR_TXEN 0x00004000
#define EMCR_RXDMAEN 0x00008000
#define EMCR_RXEN 0x00010000
#define EMCR_LOOPBACK 0x00020000
#define EMCR_ARB_DIAG 0x001c0000
#define EMCR_ARB_DIAG_IDLE 0x00200000
#define EMCR_RST 0x80000000
#define EISR_RXTIMERINT 0x00000001
#define EISR_RXTHRESHINT 0x00000002
#define EISR_RXOFLO 0x00000004
#define EISR_RXBUFOFLO 0x00000008
#define EISR_RXMEMERR 0x00000010
#define EISR_RXPARERR 0x00000020
#define EISR_TXEMPTY 0x00010000
#define EISR_TXRTRY 0x00020000
#define EISR_TXEXDEF 0x00040000
#define EISR_TXLCOL 0x00080000
#define EISR_TXGIANT 0x00100000
#define EISR_TXBUFUFLO 0x00200000
#define EISR_TXEXPLICIT 0x00400000
#define EISR_TXCOLLWRAP 0x00800000
#define EISR_TXDEFERWRAP 0x01000000
#define EISR_TXMEMERR 0x02000000
#define EISR_TXPARERR 0x04000000
#define ERCSR_THRESH_MASK 0x000001ff /* enet RX threshold */
#define ERCSR_RX_TMR 0x40000000 /* simulation only */
#define ERCSR_DIAG_OFLO 0x80000000 /* simulation only */
#define ERBR_ALIGNMENT 4096
#define ERBR_L_RXRINGBASE_MASK 0xfffff000
#define ERBAR_BARRIER_BIT 0x0100
#define ERBAR_RXBARR_MASK 0xffff0000
#define ERBAR_RXBARR_SHIFT 16
#define ERCIR_RXCONSUME_MASK 0x00000fff
#define ERPIR_RXPRODUCE_MASK 0x00000fff
#define ERPIR_ARM 0x80000000
#define ERTR_CNT_MASK 0x000007ff
#define ETCSR_IPGT_MASK 0x0000007f
#define ETCSR_IPGR1_MASK 0x00007f00
#define ETCSR_IPGR1_SHIFT 8
#define ETCSR_IPGR2_MASK 0x007f0000
#define ETCSR_IPGR2_SHIFT 16
#define ETCSR_NOTXCLK 0x80000000
#define ETCDC_COLLCNT_MASK 0x0000ffff
#define ETCDC_DEFERCNT_MASK 0xffff0000
#define ETCDC_DEFERCNT_SHIFT 16
#define ETBR_ALIGNMENT (64*1024)
#define ETBR_L_RINGSZ_MASK 0x00000001
#define ETBR_L_RINGSZ128 0
#define ETBR_L_RINGSZ512 1
#define ETBR_L_TXRINGBASE_MASK 0xffffc000
#define ETCIR_TXCONSUME_MASK 0x0000ffff
#define ETCIR_IDLE 0x80000000
#define ETPIR_TXPRODUCE_MASK 0x0000ffff
#define EBIR_TXBUFPROD_MASK 0x0000001f
#define EBIR_TXBUFCONS_MASK 0x00001f00
#define EBIR_TXBUFCONS_SHIFT 8
#define EBIR_RXBUFPROD_MASK 0x007fc000
#define EBIR_RXBUFPROD_SHIFT 14
#define EBIR_RXBUFCONS_MASK 0xff800000
#define EBIR_RXBUFCONS_SHIFT 23
#define MICR_REGADDR_MASK 0x0000001f
#define MICR_PHYADDR_MASK 0x000003e0
#define MICR_PHYADDR_SHIFT 5
#define MICR_READTRIG 0x00000400
#define MICR_BUSY 0x00000800
#define MIDR_DATA_MASK 0x0000ffff
#define ERXBUF_IPCKSUM_MASK 0x0000ffff
#define ERXBUF_BYTECNT_MASK 0x07ff0000
#define ERXBUF_BYTECNT_SHIFT 16
#define ERXBUF_V 0x80000000
#define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */
#define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */
#define ERXBUF_CODERR 0x00000004 /* aka RSV13 */
#define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */
#define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */
#define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */
#define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */
#define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */
#define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */
#define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */
#define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */
#define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */
#define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */
#define ETXD_INTWHENDONE 0x00001000 /* intr when done */
#define ETXD_D0V 0x00010000 /* data 0 valid */
#define ETXD_B1V 0x00020000 /* buf 1 valid */
#define ETXD_B2V 0x00040000 /* buf 2 valid */
#define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */
#define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */
#define ETXD_CHKOFF_SHIFT 20
#define ETXD_D0CNT_MASK 0x0000007f
#define ETXD_B1CNT_MASK 0x0007ff00
#define ETXD_B1CNT_SHIFT 8
#define ETXD_B2CNT_MASK 0x7ff00000
#define ETXD_B2CNT_SHIFT 20
typedef enum ioc3_subdevs_e {
ioc3_subdev_ether,
ioc3_subdev_generic,
ioc3_subdev_nic,
ioc3_subdev_kbms,
ioc3_subdev_ttya,
ioc3_subdev_ttyb,
ioc3_subdev_ecpp,
ioc3_subdev_rt,
ioc3_nsubdevs
} ioc3_subdev_t;
/* subdevice disable bits,
* from the standard INFO_LBL_SUBDEVS
*/
#define IOC3_SDB_ETHER (1<<ioc3_subdev_ether)
#define IOC3_SDB_GENERIC (1<<ioc3_subdev_generic)
#define IOC3_SDB_NIC (1<<ioc3_subdev_nic)
#define IOC3_SDB_KBMS (1<<ioc3_subdev_kbms)
#define IOC3_SDB_TTYA (1<<ioc3_subdev_ttya)
#define IOC3_SDB_TTYB (1<<ioc3_subdev_ttyb)
#define IOC3_SDB_ECPP (1<<ioc3_subdev_ecpp)
#define IOC3_SDB_RT (1<<ioc3_subdev_rt)
#define IOC3_ALL_SUBDEVS ((1<<ioc3_nsubdevs)-1)
#define IOC3_SDB_SERIAL (IOC3_SDB_TTYA|IOC3_SDB_TTYB)
#define IOC3_STD_SUBDEVS IOC3_ALL_SUBDEVS
#define IOC3_INTA_SUBDEVS IOC3_SDB_ETHER
#define IOC3_INTB_SUBDEVS (IOC3_SDB_GENERIC|IOC3_SDB_KBMS|IOC3_SDB_SERIAL|IOC3_SDB_ECPP|IOC3_SDB_RT)
#endif /* _IOC3_H */
include/asm-mips/sn/klconfig.h
+980
View File
@@ -0,0 +1,980 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Derived from IRIX <sys/SN/klconfig.h>.
*
* Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 1999, 2000 by Ralf Baechle
*/
#ifndef _ASM_SN_KLCONFIG_H
#define _ASM_SN_KLCONFIG_H
/*
* The KLCONFIG structures store info about the various BOARDs found
* during Hardware Discovery. In addition, it stores info about the
* components found on the BOARDs.
*/
/*
* WARNING:
* Certain assembly language routines (notably xxxxx.s) in the IP27PROM
* will depend on the format of the data structures in this file. In
* most cases, rearranging the fields can seriously break things.
* Adding fields in the beginning or middle can also break things.
* Add fields if necessary, to the end of a struct in such a way
* that offsets of existing fields do not change.
*/
#include <linux/config.h>
#include <linux/types.h>
#include <asm/sn/types.h>
#if defined(CONFIG_SGI_IP27)
#include <asm/sn/sn0/addrs.h>
//#include <sys/SN/router.h>
// XXX Stolen from <sys/SN/router.h>:
#define MAX_ROUTER_PORTS (6) /* Max. number of ports on a router */
#include <asm/sn/sn0/sn0_fru.h>
//#include <sys/graph.h>
//#include <sys/xtalk/xbow.h>
#elif defined(CONFIG_SGI_IP35)
#include <asm/sn/sn1/addrs.h>
#include <sys/sn/router.h>
#include <sys/graph.h>
#include <asm/xtalk/xbow.h>
#endif /* !CONFIG_SGI_IP27 && !CONFIG_SGI_IP35 */
#if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP35)
#include <asm/sn/agent.h>
#include <asm/arc/types.h>
#include <asm/arc/hinv.h>
#if defined(CONFIG_SGI_IO) || defined(CONFIG_SGI_IP35)
// The hack file has to be before vector and after sn0_fru....
#include <asm/hack.h>
#include <asm/sn/vector.h>
#include <asm/xtalk/xtalk.h>
#endif /* CONFIG_SGI_IO || CONFIG_SGI_IP35 */
#endif /* CONFIG_SGI_IP27 || CONFIG_SGI_IP35 */
#define KLCFGINFO_MAGIC 0xbeedbabe
#ifdef FRUTEST
typedef u64 klconf_off_t;
#else
typedef s32 klconf_off_t;
#endif
/*
* Some IMPORTANT OFFSETS. These are the offsets on all NODES.
*/
#if 0
#define RAMBASE 0
#define ARCSSPB_OFF 0x1000 /* shift it to sys/arcs/spb.h */
#define OFF_HWGRAPH 0
#endif
#define MAX_MODULE_ID 255
#define SIZE_PAD 4096 /* 4k padding for structures */
/*
* 1 NODE brd, 2 Router brd (1 8p, 1 meta), 6 Widgets,
* 2 Midplanes assuming no pci card cages
*/
#define MAX_SLOTS_PER_NODE (1 + 2 + 6 + 2)
/* XXX if each node is guranteed to have some memory */
#define MAX_PCI_DEVS 8
/* lboard_t->brd_flags fields */
/* All bits in this field are currently used. Try the pad fields if
you need more flag bits */
#define ENABLE_BOARD 0x01
#define FAILED_BOARD 0x02
#define DUPLICATE_BOARD 0x04 /* Boards like midplanes/routers which
are discovered twice. Use one of them */
#define VISITED_BOARD 0x08 /* Used for compact hub numbering. */
#define LOCAL_MASTER_IO6 0x10 /* master io6 for that node */
#define GLOBAL_MASTER_IO6 0x20
#define THIRD_NIC_PRESENT 0x40 /* for future use */
#define SECOND_NIC_PRESENT 0x80 /* addons like MIO are present */
/* klinfo->flags fields */
#define KLINFO_ENABLE 0x01 /* This component is enabled */
#define KLINFO_FAILED 0x02 /* This component failed */
#define KLINFO_DEVICE 0x04 /* This component is a device */
#define KLINFO_VISITED 0x08 /* This component has been visited */
#define KLINFO_CONTROLLER 0x10 /* This component is a device controller */
#define KLINFO_INSTALL 0x20 /* Install a driver */
#define KLINFO_HEADLESS 0x40 /* Headless (or hubless) component */
#define IS_CONSOLE_IOC3(i) ((((klinfo_t *)i)->flags) & KLINFO_INSTALL)
#define GB2 0x80000000
#define MAX_RSV_PTRS 32
/* Structures to manage various data storage areas */
/* The numbers must be contiguous since the array index i
is used in the code to allocate various areas.
*/
#define BOARD_STRUCT 0
#define COMPONENT_STRUCT 1
#define ERRINFO_STRUCT 2
#define KLMALLOC_TYPE_MAX (ERRINFO_STRUCT + 1)
#define DEVICE_STRUCT 3
typedef struct console_s {
#if defined(CONFIG_SGI_IO) /* FIXME */
__psunsigned_t uart_base;
__psunsigned_t config_base;
__psunsigned_t memory_base;
#else
unsigned long uart_base;
unsigned long config_base;
unsigned long memory_base;
#endif
short baud;
short flag;
int type;
nasid_t nasid;
char wid;
char npci;
nic_t baseio_nic;
} console_t;
typedef struct klc_malloc_hdr {
klconf_off_t km_base;
klconf_off_t km_limit;
klconf_off_t km_current;
} klc_malloc_hdr_t;
/* Functions/macros needed to use this structure */
typedef struct kl_config_hdr {
u64 ch_magic; /* set this to KLCFGINFO_MAGIC */
u32 ch_version; /* structure version number */
klconf_off_t ch_malloc_hdr_off; /* offset of ch_malloc_hdr */
klconf_off_t ch_cons_off; /* offset of ch_cons */
klconf_off_t ch_board_info; /* the link list of boards */
console_t ch_cons_info; /* address info of the console */
klc_malloc_hdr_t ch_malloc_hdr[KLMALLOC_TYPE_MAX];
confidence_t ch_sw_belief; /* confidence that software is bad*/
confidence_t ch_sn0net_belief; /* confidence that sn0net is bad */
} kl_config_hdr_t;
#define KL_CONFIG_HDR(_nasid) ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid)))
#if 0
#define KL_CONFIG_MALLOC_HDR(_nasid) \
(KL_CONFIG_HDR(_nasid)->ch_malloc_hdr)
#endif
#define KL_CONFIG_INFO_OFFSET(_nasid) \
(KL_CONFIG_HDR(_nasid)->ch_board_info)
#define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off) \
(KL_CONFIG_HDR(_nasid)->ch_board_info = (_off))
#define KL_CONFIG_INFO(_nasid) \
(lboard_t *)((KL_CONFIG_HDR(_nasid)->ch_board_info) ? \
NODE_OFFSET_TO_K1((_nasid), KL_CONFIG_HDR(_nasid)->ch_board_info) : \
0)
#define KL_CONFIG_MAGIC(_nasid) (KL_CONFIG_HDR(_nasid)->ch_magic)
#define KL_CONFIG_CHECK_MAGIC(_nasid) \
(KL_CONFIG_HDR(_nasid)->ch_magic == KLCFGINFO_MAGIC)
#define KL_CONFIG_HDR_INIT_MAGIC(_nasid) \
(KL_CONFIG_HDR(_nasid)->ch_magic = KLCFGINFO_MAGIC)
/* --- New Macros for the changed kl_config_hdr_t structure --- */
#if defined(CONFIG_SGI_IO)
#define PTR_CH_MALLOC_HDR(_k) ((klc_malloc_hdr_t *)\
((__psunsigned_t)_k + (_k->ch_malloc_hdr_off)))
#else
#define PTR_CH_MALLOC_HDR(_k) ((klc_malloc_hdr_t *)\
(unsigned long)_k + (_k->ch_malloc_hdr_off)))
#endif
#define KL_CONFIG_CH_MALLOC_HDR(_n) PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n))
#if defined(CONFIG_SGI_IO)
#define PTR_CH_CONS_INFO(_k) ((console_t *)\
((__psunsigned_t)_k + (_k->ch_cons_off)))
#else
#define PTR_CH_CONS_INFO(_k) ((console_t *)\
((unsigned long)_k + (_k->ch_cons_off)))
#endif
#define KL_CONFIG_CH_CONS_INFO(_n) PTR_CH_CONS_INFO(KL_CONFIG_HDR(_n))
/* ------------------------------------------------------------- */
#define KL_CONFIG_INFO_START(_nasid) \
(klconf_off_t)(KLCONFIG_OFFSET(_nasid) + sizeof(kl_config_hdr_t))
#define KL_CONFIG_BOARD_NASID(_brd) ((_brd)->brd_nasid)
#define KL_CONFIG_BOARD_SET_NEXT(_brd, _off) ((_brd)->brd_next = (_off))
#define KL_CONFIG_DUPLICATE_BOARD(_brd) ((_brd)->brd_flags & DUPLICATE_BOARD)
#define XBOW_PORT_TYPE_HUB(_xbowp, _link) \
((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_HUB)
#define XBOW_PORT_TYPE_IO(_xbowp, _link) \
((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_IO)
#define XBOW_PORT_IS_ENABLED(_xbowp, _link) \
((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_ENABLE)
#define XBOW_PORT_NASID(_xbowp, _link) \
((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_nasid)
#define XBOW_PORT_IO 0x1
#define XBOW_PORT_HUB 0x2
#define XBOW_PORT_ENABLE 0x4
#define SN0_PORT_FENCE_SHFT 0
#define SN0_PORT_FENCE_MASK (1 << SN0_PORT_FENCE_SHFT)
/*
* The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD
* can be either 'LOCAL' or 'REMOTE'. LOCAL means it is attached to
* the LOCAL/current NODE. REMOTE means it is attached to a different
* node.(TBD - Need a way to treat ROUTER boards.)
*
* There are 2 different structures to represent these boards -
* lboard - Local board, rboard - remote board. These 2 structures
* can be arbitrarily mixed in the LINKED LIST of BOARDs. (Refer
* Figure below). The first byte of the rboard or lboard structure
* is used to find out its type - no unions are used.
* If it is a lboard, then the config info of this board will be found
* on the local node. (LOCAL NODE BASE + offset value gives pointer to
* the structure.
* If it is a rboard, the local structure contains the node number
* and the offset of the beginning of the LINKED LIST on the remote node.
* The details of the hardware on a remote node can be built locally,
* if required, by reading the LINKED LIST on the remote node and
* ignoring all the rboards on that node.
*
* The local node uses the REMOTE NODE NUMBER + OFFSET to point to the
* First board info on the remote node. The remote node list is
* traversed as the local list, using the REMOTE BASE ADDRESS and not
* the local base address and ignoring all rboard values.
*
*
KLCONFIG
+------------+ +------------+ +------------+ +------------+
| lboard | +-->| lboard | +-->| rboard | +-->| lboard |
+------------+ | +------------+ | +------------+ | +------------+
| board info | | | board info | | |errinfo,bptr| | | board info |
+------------+ | +------------+ | +------------+ | +------------+
| offset |--+ | offset |--+ | offset |--+ |offset=NULL |
+------------+ +------------+ +------------+ +------------+
+------------+
| board info |
+------------+ +--------------------------------+
| compt 1 |------>| type, rev, diaginfo, size ... | (CPU)
+------------+ +--------------------------------+
| compt 2 |--+
+------------+ | +--------------------------------+
| ... | +--->| type, rev, diaginfo, size ... | (MEM_BANK)
+------------+ +--------------------------------+
| errinfo |--+
+------------+ | +--------------------------------+
+--->|r/l brd errinfo,compt err flags |
+--------------------------------+
*
* Each BOARD consists of COMPONENTs and the BOARD structure has
* pointers (offsets) to its COMPONENT structure.
* The COMPONENT structure has version info, size and speed info, revision,
* error info and the NIC info. This structure can accommodate any
* BOARD with arbitrary COMPONENT composition.
*
* The ERRORINFO part of each BOARD has error information
* that describes errors about the BOARD itself. It also has flags to
* indicate the COMPONENT(s) on the board that have errors. The error
* information specific to the COMPONENT is present in the respective
* COMPONENT structure.
*
* The ERRORINFO structure is also treated like a COMPONENT, ie. the
* BOARD has pointers(offset) to the ERRORINFO structure. The rboard
* structure also has a pointer to the ERRORINFO structure. This is
* the place to store ERRORINFO about a REMOTE NODE, if the HUB on
* that NODE is not working or if the REMOTE MEMORY is BAD. In cases where
* only the CPU of the REMOTE NODE is disabled, the ERRORINFO pointer can
* be a NODE NUMBER, REMOTE OFFSET combination, pointing to error info
* which is present on the REMOTE NODE.(TBD)
* REMOTE ERRINFO can be stored on any of the nearest nodes
* or on all the nearest nodes.(TBD)
* Like BOARD structures, REMOTE ERRINFO structures can be built locally
* using the rboard errinfo pointer.
*
* In order to get useful information from this Data organization, a set of
* interface routines are provided (TBD). The important thing to remember while
* manipulating the structures, is that, the NODE number information should
* be used. If the NODE is non-zero (remote) then each offset should
* be added to the REMOTE BASE ADDR else it should be added to the LOCAL BASE ADDR.
* This includes offsets for BOARDS, COMPONENTS and ERRORINFO.
*
* Note that these structures do not provide much info about connectivity.
* That info will be part of HWGRAPH, which is an extension of the cfg_t
* data structure. (ref IP27prom/cfg.h) It has to be extended to include
* the IO part of the Network(TBD).
*
* The data structures below define the above concepts.
*/
/*
* Values for CPU types
*/
#define KL_CPU_R4000 0x1 /* Standard R4000 */
#define KL_CPU_TFP 0x2 /* TFP processor */
#define KL_CPU_R10000 0x3 /* R10000 (T5) */
#define KL_CPU_NONE (-1) /* no cpu present in slot */
/*
* IP27 BOARD classes
*/
#define KLCLASS_MASK 0xf0
#define KLCLASS_NONE 0x00
#define KLCLASS_NODE 0x10 /* CPU, Memory and HUB board */
#define KLCLASS_CPU KLCLASS_NODE
#define KLCLASS_IO 0x20 /* BaseIO, 4 ch SCSI, ethernet, FDDI
and the non-graphics widget boards */
#define KLCLASS_ROUTER 0x30 /* Router board */
#define KLCLASS_MIDPLANE 0x40 /* We need to treat this as a board
so that we can record error info */
#define KLCLASS_GFX 0x50 /* graphics boards */
#define KLCLASS_PSEUDO_GFX 0x60 /* HDTV type cards that use a gfx
* hw ifc to xtalk and are not gfx
* class for sw purposes */
#define KLCLASS_MAX 7 /* Bump this if a new CLASS is added */
#define KLTYPE_MAX 10 /* Bump this if a new CLASS is added */
#define KLCLASS_UNKNOWN 0xf0
#define KLCLASS(_x) ((_x) & KLCLASS_MASK)
/*
* IP27 board types
*/
#define KLTYPE_MASK 0x0f
#define KLTYPE_NONE 0x00
#define KLTYPE_EMPTY 0x00
#define KLTYPE_WEIRDCPU (KLCLASS_CPU | 0x0)
#define KLTYPE_IP27 (KLCLASS_CPU | 0x1) /* 2 CPUs(R10K) per board */
#define KLTYPE_WEIRDIO (KLCLASS_IO | 0x0)
#define KLTYPE_BASEIO (KLCLASS_IO | 0x1) /* IOC3, SuperIO, Bridge, SCSI */
#define KLTYPE_IO6 KLTYPE_BASEIO /* Additional name */
#define KLTYPE_4CHSCSI (KLCLASS_IO | 0x2)
#define KLTYPE_MSCSI KLTYPE_4CHSCSI /* Additional name */
#define KLTYPE_ETHERNET (KLCLASS_IO | 0x3)
#define KLTYPE_MENET KLTYPE_ETHERNET /* Additional name */
#define KLTYPE_FDDI (KLCLASS_IO | 0x4)
#define KLTYPE_UNUSED (KLCLASS_IO | 0x5) /* XXX UNUSED */
#define KLTYPE_HAROLD (KLCLASS_IO | 0x6) /* PCI SHOE BOX */
#define KLTYPE_PCI KLTYPE_HAROLD
#define KLTYPE_VME (KLCLASS_IO | 0x7) /* Any 3rd party VME card */
#define KLTYPE_MIO (KLCLASS_IO | 0x8)
#define KLTYPE_FC (KLCLASS_IO | 0x9)
#define KLTYPE_LINC (KLCLASS_IO | 0xA)
#define KLTYPE_TPU (KLCLASS_IO | 0xB) /* Tensor Processing Unit */
#define KLTYPE_GSN_A (KLCLASS_IO | 0xC) /* Main GSN board */
#define KLTYPE_GSN_B (KLCLASS_IO | 0xD) /* Auxiliary GSN board */
#define KLTYPE_GFX (KLCLASS_GFX | 0x0) /* unknown graphics type */
#define KLTYPE_GFX_KONA (KLCLASS_GFX | 0x1) /* KONA graphics on IP27 */
#define KLTYPE_GFX_MGRA (KLCLASS_GFX | 0x3) /* MGRAS graphics on IP27 */
#define KLTYPE_WEIRDROUTER (KLCLASS_ROUTER | 0x0)
#define KLTYPE_ROUTER (KLCLASS_ROUTER | 0x1)
#define KLTYPE_ROUTER2 KLTYPE_ROUTER /* Obsolete! */
#define KLTYPE_NULL_ROUTER (KLCLASS_ROUTER | 0x2)
#define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
#define KLTYPE_WEIRDMIDPLANE (KLCLASS_MIDPLANE | 0x0)
#define KLTYPE_MIDPLANE8 (KLCLASS_MIDPLANE | 0x1) /* 8 slot backplane */
#define KLTYPE_MIDPLANE KLTYPE_MIDPLANE8
#define KLTYPE_PBRICK_XBOW (KLCLASS_MIDPLANE | 0x2)
#define KLTYPE_IOBRICK (KLCLASS_IOBRICK | 0x0)
#define KLTYPE_IBRICK (KLCLASS_IOBRICK | 0x1)
#define KLTYPE_PBRICK (KLCLASS_IOBRICK | 0x2)
#define KLTYPE_XBRICK (KLCLASS_IOBRICK | 0x3)
#define KLTYPE_PBRICK_BRIDGE KLTYPE_PBRICK
/* The value of type should be more than 8 so that hinv prints
* out the board name from the NIC string. For values less than
* 8 the name of the board needs to be hard coded in a few places.
* When bringup started nic names had not standardized and so we
* had to hard code. (For people interested in history.)
*/
#define KLTYPE_XTHD (KLCLASS_PSEUDO_GFX | 0x9)
#define KLTYPE_UNKNOWN (KLCLASS_UNKNOWN | 0xf)
#define KLTYPE(_x) ((_x) & KLTYPE_MASK)
#define IS_MIO_PRESENT(l) ((l->brd_type == KLTYPE_BASEIO) && \
(l->brd_flags & SECOND_NIC_PRESENT))
#define IS_MIO_IOC3(l,n) (IS_MIO_PRESENT(l) && (n > 2))
/*
* board structures
*/
#define MAX_COMPTS_PER_BRD 24
#define LOCAL_BOARD 1
#define REMOTE_BOARD 2
#define LBOARD_STRUCT_VERSION 2
typedef struct lboard_s {
klconf_off_t brd_next; /* Next BOARD */
unsigned char struct_type; /* type of structure, local or remote */
unsigned char brd_type; /* type+class */
unsigned char brd_sversion; /* version of this structure */
unsigned char brd_brevision; /* board revision */
unsigned char brd_promver; /* board prom version, if any */
unsigned char brd_flags; /* Enabled, Disabled etc */
unsigned char brd_slot; /* slot number */
unsigned short brd_debugsw; /* Debug switches */
moduleid_t brd_module; /* module to which it belongs */
partid_t brd_partition; /* Partition number */
unsigned short brd_diagval; /* diagnostic value */
unsigned short brd_diagparm; /* diagnostic parameter */
unsigned char brd_inventory; /* inventory history */
unsigned char brd_numcompts; /* Number of components */
nic_t brd_nic; /* Number in CAN */
nasid_t brd_nasid; /* passed parameter */
klconf_off_t brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
klconf_off_t brd_errinfo; /* Board's error information */
struct lboard_s *brd_parent; /* Logical parent for this brd */
vertex_hdl_t brd_graph_link; /* vertex hdl to connect extern compts */
confidence_t brd_confidence; /* confidence that the board is bad */
nasid_t brd_owner; /* who owns this board */
unsigned char brd_nic_flags; /* To handle 8 more NICs */
char brd_name[32];
} lboard_t;
/*
* Make sure we pass back the calias space address for local boards.
* klconfig board traversal and error structure extraction defines.
*/
#define BOARD_SLOT(_brd) ((_brd)->brd_slot)
#define KLCF_CLASS(_brd) KLCLASS((_brd)->brd_type)
#define KLCF_TYPE(_brd) KLTYPE((_brd)->brd_type)
#define KLCF_REMOTE(_brd) (((_brd)->struct_type & LOCAL_BOARD) ? 0 : 1)
#define KLCF_NUM_COMPS(_brd) ((_brd)->brd_numcompts)
#define KLCF_MODULE_ID(_brd) ((_brd)->brd_module)
#ifdef FRUTEST
#define KLCF_NEXT(_brd) ((_brd)->brd_next ? (lboard_t *)((_brd)->brd_next): NULL)
#define KLCF_COMP(_brd, _ndx) (klinfo_t *)((_brd)->brd_compts[(_ndx)])
#define KLCF_COMP_ERROR(_brd, _comp) (_brd = _brd , (_comp)->errinfo)
#else
#define KLCF_NEXT(_brd) \
((_brd)->brd_next ? \
(lboard_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_brd)->brd_next)):\
NULL)
#define KLCF_COMP(_brd, _ndx) \
(klinfo_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), \
(_brd)->brd_compts[(_ndx)]))
#define KLCF_COMP_ERROR(_brd, _comp) \
(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo))
#endif
#define KLCF_COMP_TYPE(_comp) ((_comp)->struct_type)
#define KLCF_BRIDGE_W_ID(_comp) ((_comp)->physid) /* Widget ID */
/*
* Generic info structure. This stores common info about a
* component.
*/
typedef struct klinfo_s { /* Generic info */
unsigned char struct_type; /* type of this structure */
unsigned char struct_version; /* version of this structure */
unsigned char flags; /* Enabled, disabled etc */
unsigned char revision; /* component revision */
unsigned short diagval; /* result of diagnostics */
unsigned short diagparm; /* diagnostic parameter */
unsigned char inventory; /* previous inventory status */
nic_t nic; /* MUst be aligned properly */
unsigned char physid; /* physical id of component */
unsigned int virtid; /* virtual id as seen by system */
unsigned char widid; /* Widget id - if applicable */
nasid_t nasid; /* node number - from parent */
char pad1; /* pad out structure. */
char pad2; /* pad out structure. */
COMPONENT *arcs_compt; /* ptr to the arcs struct for ease*/
klconf_off_t errinfo; /* component specific errors */
unsigned short pad3; /* pci fields have moved over to */
unsigned short pad4; /* klbri_t */
} klinfo_t ;
#define KLCONFIG_INFO_ENABLED(_i) ((_i)->flags & KLINFO_ENABLE)
/*
* Component structures.
* Following are the currently identified components:
* CPU, HUB, MEM_BANK,
* XBOW(consists of 16 WIDGETs, each of which can be HUB or GRAPHICS or BRIDGE)
* BRIDGE, IOC3, SuperIO, SCSI, FDDI
* ROUTER
* GRAPHICS
*/
#define KLSTRUCT_UNKNOWN 0
#define KLSTRUCT_CPU 1
#define KLSTRUCT_HUB 2
#define KLSTRUCT_MEMBNK 3
#define KLSTRUCT_XBOW 4
#define KLSTRUCT_BRI 5
#define KLSTRUCT_IOC3 6
#define KLSTRUCT_PCI 7
#define KLSTRUCT_VME 8
#define KLSTRUCT_ROU 9
#define KLSTRUCT_GFX 10
#define KLSTRUCT_SCSI 11
#define KLSTRUCT_FDDI 12
#define KLSTRUCT_MIO 13
#define KLSTRUCT_DISK 14
#define KLSTRUCT_TAPE 15
#define KLSTRUCT_CDROM 16
#define KLSTRUCT_HUB_UART 17
#define KLSTRUCT_IOC3ENET 18
#define KLSTRUCT_IOC3UART 19
#define KLSTRUCT_UNUSED 20 /* XXX UNUSED */
#define KLSTRUCT_IOC3PCKM 21
#define KLSTRUCT_RAD 22
#define KLSTRUCT_HUB_TTY 23
#define KLSTRUCT_IOC3_TTY 24
/* Early Access IO proms are compatible
only with KLSTRUCT values upto 24. */
#define KLSTRUCT_FIBERCHANNEL 25
#define KLSTRUCT_MOD_SERIAL_NUM 26
#define KLSTRUCT_IOC3MS 27
#define KLSTRUCT_TPU 28
#define KLSTRUCT_GSN_A 29
#define KLSTRUCT_GSN_B 30
#define KLSTRUCT_XTHD 31
/*
* These are the indices of various components within a lboard structure.
*/
#define IP27_CPU0_INDEX 0
#define IP27_CPU1_INDEX 1
#define IP27_HUB_INDEX 2
#define IP27_MEM_INDEX 3
#define BASEIO_BRIDGE_INDEX 0
#define BASEIO_IOC3_INDEX 1
#define BASEIO_SCSI1_INDEX 2
#define BASEIO_SCSI2_INDEX 3
#define MIDPLANE_XBOW_INDEX 0
#define ROUTER_COMPONENT_INDEX 0
#define CH4SCSI_BRIDGE_INDEX 0
/* Info holders for various hardware components */
typedef u64 *pci_t;
typedef u64 *vmeb_t;
typedef u64 *vmed_t;
typedef u64 *fddi_t;
typedef u64 *scsi_t;
typedef u64 *mio_t;
typedef u64 *graphics_t;
typedef u64 *router_t;
/*
* The port info in ip27_cfg area translates to a lboart_t in the
* KLCONFIG area. But since KLCONFIG does not use pointers, lboart_t
* is stored in terms of a nasid and a offset from start of KLCONFIG
* area on that nasid.
*/
typedef struct klport_s {
nasid_t port_nasid;
unsigned char port_flag;
klconf_off_t port_offset;
} klport_t;
#if 0
/*
* This is very similar to the klport_s but instead of having a componant
* offset it has a board offset.
*/
typedef struct klxbow_port_s {
nasid_t port_nasid;
unsigned char port_flag;
klconf_off_t board_offset;
} klxbow_port_t;
#endif
typedef struct klcpu_s { /* CPU */
klinfo_t cpu_info;
unsigned short cpu_prid; /* Processor PRID value */
unsigned short cpu_fpirr; /* FPU IRR value */
unsigned short cpu_speed; /* Speed in MHZ */
unsigned short cpu_scachesz; /* secondary cache size in MB */
unsigned short cpu_scachespeed;/* secondary cache speed in MHz */
} klcpu_t ;
#define CPU_STRUCT_VERSION 2
typedef struct klhub_s { /* HUB */
klinfo_t hub_info;
uint hub_flags; /* PCFG_HUB_xxx flags */
klport_t hub_port; /* hub is connected to this */
nic_t hub_box_nic; /* nic of containing box */
klconf_off_t hub_mfg_nic; /* MFG NIC string */
u64 hub_speed; /* Speed of hub in HZ */
} klhub_t ;
typedef struct klhub_uart_s { /* HUB */
klinfo_t hubuart_info;
uint hubuart_flags; /* PCFG_HUB_xxx flags */
nic_t hubuart_box_nic; /* nic of containing box */
} klhub_uart_t ;
#define MEMORY_STRUCT_VERSION 2
typedef struct klmembnk_s { /* MEMORY BANK */
klinfo_t membnk_info;
short membnk_memsz; /* Total memory in megabytes */
short membnk_dimm_select; /* bank to physical addr mapping*/
short membnk_bnksz[MD_MEM_BANKS]; /* Memory bank sizes */
short membnk_attr;
} klmembnk_t ;
#define KLCONFIG_MEMBNK_SIZE(_info, _bank) \
((_info)->membnk_bnksz[(_bank)])
#define MEMBNK_PREMIUM 1
#define KLCONFIG_MEMBNK_PREMIUM(_info, _bank) \
((_info)->membnk_attr & (MEMBNK_PREMIUM << (_bank)))
#define MAX_SERIAL_NUM_SIZE 10
typedef struct klmod_serial_num_s {
klinfo_t snum_info;
union {
char snum_str[MAX_SERIAL_NUM_SIZE];
unsigned long long snum_int;
} snum;
} klmod_serial_num_t;
/* Macros needed to access serial number structure in lboard_t.
Hard coded values are necessary since we cannot treat
serial number struct as a component without losing compatibility
between prom versions. */
#define GET_SNUM_COMP(_l) ((klmod_serial_num_t *)\
KLCF_COMP(_l, _l->brd_numcompts))
#define MAX_XBOW_LINKS 16
typedef struct klxbow_s { /* XBOW */
klinfo_t xbow_info ;
klport_t xbow_port_info[MAX_XBOW_LINKS] ; /* Module number */
int xbow_master_hub_link;
/* type of brd connected+component struct ptr+flags */
} klxbow_t ;
#define MAX_PCI_SLOTS 8
typedef struct klpci_device_s {
s32 pci_device_id; /* 32 bits of vendor/device ID. */
s32 pci_device_pad; /* 32 bits of padding. */
} klpci_device_t;
#define BRIDGE_STRUCT_VERSION 2
typedef struct klbri_s { /* BRIDGE */
klinfo_t bri_info ;
unsigned char bri_eprominfo ; /* IO6prom connected to bridge */
unsigned char bri_bustype ; /* PCI/VME BUS bridge/GIO */
pci_t pci_specific ; /* PCI Board config info */
klpci_device_t bri_devices[MAX_PCI_DEVS] ; /* PCI IDs */
klconf_off_t bri_mfg_nic ;
} klbri_t ;
#define MAX_IOC3_TTY 2
typedef struct klioc3_s { /* IOC3 */
klinfo_t ioc3_info ;
unsigned char ioc3_ssram ; /* Info about ssram */
unsigned char ioc3_nvram ; /* Info about nvram */
klinfo_t ioc3_superio ; /* Info about superio */
klconf_off_t ioc3_tty_off ;
klinfo_t ioc3_enet ;
klconf_off_t ioc3_enet_off ;
klconf_off_t ioc3_kbd_off ;
} klioc3_t ;
#define MAX_VME_SLOTS 8
typedef struct klvmeb_s { /* VME BRIDGE - PCI CTLR */
klinfo_t vmeb_info ;
vmeb_t vmeb_specific ;
klconf_off_t vmeb_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */
} klvmeb_t ;
typedef struct klvmed_s { /* VME DEVICE - VME BOARD */
klinfo_t vmed_info ;
vmed_t vmed_specific ;
klconf_off_t vmed_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */
} klvmed_t ;
#define ROUTER_VECTOR_VERS 2
/* XXX - Don't we need the number of ports here?!? */
typedef struct klrou_s { /* ROUTER */
klinfo_t rou_info ;
uint rou_flags ; /* PCFG_ROUTER_xxx flags */
nic_t rou_box_nic ; /* nic of the containing module */
klport_t rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */
klconf_off_t rou_mfg_nic ; /* MFG NIC string */
u64 rou_vector; /* vector from master node */
} klrou_t ;
/*
* Graphics Controller/Device
*
* (IP27/IO6) Prom versions 6.13 (and 6.5.1 kernels) and earlier
* used a couple different structures to store graphics information.
* For compatibility reasons, the newer data structure preserves some
* of the layout so that fields that are used in the old versions remain
* in the same place (with the same info). Determination of what version
* of this structure we have is done by checking the cookie field.
*/
#define KLGFX_COOKIE 0x0c0de000
typedef struct klgfx_s { /* GRAPHICS Device */
klinfo_t gfx_info;
klconf_off_t old_gndevs; /* for compatibility with older proms */
klconf_off_t old_gdoff0; /* for compatibility with older proms */
uint cookie; /* for compatibility with older proms */
uint moduleslot;
struct klgfx_s *gfx_next_pipe;
graphics_t gfx_specific;
klconf_off_t pad0; /* for compatibility with older proms */
klconf_off_t gfx_mfg_nic;
} klgfx_t;
typedef struct klxthd_s {
klinfo_t xthd_info ;
klconf_off_t xthd_mfg_nic ; /* MFG NIC string */
} klxthd_t ;
typedef struct kltpu_s { /* TPU board */
klinfo_t tpu_info ;
klconf_off_t tpu_mfg_nic ; /* MFG NIC string */
} kltpu_t ;
typedef struct klgsn_s { /* GSN board */
klinfo_t gsn_info ;
klconf_off_t gsn_mfg_nic ; /* MFG NIC string */
} klgsn_t ;
#define MAX_SCSI_DEVS 16
/*
* NOTE: THis is the max sized kl* structure and is used in klmalloc.c
* to allocate space of type COMPONENT. Make sure that if the size of
* any other component struct becomes more than this, then redefine
* that as the size to be klmalloced.
*/
typedef struct klscsi_s { /* SCSI Controller */
klinfo_t scsi_info ;
scsi_t scsi_specific ;
unsigned char scsi_numdevs ;
klconf_off_t scsi_devinfo[MAX_SCSI_DEVS] ;
} klscsi_t ;
typedef struct klscdev_s { /* SCSI device */
klinfo_t scdev_info ;
struct scsidisk_data *scdev_cfg ; /* driver fills up this */
} klscdev_t ;
typedef struct klttydev_s { /* TTY device */
klinfo_t ttydev_info ;
struct terminal_data *ttydev_cfg ; /* driver fills up this */
} klttydev_t ;
typedef struct klenetdev_s { /* ENET device */
klinfo_t enetdev_info ;
struct net_data *enetdev_cfg ; /* driver fills up this */
} klenetdev_t ;
typedef struct klkbddev_s { /* KBD device */
klinfo_t kbddev_info ;
struct keyboard_data *kbddev_cfg ; /* driver fills up this */
} klkbddev_t ;
typedef struct klmsdev_s { /* mouse device */
klinfo_t msdev_info ;
void *msdev_cfg ;
} klmsdev_t ;
#define MAX_FDDI_DEVS 10 /* XXX Is this true */
typedef struct klfddi_s { /* FDDI */
klinfo_t fddi_info ;
fddi_t fddi_specific ;
klconf_off_t fddi_devinfo[MAX_FDDI_DEVS] ;
} klfddi_t ;
typedef struct klmio_s { /* MIO */
klinfo_t mio_info ;
mio_t mio_specific ;
} klmio_t ;
typedef union klcomp_s {
klcpu_t kc_cpu;
klhub_t kc_hub;
klmembnk_t kc_mem;
klxbow_t kc_xbow;
klbri_t kc_bri;
klioc3_t kc_ioc3;
klvmeb_t kc_vmeb;
klvmed_t kc_vmed;
klrou_t kc_rou;
klgfx_t kc_gfx;
klscsi_t kc_scsi;
klscdev_t kc_scsi_dev;
klfddi_t kc_fddi;
klmio_t kc_mio;
klmod_serial_num_t kc_snum ;
} klcomp_t;
typedef union kldev_s { /* for device structure allocation */
klscdev_t kc_scsi_dev ;
klttydev_t kc_tty_dev ;
klenetdev_t kc_enet_dev ;
klkbddev_t kc_kbd_dev ;
} kldev_t ;
/* Data structure interface routines. TBD */
/* Include launch info in this file itself? TBD */
/*
* TBD - Can the ARCS and device driver related info also be included in the
* KLCONFIG area. On the IO4PROM, prom device driver info is part of cfgnode_t
* structure, viz private to the IO4prom.
*/
/*
* TBD - Allocation issues.
*
* Do we need to Mark off sepatate heaps for lboard_t, rboard_t, component,
* errinfo and allocate from them, or have a single heap and allocate all
* structures from it. Debug is easier in the former method since we can
* dump all similar structs in one command, but there will be lots of holes,
* in memory and max limits are needed for number of structures.
* Another way to make it organized, is to have a union of all components
* and allocate a aligned chunk of memory greater than the biggest
* component.
*/
typedef union {
lboard_t *lbinfo ;
} biptr_t ;
#define BRI_PER_XBOW 6
#define PCI_PER_BRI 8
#define DEV_PER_PCI 16
/* Virtual dipswitch values (starting from switch "7"): */
#define VDS_NOGFX 0x8000 /* Don't enable gfx and autoboot */
#define VDS_NOMP 0x100 /* Don't start slave processors */
#define VDS_MANUMODE 0x80 /* Manufacturing mode */
#define VDS_NOARB 0x40 /* No bootmaster arbitration */
#define VDS_PODMODE 0x20 /* Go straight to POD mode */
#define VDS_NO_DIAGS 0x10 /* Don't run any diags after BM arb */
#define VDS_DEFAULTS 0x08 /* Use default environment values */
#define VDS_NOMEMCLEAR 0x04 /* Don't run mem cfg code */
#define VDS_2ND_IO4 0x02 /* Boot from the second IO4 */
#define VDS_DEBUG_PROM 0x01 /* Print PROM debugging messages */
/* external declarations of Linux kernel functions. */
extern lboard_t *find_lboard(lboard_t *start, unsigned char type);
extern klinfo_t *find_component(lboard_t *brd, klinfo_t *kli, unsigned char type);
extern klinfo_t *find_first_component(lboard_t *brd, unsigned char type);
extern klcpu_t *nasid_slice_to_cpuinfo(nasid_t, int);
extern lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_class);
#if defined(CONFIG_SGI_IO)
extern xwidgetnum_t nodevertex_widgetnum_get(vertex_hdl_t node_vtx);
extern vertex_hdl_t nodevertex_xbow_peer_get(vertex_hdl_t node_vtx);
extern lboard_t *find_gfxpipe(int pipenum);
extern void setup_gfxpipe_link(vertex_hdl_t vhdl,int pipenum);
extern lboard_t *find_lboard_module_class(lboard_t *start, moduleid_t mod,
unsigned char brd_class);
extern lboard_t *find_nic_lboard(lboard_t *, nic_t);
extern lboard_t *find_nic_type_lboard(nasid_t, unsigned char, nic_t);
extern lboard_t *find_lboard_modslot(lboard_t *start, moduleid_t mod, slotid_t slot);
extern lboard_t *find_lboard_module(lboard_t *start, moduleid_t mod);
extern lboard_t *get_board_name(nasid_t nasid, moduleid_t mod, slotid_t slot, char *name);
extern int config_find_nic_router(nasid_t, nic_t, lboard_t **, klrou_t**);
extern int config_find_nic_hub(nasid_t, nic_t, lboard_t **, klhub_t**);
extern int config_find_xbow(nasid_t, lboard_t **, klxbow_t**);
extern klcpu_t *get_cpuinfo(cpuid_t cpu);
extern int update_klcfg_cpuinfo(nasid_t, int);
extern void board_to_path(lboard_t *brd, char *path);
extern moduleid_t get_module_id(nasid_t nasid);
extern void nic_name_convert(char *old_name, char *new_name);
extern int module_brds(nasid_t nasid, lboard_t **module_brds, int n);
extern lboard_t *brd_from_key(ulong_t key);
extern void device_component_canonical_name_get(lboard_t *,klinfo_t *,
char *);
extern int board_serial_number_get(lboard_t *,char *);
extern int is_master_baseio(nasid_t,moduleid_t,slotid_t);
extern nasid_t get_actual_nasid(lboard_t *brd) ;
extern net_vec_t klcfg_discover_route(lboard_t *, lboard_t *, int);
#else /* CONFIG_SGI_IO */
extern klcpu_t *sn_get_cpuinfo(cpuid_t cpu);
#endif /* CONFIG_SGI_IO */
#endif /* _ASM_SN_KLCONFIG_H */
include/asm-mips/sn/kldir.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Derived from IRIX <sys/SN/kldir.h>, revision 1.21.
*
* Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 1999, 2000 by Ralf Baechle
*/
#ifndef _ASM_SN_KLDIR_H
#define _ASM_SN_KLDIR_H
#include <linux/config.h>
#if defined(CONFIG_SGI_IO)
#include <asm/hack.h>
#endif
/*
* The kldir memory area resides at a fixed place in each node's memory and
* provides pointers to most other IP27 memory areas. This allows us to
* resize and/or relocate memory areas at a later time without breaking all
* firmware and kernels that use them. Indices in the array are
* permanently dedicated to areas listed below. Some memory areas (marked
* below) reside at a permanently fixed location, but are included in the
* directory for completeness.
*/
#define KLDIR_MAGIC 0x434d5f53505f5357
/*
* The upper portion of the memory map applies during boot
* only and is overwritten by IRIX/SYMMON.
*
* MEMORY MAP PER NODE
*
* 0x2000000 (32M) +-----------------------------------------+
* | IO6 BUFFERS FOR FLASH ENET IOC3 |
* 0x1F80000 (31.5M) +-----------------------------------------+
* | IO6 TEXT/DATA/BSS/stack |
* 0x1C00000 (30M) +-----------------------------------------+
* | IO6 PROM DEBUG TEXT/DATA/BSS/stack |
* 0x0800000 (28M) +-----------------------------------------+
* | IP27 PROM TEXT/DATA/BSS/stack |
* 0x1B00000 (27M) +-----------------------------------------+
* | IP27 CFG |
* 0x1A00000 (26M) +-----------------------------------------+
* | Graphics PROM |
* 0x1800000 (24M) +-----------------------------------------+
* | 3rd Party PROM drivers |
* 0x1600000 (22M) +-----------------------------------------+
* | |
* | Free |
* | |
* +-----------------------------------------+
* | UNIX DEBUG Version |
* 0x190000 (2M--) +-----------------------------------------+
* | SYMMON |
* | (For UNIX Debug only) |
* 0x34000 (208K) +-----------------------------------------+
* | SYMMON STACK [NUM_CPU_PER_NODE] |
* | (For UNIX Debug only) |
* 0x25000 (148K) +-----------------------------------------+
* | KLCONFIG - II (temp) |
* | |
* | ---------------------------- |
* | |
* | UNIX NON-DEBUG Version |
* 0x19000 (100K) +-----------------------------------------+
*
*
* The lower portion of the memory map contains information that is
* permanent and is used by the IP27PROM, IO6PROM and IRIX.
*
* 0x19000 (100K) +-----------------------------------------+
* | |
* | PI Error Spools (32K) |
* | |
* 0x12000 (72K) +-----------------------------------------+
* | Unused |
* 0x11c00 (71K) +-----------------------------------------+
* | CPU 1 NMI Eframe area |
* 0x11a00 (70.5K) +-----------------------------------------+
* | CPU 0 NMI Eframe area |
* 0x11800 (70K) +-----------------------------------------+
* | CPU 1 NMI Register save area |
* 0x11600 (69.5K) +-----------------------------------------+
* | CPU 0 NMI Register save area |
* 0x11400 (69K) +-----------------------------------------+
* | GDA (1k) |
* 0x11000 (68K) +-----------------------------------------+
* | Early cache Exception stack |
* | and/or |
* | kernel/io6prom nmi registers |
* 0x10800 (66k) +-----------------------------------------+
* | cache error eframe |
* 0x10400 (65K) +-----------------------------------------+
* | Exception Handlers (UALIAS copy) |
* 0x10000 (64K) +-----------------------------------------+
* | |
* | |
* | KLCONFIG - I (permanent) (48K) |
* | |
* | |
* | |
* 0x4000 (16K) +-----------------------------------------+
* | NMI Handler (Protected Page) |
* 0x3000 (12K) +-----------------------------------------+
* | ARCS PVECTORS (master node only) |
* 0x2c00 (11K) +-----------------------------------------+
* | ARCS TVECTORS (master node only) |
* 0x2800 (10K) +-----------------------------------------+
* | LAUNCH [NUM_CPU] |
* 0x2400 (9K) +-----------------------------------------+
* | Low memory directory (KLDIR) |
* 0x2000 (8K) +-----------------------------------------+
* | ARCS SPB (1K) |
* 0x1000 (4K) +-----------------------------------------+
* | Early cache Exception stack |
* | and/or |
* | kernel/io6prom nmi registers |
* 0x800 (2k) +-----------------------------------------+
* | cache error eframe |
* 0x400 (1K) +-----------------------------------------+
* | Exception Handlers |
* 0x0 (0K) +-----------------------------------------+
*/
#ifdef __ASSEMBLY__
#define KLDIR_OFF_MAGIC 0x00
#define KLDIR_OFF_OFFSET 0x08
#define KLDIR_OFF_POINTER 0x10
#define KLDIR_OFF_SIZE 0x18
#define KLDIR_OFF_COUNT 0x20
#define KLDIR_OFF_STRIDE 0x28
#endif /* __ASSEMBLY__ */
#if !defined(CONFIG_SGI_IO)
/*
* This is defined here because IP27_SYMMON_STK_SIZE must be at least what
* we define here. Since it's set up in the prom. We can't redefine it later
* and expect more space to be allocated. The way to find out the true size
* of the symmon stacks is to divide SYMMON_STK_SIZE by SYMMON_STK_STRIDE
* for a particular node.
*/
#define SYMMON_STACK_SIZE 0x8000
#if defined (PROM) || defined (SABLE)
/*
* These defines are prom version dependent. No code other than the IP27
* prom should attempt to use these values.
*/
#define IP27_LAUNCH_OFFSET 0x2400
#define IP27_LAUNCH_SIZE 0x400
#define IP27_LAUNCH_COUNT 2
#define IP27_LAUNCH_STRIDE 0x200
#define IP27_KLCONFIG_OFFSET 0x4000
#define IP27_KLCONFIG_SIZE 0xc000
#define IP27_KLCONFIG_COUNT 1
#define IP27_KLCONFIG_STRIDE 0
#define IP27_NMI_OFFSET 0x3000
#define IP27_NMI_SIZE 0x40
#define IP27_NMI_COUNT 2
#define IP27_NMI_STRIDE 0x40
#define IP27_PI_ERROR_OFFSET 0x12000
#define IP27_PI_ERROR_SIZE 0x4000
#define IP27_PI_ERROR_COUNT 1
#define IP27_PI_ERROR_STRIDE 0
#define IP27_SYMMON_STK_OFFSET 0x25000
#define IP27_SYMMON_STK_SIZE 0xe000
#define IP27_SYMMON_STK_COUNT 2
/* IP27_SYMMON_STK_STRIDE must be >= SYMMON_STACK_SIZE */
#define IP27_SYMMON_STK_STRIDE 0x7000
#define IP27_FREEMEM_OFFSET 0x19000
#define IP27_FREEMEM_SIZE -1
#define IP27_FREEMEM_COUNT 1
#define IP27_FREEMEM_STRIDE 0
#endif /* PROM || SABLE*/
/*
* There will be only one of these in a partition so the IO6 must set it up.
*/
#define IO6_GDA_OFFSET 0x11000
#define IO6_GDA_SIZE 0x400
#define IO6_GDA_COUNT 1
#define IO6_GDA_STRIDE 0
/*
* save area of kernel nmi regs in the prom format
*/
#define IP27_NMI_KREGS_OFFSET 0x11400
#define IP27_NMI_KREGS_CPU_SIZE 0x200
/*
* save area of kernel nmi regs in eframe format
*/
#define IP27_NMI_EFRAME_OFFSET 0x11800
#define IP27_NMI_EFRAME_SIZE 0x200
#define KLDIR_ENT_SIZE 0x40
#define KLDIR_MAX_ENTRIES (0x400 / 0x40)
#endif /* !CONFIG_SGI_IO */
#ifndef __ASSEMBLY__
typedef struct kldir_ent_s {
u64 magic; /* Indicates validity of entry */
off_t offset; /* Offset from start of node space */
#if defined(CONFIG_SGI_IO) /* FIXME */
__psunsigned_t pointer; /* Pointer to area in some cases */
#else
unsigned long pointer; /* Pointer to area in some cases */
#endif
size_t size; /* Size in bytes */
u64 count; /* Repeat count if array, 1 if not */
size_t stride; /* Stride if array, 0 if not */
char rsvd[16]; /* Pad entry to 0x40 bytes */
/* NOTE: These 16 bytes are used in the Partition KLDIR
entry to store partition info. Refer to klpart.h for this. */
} kldir_ent_t;
#endif /* !__ASSEMBLY__ */
#if defined(CONFIG_SGI_IO)
#define KLDIR_ENT_SIZE 0x40
#define KLDIR_MAX_ENTRIES (0x400 / 0x40)
/*
* The actual offsets of each memory area are machine-dependent
*/
#ifdef CONFIG_SGI_IP27
// Not yet #include <asm/sn/sn0/kldir.h>
#elif defined(CONFIG_SGI_IP35)
#include <asm/sn/sn1/kldir.h>
#else
#error "kldir.h is currently defined for IP27 and IP35 platforms only"
#endif
#endif /* CONFIG_SGI_IO */
#endif /* _ASM_SN_KLDIR_H */
include/asm-mips/sn/klkernvars.h
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/*
* File ported from IRIX to Linux by Kanoj Sarcar, 06/08/00.
* Copyright 2000 Silicon Graphics, Inc.
*/
#ifndef __ASM_SN_KLKERNVARS_H
#define __ASM_SN_KLKERNVARS_H
#define KV_MAGIC_OFFSET 0x0
#define KV_RO_NASID_OFFSET 0x4
#define KV_RW_NASID_OFFSET 0x6
#define KV_MAGIC 0x5f4b565f
#ifndef __ASSEMBLY__
#include <asm/sn/types.h>
typedef struct kern_vars_s {
int kv_magic;
nasid_t kv_ro_nasid;
nasid_t kv_rw_nasid;
unsigned long kv_ro_baseaddr;
unsigned long kv_rw_baseaddr;
} kern_vars_t;
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_SN_KLKERNVARS_H */
include/asm-mips/sn/launch.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
* Copyright (C) 2000 by Colin Ngam
*/
#ifndef _ASM_SN_LAUNCH_H
#define _ASM_SN_LAUNCH_H
#include <linux/config.h>
#include <asm/sn/types.h>
#include <asm/sn/addrs.h>
/*
* The launch data structure resides at a fixed place in each node's memory
* and is used to communicate between the master processor and the slave
* processors.
*
* The master stores launch parameters in the launch structure
* corresponding to a target processor that is in a slave loop, then sends
* an interrupt to the slave processor. The slave calls the desired
* function, then returns to the slave loop. The master may poll or wait
* for the slaves to finish.
*
* There is an array of launch structures, one per CPU on the node. One
* interrupt level is used per local CPU.
*/
#define LAUNCH_MAGIC 0xaddbead2addbead3
#ifdef CONFIG_SGI_IP27
#define LAUNCH_SIZEOF 0x100
#define LAUNCH_PADSZ 0xa0
#endif
#define LAUNCH_OFF_MAGIC 0x00 /* Struct offsets for assembly */
#define LAUNCH_OFF_BUSY 0x08
#define LAUNCH_OFF_CALL 0x10
#define LAUNCH_OFF_CALLC 0x18
#define LAUNCH_OFF_CALLPARM 0x20
#define LAUNCH_OFF_STACK 0x28
#define LAUNCH_OFF_GP 0x30
#define LAUNCH_OFF_BEVUTLB 0x38
#define LAUNCH_OFF_BEVNORMAL 0x40
#define LAUNCH_OFF_BEVECC 0x48
#define LAUNCH_STATE_DONE 0 /* Return value of LAUNCH_POLL */
#define LAUNCH_STATE_SENT 1
#define LAUNCH_STATE_RECD 2
/*
* The launch routine is called only if the complement address is correct.
*
* Before control is transferred to a routine, the complement address
* is zeroed (invalidated) to prevent an accidental call from a spurious
* interrupt.
*
* The slave_launch routine turns on the BUSY flag, and the slave loop
* clears the BUSY flag after control is returned to it.
*/
#ifndef __ASSEMBLY__
typedef int launch_state_t;
typedef void (*launch_proc_t)(u64 call_parm);
typedef struct launch_s {
volatile u64 magic; /* Magic number */
volatile u64 busy; /* Slave currently active */
volatile launch_proc_t call_addr; /* Func. for slave to call */
volatile u64 call_addr_c; /* 1's complement of call_addr*/
volatile u64 call_parm; /* Single parm passed to call*/
volatile void *stack_addr; /* Stack pointer for slave function */
volatile void *gp_addr; /* Global pointer for slave func. */
volatile char *bevutlb;/* Address of bev utlb ex handler */
volatile char *bevnormal;/*Address of bev normal ex handler */
volatile char *bevecc;/* Address of bev cache err handler */
volatile char pad[160]; /* Pad to LAUNCH_SIZEOF */
} launch_t;
/*
* PROM entry points for launch routines are determined by IPxxprom/start.s
*/
#define LAUNCH_SLAVE (*(void (*)(int nasid, int cpu, \
launch_proc_t call_addr, \
u64 call_parm, \
void *stack_addr, \
void *gp_addr)) \
IP27PROM_LAUNCHSLAVE)
#define LAUNCH_WAIT (*(void (*)(int nasid, int cpu, int timeout_msec)) \
IP27PROM_WAITSLAVE)
#define LAUNCH_POLL (*(launch_state_t (*)(int nasid, int cpu)) \
IP27PROM_POLLSLAVE)
#define LAUNCH_LOOP (*(void (*)(void)) \
IP27PROM_SLAVELOOP)
#define LAUNCH_FLASH (*(void (*)(void)) \
IP27PROM_FLASHLEDS)
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_SN_LAUNCH_H */
include/asm-mips/sn/mapped_kernel.h
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/*
* File created by Kanoj Sarcar 06/06/00.
* Copyright 2000 Silicon Graphics, Inc.
*/
#ifndef __ASM_SN_MAPPED_KERNEL_H
#define __ASM_SN_MAPPED_KERNEL_H
/*
* Note on how mapped kernels work: the text and data section is
* compiled at cksseg segment (LOADADDR = 0xc001c000), and the
* init/setup/data section gets a 16M virtual address bump in the
* ld.script file (so that tlblo0 and tlblo1 maps the sections).
* The vmlinux.64 section addresses are put in the xkseg range
* using the change-addresses makefile option. Use elfdump -of
* on IRIX to see where the sections go. The Origin loader loads
* the two sections contiguously in physical memory. The loader
* sets the entry point into kernel_entry using a xkphys address,
* but instead of using 0xa800000001160000, it uses the address
* 0xa800000000160000, which is where it physically loaded that
* code. So no jumps can be done before we have switched to using
* cksseg addresses.
*/
#include <linux/config.h>
#include <asm/addrspace.h>
#ifdef CONFIG_BUILD_ELF64
#define REP_BASE CAC_BASE
#else
#define REP_BASE CKSEG0
#endif
#ifdef CONFIG_MAPPED_KERNEL
#define MAPPED_ADDR_RO_TO_PHYS(x) (x - REP_BASE)
#define MAPPED_ADDR_RW_TO_PHYS(x) (x - REP_BASE - 16777216)
#define MAPPED_KERN_RO_PHYSBASE(n) \
(PLAT_NODE_DATA(n)->kern_vars.kv_ro_baseaddr)
#define MAPPED_KERN_RW_PHYSBASE(n) \
(PLAT_NODE_DATA(n)->kern_vars.kv_rw_baseaddr)
#define MAPPED_KERN_RO_TO_PHYS(x) \
((unsigned long)MAPPED_ADDR_RO_TO_PHYS(x) | \
MAPPED_KERN_RO_PHYSBASE(get_compact_nodeid()))
#define MAPPED_KERN_RW_TO_PHYS(x) \
((unsigned long)MAPPED_ADDR_RW_TO_PHYS(x) | \
MAPPED_KERN_RW_PHYSBASE(get_compact_nodeid()))
#else /* CONFIG_MAPPED_KERNEL */
#define MAPPED_KERN_RO_TO_PHYS(x) (x - REP_BASE)
#define MAPPED_KERN_RW_TO_PHYS(x) (x - REP_BASE)
#endif /* CONFIG_MAPPED_KERNEL */
#define MAPPED_KERN_RO_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RO_TO_PHYS(x))
#define MAPPED_KERN_RW_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RW_TO_PHYS(x))
#endif /* __ASM_SN_MAPPED_KERNEL_H */
include/asm-mips/sn/nmi.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
*/
#ifndef __ASM_SN_NMI_H
#define __ASM_SN_NMI_H
#ident "$Revision: 1.5 $"
#include <asm/sn/addrs.h>
/*
* The launch data structure resides at a fixed place in each node's memory
* and is used to communicate between the master processor and the slave
* processors.
*
* The master stores launch parameters in the launch structure
* corresponding to a target processor that is in a slave loop, then sends
* an interrupt to the slave processor. The slave calls the desired
* function, followed by an optional rendezvous function, then returns to
* the slave loop. The master does not wait for the slaves before
* returning.
*
* There is an array of launch structures, one per CPU on the node. One
* interrupt level is used per CPU.
*/
#define NMI_MAGIC 0x48414d4d455201
#define NMI_SIZEOF 0x40
#define NMI_OFF_MAGIC 0x00 /* Struct offsets for assembly */
#define NMI_OFF_FLAGS 0x08
#define NMI_OFF_CALL 0x10
#define NMI_OFF_CALLC 0x18
#define NMI_OFF_CALLPARM 0x20
#define NMI_OFF_GMASTER 0x28
/*
* The NMI routine is called only if the complement address is
* correct.
*
* Before control is transferred to a routine, the complement address
* is zeroed (invalidated) to prevent an accidental call from a spurious
* interrupt.
*
*/
#ifndef __ASSEMBLY__
typedef struct nmi_s {
volatile unsigned long magic; /* Magic number */
volatile unsigned long flags; /* Combination of flags above */
volatile void *call_addr; /* Routine for slave to call */
volatile void *call_addr_c; /* 1's complement of address */
volatile void *call_parm; /* Single parm passed to call */
volatile unsigned long gmaster; /* Flag true only on global master*/
} nmi_t;
#endif /* !__ASSEMBLY__ */
/* Following definitions are needed both in the prom & the kernel
* to identify the format of the nmi cpu register save area in the
* low memory on each node.
*/
#ifndef __ASSEMBLY__
struct reg_struct {
unsigned long gpr[32];
unsigned long sr;
unsigned long cause;
unsigned long epc;
unsigned long badva;
unsigned long error_epc;
unsigned long cache_err;
unsigned long nmi_sr;
};
#endif /* !__ASSEMBLY__ */
/* These are the assembly language offsets into the reg_struct structure */
#define R0_OFF 0x0
#define R1_OFF 0x8
#define R2_OFF 0x10
#define R3_OFF 0x18
#define R4_OFF 0x20
#define R5_OFF 0x28
#define R6_OFF 0x30
#define R7_OFF 0x38
#define R8_OFF 0x40
#define R9_OFF 0x48
#define R10_OFF 0x50
#define R11_OFF 0x58
#define R12_OFF 0x60
#define R13_OFF 0x68
#define R14_OFF 0x70
#define R15_OFF 0x78
#define R16_OFF 0x80
#define R17_OFF 0x88
#define R18_OFF 0x90
#define R19_OFF 0x98
#define R20_OFF 0xa0
#define R21_OFF 0xa8
#define R22_OFF 0xb0
#define R23_OFF 0xb8
#define R24_OFF 0xc0
#define R25_OFF 0xc8
#define R26_OFF 0xd0
#define R27_OFF 0xd8
#define R28_OFF 0xe0
#define R29_OFF 0xe8
#define R30_OFF 0xf0
#define R31_OFF 0xf8
#define SR_OFF 0x100
#define CAUSE_OFF 0x108
#define EPC_OFF 0x110
#define BADVA_OFF 0x118
#define ERROR_EPC_OFF 0x120
#define CACHE_ERR_OFF 0x128
#define NMISR_OFF 0x130
#endif /* __ASM_SN_NMI_H */
include/asm-mips/sn/sn0/addrs.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Derived from IRIX <sys/SN/SN0/addrs.h>, revision 1.126.
*
* Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
* Copyright (C) 1999 by Ralf Baechle
*/
#ifndef _ASM_SN_SN0_ADDRS_H
#define _ASM_SN_SN0_ADDRS_H
#include <linux/config.h>
/*
* SN0 (on a T5) Address map
*
* This file contains a set of definitions and macros which are used
* to reference into the major address spaces (CAC, HSPEC, IO, MSPEC,
* and UNCAC) used by the SN0 architecture. It also contains addresses
* for "major" statically locatable PROM/Kernel data structures, such as
* the partition table, the configuration data structure, etc.
* We make an implicit assumption that the processor using this file
* follows the R10K's provisions for specifying uncached attributes;
* should this change, the base registers may very well become processor-
* dependent.
*
* For more information on the address spaces, see the "Local Resources"
* chapter of the Hub specification.
*
* NOTE: This header file is included both by C and by assembler source
* files. Please bracket any language-dependent definitions
* appropriately.
*/
/*
* Some of the macros here need to be casted to appropriate types when used
* from C. They definitely must not be casted from assembly language so we
* use some new ANSI preprocessor stuff to paste these on where needed.
*/
/*
* The following couple of definitions will eventually need to be variables,
* since the amount of address space assigned to each node depends on
* whether the system is running in N-mode (more nodes with less memory)
* or M-mode (fewer nodes with more memory). We expect that it will
* be a while before we need to make this decision dynamically, though,
* so for now we just use defines bracketed by an ifdef.
*/
#ifdef CONFIG_SGI_SN0_N_MODE
#define NODE_SIZE_BITS 31
#define BWIN_SIZE_BITS 28
#define NASID_BITS 9
#define NASID_BITMASK (0x1ffLL)
#define NASID_SHFT 31
#define NASID_META_BITS 5
#define NASID_LOCAL_BITS 4
#define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
#define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
#else /* !defined(CONFIG_SGI_SN0_N_MODE), assume that M-mode is desired */
#define NODE_SIZE_BITS 32
#define BWIN_SIZE_BITS 29
#define NASID_BITMASK (0xffLL)
#define NASID_BITS 8
#define NASID_SHFT 32
#define NASID_META_BITS 4
#define NASID_LOCAL_BITS 4
#define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
#define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
#endif /* !defined(CONFIG_SGI_SN0_N_MODE) */
#define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS)
#define NASID_MASK (UINT64_CAST NASID_BITMASK << NASID_SHFT)
#define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \
NASID_SHFT) & NASID_BITMASK)
#if !defined(__ASSEMBLY__) && !defined(_STANDALONE)
#define NODE_SWIN_BASE(nasid, widget) \
((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
: RAW_NODE_SWIN_BASE(nasid, widget))
#else /* __ASSEMBLY__ || _STANDALONE */
#define NODE_SWIN_BASE(nasid, widget) \
(NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
#endif /* __ASSEMBLY__ || _STANDALONE */
/*
* The following definitions pertain to the IO special address
* space. They define the location of the big and little windows
* of any given node.
*/
#define BWIN_INDEX_BITS 3
#define BWIN_SIZE (UINT64_CAST 1 << BWIN_SIZE_BITS)
#define BWIN_SIZEMASK (BWIN_SIZE - 1)
#define BWIN_WIDGET_MASK 0x7
#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE)
#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \
(UINT64_CAST (bigwin) << BWIN_SIZE_BITS))
#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK)
#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
/*
* Verify if addr belongs to large window address of node with "nasid"
*
*
* NOTE: "addr" is expected to be XKPHYS address, and NOT physical
* address
*
*
*/
#define NODE_BWIN_ADDR(nasid, addr) \
(((addr) >= NODE_BWIN_BASE0(nasid)) && \
((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
BWIN_SIZE)))
/*
* The following define the major position-independent aliases used
* in SN0.
* CALIAS -- Varies in size, points to the first n bytes of memory
* on the reader's node.
*/
#define CALIAS_BASE CAC_BASE
#define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \
((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
#define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid)))
/* Turn on sable logging for the processors whose bits are set. */
#ifdef SABLE
#define SABLE_LOG_TRIGGER(_map) \
*((volatile hubreg_t *)(IO_BASE + 0x17ffff0)) = (_map)
#else
#define SABLE_LOG_TRIGGER(_map)
#endif /* SABLE */
#ifndef __ASSEMBLY__
#define KERN_NMI_ADDR(nasid, slice) \
TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + \
(IP27_NMI_KREGS_CPU_SIZE * (slice)))
#endif /* !__ASSEMBLY__ */
#ifdef PROM
#define MISC_PROM_BASE PHYS_TO_K0(0x01300000)
#define MISC_PROM_SIZE 0x200000
#define DIAG_BASE PHYS_TO_K0(0x01500000)
#define DIAG_SIZE 0x300000
#define ROUTE_BASE PHYS_TO_K0(0x01800000)
#define ROUTE_SIZE 0x200000
#define IP27PROM_FLASH_HDR PHYS_TO_K0(0x01300000)
#define IP27PROM_FLASH_DATA PHYS_TO_K0(0x01301000)
#define IP27PROM_CORP_MAX 32
#define IP27PROM_CORP PHYS_TO_K0(0x01800000)
#define IP27PROM_CORP_SIZE 0x10000
#define IP27PROM_CORP_STK PHYS_TO_K0(0x01810000)
#define IP27PROM_CORP_STKSIZE 0x2000
#define IP27PROM_DECOMP_BUF PHYS_TO_K0(0x01900000)
#define IP27PROM_DECOMP_SIZE 0xfff00
#define IP27PROM_BASE PHYS_TO_K0(0x01a00000)
#define IP27PROM_BASE_MAPPED (UNCAC_BASE | 0x1fc00000)
#define IP27PROM_SIZE_MAX 0x100000
#define IP27PROM_PCFG PHYS_TO_K0(0x01b00000)
#define IP27PROM_PCFG_SIZE 0xd0000
#define IP27PROM_ERRDMP PHYS_TO_K1(0x01bd0000)
#define IP27PROM_ERRDMP_SIZE 0xf000
#define IP27PROM_INIT_START PHYS_TO_K1(0x01bd0000)
#define IP27PROM_CONSOLE PHYS_TO_K1(0x01bdf000)
#define IP27PROM_CONSOLE_SIZE 0x200
#define IP27PROM_NETUART PHYS_TO_K1(0x01bdf200)
#define IP27PROM_NETUART_SIZE 0x100
#define IP27PROM_UNUSED1 PHYS_TO_K1(0x01bdf300)
#define IP27PROM_UNUSED1_SIZE 0x500
#define IP27PROM_ELSC_BASE_A PHYS_TO_K0(0x01bdf800)
#define IP27PROM_ELSC_BASE_B PHYS_TO_K0(0x01bdfc00)
#define IP27PROM_STACK_A PHYS_TO_K0(0x01be0000)
#define IP27PROM_STACK_B PHYS_TO_K0(0x01bf0000)
#define IP27PROM_STACK_SHFT 16
#define IP27PROM_STACK_SIZE (1 << IP27PROM_STACK_SHFT)
#define IP27PROM_INIT_END PHYS_TO_K0(0x01c00000)
#define SLAVESTACK_BASE PHYS_TO_K0(0x01580000)
#define SLAVESTACK_SIZE 0x40000
#define ENETBUFS_BASE PHYS_TO_K0(0x01f80000)
#define ENETBUFS_SIZE 0x20000
#define IO6PROM_BASE PHYS_TO_K0(0x01c00000)
#define IO6PROM_SIZE 0x400000
#define IO6PROM_BASE_MAPPED (UNCAC_BASE | 0x11c00000)
#define IO6DPROM_BASE PHYS_TO_K0(0x01c00000)
#define IO6DPROM_SIZE 0x200000
#define NODEBUGUNIX_ADDR PHYS_TO_K0(0x00019000)
#define DEBUGUNIX_ADDR PHYS_TO_K0(0x00100000)
#define IP27PROM_INT_LAUNCH 10 /* and 11 */
#define IP27PROM_INT_NETUART 12 /* through 17 */
#endif /* PROM */
/*
* needed by symmon so it needs to be outside #if PROM
*/
#define IP27PROM_ELSC_SHFT 10
#define IP27PROM_ELSC_SIZE (1 << IP27PROM_ELSC_SHFT)
/*
* This address is used by IO6PROM to build MemoryDescriptors of
* free memory. This address is important since unix gets loaded
* at this address, and this memory has to be FREE if unix is to
* be loaded.
*/
#define FREEMEM_BASE PHYS_TO_K0(0x2000000)
#define IO6PROM_STACK_SHFT 14 /* stack per cpu */
#define IO6PROM_STACK_SIZE (1 << IO6PROM_STACK_SHFT)
/*
* IP27 PROM vectors
*/
#define IP27PROM_ENTRY PHYS_TO_COMPATK1(0x1fc00000)
#define IP27PROM_RESTART PHYS_TO_COMPATK1(0x1fc00008)
#define IP27PROM_SLAVELOOP PHYS_TO_COMPATK1(0x1fc00010)
#define IP27PROM_PODMODE PHYS_TO_COMPATK1(0x1fc00018)
#define IP27PROM_IOC3UARTPOD PHYS_TO_COMPATK1(0x1fc00020)
#define IP27PROM_FLASHLEDS PHYS_TO_COMPATK1(0x1fc00028)
#define IP27PROM_REPOD PHYS_TO_COMPATK1(0x1fc00030)
#define IP27PROM_LAUNCHSLAVE PHYS_TO_COMPATK1(0x1fc00038)
#define IP27PROM_WAITSLAVE PHYS_TO_COMPATK1(0x1fc00040)
#define IP27PROM_POLLSLAVE PHYS_TO_COMPATK1(0x1fc00048)
#define KL_UART_BASE LOCAL_HUB_ADDR(MD_UREG0_0) /* base of UART regs */
#define KL_UART_CMD LOCAL_HUB_ADDR(MD_UREG0_0) /* UART command reg */
#define KL_UART_DATA LOCAL_HUB_ADDR(MD_UREG0_1) /* UART data reg */
#define KL_I2C_REG MD_UREG0_0 /* I2C reg */
#ifndef __ASSEMBLY__
/* Address 0x400 to 0x1000 ualias points to cache error eframe + misc
* CACHE_ERR_SP_PTR could either contain an address to the stack, or
* the stack could start at CACHE_ERR_SP_PTR
*/
#if defined (HUB_ERR_STS_WAR)
#define CACHE_ERR_EFRAME 0x480
#else /* HUB_ERR_STS_WAR */
#define CACHE_ERR_EFRAME 0x400
#endif /* HUB_ERR_STS_WAR */
#define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME + EF_SIZE)
#define CACHE_ERR_SP_PTR (0x1000 - 32) /* why -32? TBD */
#define CACHE_ERR_IBASE_PTR (0x1000 - 40)
#define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16)
#define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)
#endif /* !__ASSEMBLY__ */
#define _ARCSPROM
#ifdef _STANDALONE
/*
* The PROM needs to pass the device base address and the
* device pci cfg space address to the device drivers during
* install. The COMPONENT->Key field is used for this purpose.
* Macros needed by SN0 device drivers to convert the
* COMPONENT->Key field to the respective base address.
* Key field looks as follows:
*
* +----------------------------------------------------+
* |devnasid | widget |pciid |hubwidid|hstnasid | adap |
* | 2 | 1 | 1 | 1 | 2 | 1 |
* +----------------------------------------------------+
* | | | | | | |
* 64 48 40 32 24 8 0
*
* These are used by standalone drivers till the io infrastructure
* is in place.
*/
#ifndef __ASSEMBLY__
#define uchar unsigned char
#define KEY_DEVNASID_SHFT 48
#define KEY_WIDID_SHFT 40
#define KEY_PCIID_SHFT 32
#define KEY_HUBWID_SHFT 24
#define KEY_HSTNASID_SHFT 8
#define MK_SN0_KEY(nasid, widid, pciid) \
((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\
((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\
((__psunsigned_t)pciid) << KEY_PCIID_SHFT)
#define ADD_HUBWID_KEY(key,hubwid)\
(key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT))
#define ADD_HSTNASID_KEY(key,hstnasid)\
(key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT))
#define GET_DEVNASID_FROM_KEY(key) ((short)(key >> KEY_DEVNASID_SHFT))
#define GET_WIDID_FROM_KEY(key) ((uchar)(key >> KEY_WIDID_SHFT))
#define GET_PCIID_FROM_KEY(key) ((uchar)(key >> KEY_PCIID_SHFT))
#define GET_HUBWID_FROM_KEY(key) ((uchar)(key >> KEY_HUBWID_SHFT))
#define GET_HSTNASID_FROM_KEY(key) ((short)(key >> KEY_HSTNASID_SHFT))
#define PCI_64_TARGID_SHFT 60
#define GET_PCIBASE_FROM_KEY(key) (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
GET_WIDID_FROM_KEY(key))\
| BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key)))
#define GET_PCICFGBASE_FROM_KEY(key) \
(NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
GET_WIDID_FROM_KEY(key))\
| BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key)))
#define GET_WIDBASE_FROM_KEY(key) \
(NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
GET_WIDID_FROM_KEY(key)))
#define PUT_INSTALL_STATUS(c,s) c->Revision = s
#define GET_INSTALL_STATUS(c) c->Revision
#endif /* !__ASSEMBLY__ */
#endif /* _STANDALONE */
#if defined (HUB_ERR_STS_WAR)
#define ERR_STS_WAR_REGISTER IIO_IIBUSERR
#define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR)
#define ERR_STS_WAR_PHYSADDR TO_PHYS((__psunsigned_t)ERR_STS_WAR_ADDR)
/* Used to match addr in error reg. */
#define OLD_ERR_STS_WAR_OFFSET ((MD_MEM_BANKS * MD_BANK_SIZE) - 0x100)
#endif /* HUB_ERR_STS_WAR */
#endif /* _ASM_SN_SN0_ADDRS_H */
include/asm-mips/sn/sn0/arch.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* SGI IP27 specific setup.
*
* Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
* Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
*/
#ifndef _ASM_SN_SN0_ARCH_H
#define _ASM_SN_SN0_ARCH_H
#include <linux/config.h>
#ifndef SABLE
#ifndef SN0XXL /* 128 cpu SMP max */
/*
* This is the maximum number of nodes that can be part of a kernel.
* Effectively, it's the maximum number of compact node ids (cnodeid_t).
*/
#define MAX_COMPACT_NODES 64
/*
* MAXCPUS refers to the maximum number of CPUs in a single kernel.
* This is not necessarily the same as MAXNODES * CPUS_PER_NODE
*/
#define MAXCPUS 128
#else /* SN0XXL system */
#define MAX_COMPACT_NODES 128
#define MAXCPUS 256
#endif /* SN0XXL */
/*
* This is the maximum number of NASIDS that can be present in a system.
* (Highest NASID plus one.)
*/
#define MAX_NASIDS 256
/*
* MAX_REGIONS refers to the maximum number of hardware partitioned regions.
*/
#define MAX_REGIONS 64
#define MAX_NONPREMIUM_REGIONS 16
#define MAX_PREMIUM_REGIONS MAX_REGIONS
/*
* MAX_PARITIONS refers to the maximum number of logically defined
* partitions the system can support.
*/
#define MAX_PARTITIONS MAX_REGIONS
#else
#define MAX_COMPACT_NODES 4
#define MAX_NASIDS 4
#define MAXCPUS 8
#endif
#define NASID_MASK_BYTES ((MAX_NASIDS + 7) / 8)
/*
* Slot constants for SN0
*/
#ifdef CONFIG_SGI_SN0_N_MODE
#define MAX_MEM_SLOTS 16 /* max slots per node */
#else /* !CONFIG_SGI_SN0_N_MODE, assume M_MODE */
#define MAX_MEM_SLOTS 32 /* max slots per node */
#endif /* defined(N_MODE) */
#if SABLE_RTL
#define SLOT_SHIFT (28)
#define SLOT_MIN_MEM_SIZE (16*1024*1024)
#else
#define SLOT_SHIFT (27)
#define SLOT_MIN_MEM_SIZE (32*1024*1024)
#endif
#define CPUS_PER_NODE 2 /* CPUs on a single hub */
#define CPUS_PER_NODE_SHFT 1 /* Bits to shift in the node number */
#define CPUS_PER_SUBNODE 2 /* CPUs on a single hub PI */
#endif /* _ASM_SN_SN0_ARCH_H */
include/asm-mips/sn/sn0/hub.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
* Copyright (C) 1999 by Ralf Baechle
*/
#ifndef _ASM_SN_SN0_HUB_H
#define _ASM_SN_SN0_HUB_H
/* The secret password; used to release protection */
#define HUB_PASSWORD 0x53474972756c6573ull
#define CHIPID_HUB 0
#define CHIPID_ROUTER 1
#define HUB_REV_1_0 1
#define HUB_REV_2_0 2
#define HUB_REV_2_1 3
#define HUB_REV_2_2 4
#define HUB_REV_2_3 5
#define HUB_REV_2_4 6
#define MAX_HUB_PATH 80
#include <asm/sn/sn0/addrs.h>
#include <asm/sn/sn0/hubpi.h>
#include <asm/sn/sn0/hubmd.h>
#include <asm/sn/sn0/hubio.h>
#include <asm/sn/sn0/hubni.h>
//#include <asm/sn/sn0/hubcore.h>
#ifdef SABLE
#define IP27_NO_HUBUART_INT 1
#endif
/* Translation of uncached attributes */
#define UATTR_HSPEC 0
#define UATTR_IO 1
#define UATTR_MSPEC 2
#define UATTR_UNCAC 3
#endif /* _ASM_SN_SN0_HUB_H */
include/asm-mips/sn/sn0/hubio.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Derived from IRIX <sys/SN/SN0/hubio.h>, Revision 1.80.
*
* Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
* Copyright (C) 1999 by Ralf Baechle
*/
#ifndef _ASM_SGI_SN_SN0_HUBIO_H
#define _ASM_SGI_SN_SN0_HUBIO_H
/*
* Hub I/O interface registers
*
* All registers in this file are subject to change until Hub chip tapeout.
* In general, the longer software name should be used when available.
*/
/*
* Slightly friendlier names for some common registers.
* The hardware definitions follow.
*/
#define IIO_WIDGET IIO_WID /* Widget identification */
#define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */
#define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */
#define IIO_WIDGET_TOUT IIO_WRTO /* Widget request timeout */
#define IIO_WIDGET_FLUSH IIO_WTFR /* Widget target flush */
#define IIO_PROTECT IIO_ILAPR /* IO interface protection */
#define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */
#define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */
#define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */
#define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */
#define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */
#define IIO_LLP_LOG IIO_ILLR /* LLP log */
#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/
#define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */
#define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */
#define IIO_BTE_CRB_CNT IIO_IBCN /* IO BTE CRB count */
#define IIO_LLP_CSR_IS_UP 0x00002000
#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000
#define IIO_LLP_CSR_LLP_STAT_SHFT 12
/* key to IIO_PROTECT_OVRRD */
#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */
/* BTE register names */
#define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */
#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */
#define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */
#define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */
#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */
#define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */
#define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */
#define IIO_BTE_OFF_1 IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */
/* BTE register offsets from base */
#define BTEOFF_STAT 0
#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
#define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
#define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
/*
* The following definitions use the names defined in the IO interface
* document for ease of reference. When possible, software should
* generally use the longer but clearer names defined above.
*/
#define IIO_BASE 0x400000
#define IIO_BASE_BTE0 0x410000
#define IIO_BASE_BTE1 0x420000
#define IIO_BASE_PERF 0x430000
#define IIO_PERF_CNT 0x430008
#define IO_PERF_SETS 32
#define IIO_WID 0x400000 /* Widget identification */
#define IIO_WSTAT 0x400008 /* Widget status */
#define IIO_WCR 0x400020 /* Widget control */
#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */
#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */
#define IIO_WSTAT_TXRETRY_MASK (0x7F)
#define IIO_WSTAT_TXRETRY_SHFT (16)
#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
IIO_WSTAT_TXRETRY_MASK)
#define IIO_ILAPR 0x400100 /* Local Access Protection */
#define IIO_ILAPO 0x400108 /* Protection override */
#define IIO_IOWA 0x400110 /* outbound widget access */
#define IIO_IIWA 0x400118 /* inbound widget access */
#define IIO_IIDEM 0x400120 /* Inbound Device Error Mask */
#define IIO_ILCSR 0x400128 /* LLP control and status */
#define IIO_ILLR 0x400130 /* LLP Log */
#define IIO_IIDSR 0x400138 /* Interrupt destination */
#define IIO_IIBUSERR 0x1400208 /* Reads here cause a bus error. */
/* IO Interrupt Destination Register */
#define IIO_IIDSR_SENT_SHIFT 28
#define IIO_IIDSR_SENT_MASK 0x10000000
#define IIO_IIDSR_ENB_SHIFT 24
#define IIO_IIDSR_ENB_MASK 0x01000000
#define IIO_IIDSR_NODE_SHIFT 8
#define IIO_IIDSR_NODE_MASK 0x0000ff00
#define IIO_IIDSR_LVL_SHIFT 0
#define IIO_IIDSR_LVL_MASK 0x0000003f
/* GFX Flow Control Node/Widget Register */
#define IIO_IGFX_0 0x400140 /* gfx node/widget register 0 */
#define IIO_IGFX_1 0x400148 /* gfx node/widget register 1 */
#define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */
#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
#define IIO_IGFX_W_NUM_SHIFT 0
#define IIO_IGFX_N_NUM_BITS 9 /* size of node num field */
#define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1)
#define IIO_IGFX_N_NUM_SHIFT 4
#define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */
#define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1)
#define IIO_IGFX_P_NUM_SHIFT 16
#define IIO_IGFX_VLD_BITS 1 /* size of valid field */
#define IIO_IGFX_VLD_MASK ((1<<IIO_IGFX_VLD_BITS)-1)
#define IIO_IGFX_VLD_SHIFT 20
#define IIO_IGFX_INIT(widget, node, cpu, valid) (\
(((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \
(((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \
(((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) | \
(((valid) & IIO_IGFX_VLD_MASK) << IIO_IGFX_VLD_SHIFT) )
/* Scratch registers (not all bits available) */
#define IIO_SCRATCH_REG0 0x400150
#define IIO_SCRATCH_REG1 0x400158
#define IIO_SCRATCH_MASK 0x0000000f00f11fff
#define IIO_SCRATCH_BIT0_0 0x0000000800000000
#define IIO_SCRATCH_BIT0_1 0x0000000400000000
#define IIO_SCRATCH_BIT0_2 0x0000000200000000
#define IIO_SCRATCH_BIT0_3 0x0000000100000000
#define IIO_SCRATCH_BIT0_4 0x0000000000800000
#define IIO_SCRATCH_BIT0_5 0x0000000000400000
#define IIO_SCRATCH_BIT0_6 0x0000000000200000
#define IIO_SCRATCH_BIT0_7 0x0000000000100000
#define IIO_SCRATCH_BIT0_8 0x0000000000010000
#define IIO_SCRATCH_BIT0_9 0x0000000000001000
#define IIO_SCRATCH_BIT0_R 0x0000000000000fff
/* IO Translation Table Entries */
#define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */
/* Hw manuals number them 1..7! */
/*
* As a permanent workaround for a bug in the PI side of the hub, we've
* redefined big window 7 as small window 0.
*/
#define HUB_NUM_BIG_WINDOW IIO_NUM_ITTES - 1
/*
* Use the top big window as a surrogate for the first small window
*/
#define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW
#define ILCSR_WARM_RESET 0x100
/*
* The IO LLP control status register and widget control register
*/
#ifndef __ASSEMBLY__
typedef union hubii_wid_u {
u64 wid_reg_value;
struct {
u64 wid_rsvd: 32, /* unused */
wid_rev_num: 4, /* revision number */
wid_part_num: 16, /* the widget type: hub=c101 */
wid_mfg_num: 11, /* Manufacturer id (IBM) */
wid_rsvd1: 1; /* Reserved */
} wid_fields_s;
} hubii_wid_t;
typedef union hubii_wcr_u {
u64 wcr_reg_value;
struct {
u64 wcr_rsvd: 41, /* unused */
wcr_e_thresh: 5, /* elasticity threshold */
wcr_dir_con: 1, /* widget direct connect */
wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */
wcr_xbar_crd: 3, /* LLP crossbar credit */
wcr_rsvd1: 8, /* Reserved */
wcr_tag_mode: 1, /* Tag mode */
wcr_widget_id: 4; /* LLP crossbar credit */
} wcr_fields_s;
} hubii_wcr_t;
#define iwcr_dir_con wcr_fields_s.wcr_dir_con
typedef union hubii_wstat_u {
u64 reg_value;
struct {
u64 rsvd1: 31,
crazy: 1, /* Crazy bit */
rsvd2: 8,
llp_tx_cnt: 8, /* LLP Xmit retry counter */
rsvd3: 6,
tx_max_rtry: 1, /* LLP Retry Timeout Signal */
rsvd4: 2,
xt_tail_to: 1, /* Xtalk Tail Timeout */
xt_crd_to: 1, /* Xtalk Credit Timeout */
pending: 4; /* Pending Requests */
} wstat_fields_s;
} hubii_wstat_t;
typedef union hubii_ilcsr_u {
u64 icsr_reg_value;
struct {
u64 icsr_rsvd: 22, /* unused */
icsr_max_burst: 10, /* max burst */
icsr_rsvd4: 6, /* reserved */
icsr_max_retry: 10, /* max retry */
icsr_rsvd3: 2, /* reserved */
icsr_lnk_stat: 2, /* link status */
icsr_bm8: 1, /* Bit mode 8 */
icsr_llp_en: 1, /* LLP enable bit */
icsr_rsvd2: 1, /* reserver */
icsr_wrm_reset: 1, /* Warm reset bit */
icsr_rsvd1: 2, /* Data ready offset */
icsr_null_to: 6; /* Null timeout */
} icsr_fields_s;
} hubii_ilcsr_t;
typedef union hubii_iowa_u {
u64 iowa_reg_value;
struct {
u64 iowa_rsvd: 48, /* unused */
iowa_wxoac: 8, /* xtalk widget access bits */
iowa_rsvd1: 7, /* xtalk widget access bits */
iowa_w0oac: 1; /* xtalk widget access bits */
} iowa_fields_s;
} hubii_iowa_t;
typedef union hubii_iiwa_u {
u64 iiwa_reg_value;
struct {
u64 iiwa_rsvd: 48, /* unused */
iiwa_wxiac: 8, /* hub wid access bits */
iiwa_rsvd1: 7, /* reserved */
iiwa_w0iac: 1; /* hub wid0 access */
} iiwa_fields_s;
} hubii_iiwa_t;
typedef union hubii_illr_u {
u64 illr_reg_value;
struct {
u64 illr_rsvd: 32, /* unused */
illr_cb_cnt: 16, /* checkbit error count */
illr_sn_cnt: 16; /* sequence number count */
} illr_fields_s;
} hubii_illr_t;
/* The structures below are defined to extract and modify the ii
performance registers */
/* io_perf_sel allows the caller to specify what tests will be
performed */
typedef union io_perf_sel {
u64 perf_sel_reg;
struct {
u64 perf_rsvd : 48,
perf_icct : 8,
perf_ippr1 : 4,
perf_ippr0 : 4;
} perf_sel_bits;
} io_perf_sel_t;
/* io_perf_cnt is to extract the count from the hub registers. Due to
hardware problems there is only one counter, not two. */
typedef union io_perf_cnt {
u64 perf_cnt;
struct {
u64 perf_rsvd1 : 32,
perf_rsvd2 : 12,
perf_cnt : 20;
} perf_cnt_bits;
} io_perf_cnt_t;
#endif /* !__ASSEMBLY__ */
#define LNK_STAT_WORKING 0x2
#define IIO_LLP_CB_MAX 0xffff
#define IIO_LLP_SN_MAX 0xffff
/* IO PRB Entries */
#define IIO_NUM_IPRBS (9)
#define IIO_IOPRB_0 0x400198 /* PRB entry 0 */
#define IIO_IOPRB_8 0x4001a0 /* PRB entry 8 */
#define IIO_IOPRB_9 0x4001a8 /* PRB entry 9 */
#define IIO_IOPRB_A 0x4001b0 /* PRB entry a */
#define IIO_IOPRB_B 0x4001b8 /* PRB entry b */
#define IIO_IOPRB_C 0x4001c0 /* PRB entry c */
#define IIO_IOPRB_D 0x4001c8 /* PRB entry d */
#define IIO_IOPRB_E 0x4001d0 /* PRB entry e */
#define IIO_IOPRB_F 0x4001d8 /* PRB entry f */
#define IIO_IXCC 0x4001e0 /* Crosstalk credit count timeout */
#define IIO_IXTCC IIO_IXCC
#define IIO_IMEM 0x4001e8 /* Miscellaneous Enable Mask */
#define IIO_IXTT 0x4001f0 /* Crosstalk tail timeout */
#define IIO_IECLR 0x4001f8 /* IO error clear */
#define IIO_IBCN 0x400200 /* IO BTE CRB count */
/*
* IIO_IMEM Register fields.
*/
#define IIO_IMEM_W0ESD 0x1 /* Widget 0 shut down due to error */
#define IIO_IMEM_B0ESD (1 << 4) /* BTE 0 shut down due to error */
#define IIO_IMEM_B1ESD (1 << 8) /* BTE 1 Shut down due to error */
/* PIO Read address Table Entries */
#define IIO_IPCA 0x400300 /* PRB Counter adjust */
#define IIO_NUM_PRTES 8 /* Total number of PRB table entries */
#define IIO_PRTE_0 0x400308 /* PIO Read address table entry 0 */
#define IIO_PRTE(_x) (IIO_PRTE_0 + (8 * (_x)))
#define IIO_WIDPRTE(x) IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */
#define IIO_IPDR 0x400388 /* PIO table entry deallocation */
#define IIO_ICDR 0x400390 /* CRB Entry Deallocation */
#define IIO_IFDR 0x400398 /* IOQ FIFO Depth */
#define IIO_IIAP 0x4003a0 /* IIQ Arbitration Parameters */
#define IIO_IMMR IIO_IIAP
#define IIO_ICMR 0x4003a8 /* CRB Managment Register */
#define IIO_ICCR 0x4003b0 /* CRB Control Register */
#define IIO_ICTO 0x4003b8 /* CRB Time Out Register */
#define IIO_ICTP 0x4003c0 /* CRB Time Out Prescalar */
/*
* ICMR register fields
*/
#define IIO_ICMR_PC_VLD_SHFT 36
#define IIO_ICMR_PC_VLD_MASK (0x7fffUL << IIO_ICMR_PC_VLD_SHFT)
#define IIO_ICMR_CRB_VLD_SHFT 20
#define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
#define IIO_ICMR_FC_CNT_SHFT 16
#define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT)
#define IIO_ICMR_C_CNT_SHFT 4
#define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT)
#define IIO_ICMR_P_CNT_SHFT 0
#define IIO_ICMR_P_CNT_MASK (0xf << IIO_ICMR_P_CNT_SHFT)
#define IIO_ICMR_PRECISE (1UL << 52)
#define IIO_ICMR_CLR_RPPD (1UL << 13)
#define IIO_ICMR_CLR_RQPD (1UL << 12)
/*
* IIO PIO Deallocation register field masks : (IIO_IPDR)
*/
#define IIO_IPDR_PND (1 << 4)
/*
* IIO CRB deallocation register field masks: (IIO_ICDR)
*/
#define IIO_ICDR_PND (1 << 4)
/*
* IIO CRB control register Fields: IIO_ICCR
*/
#define IIO_ICCR_PENDING (0x10000)
#define IIO_ICCR_CMD_MASK (0xFF)
#define IIO_ICCR_CMD_SHFT (7)
#define IIO_ICCR_CMD_NOP (0x0) /* No Op */
#define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */
#define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */
#define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory
* via a WB
*/
#define IIO_ICCR_CMD_FLUSH (0x800)
/*
* CRB manipulation macros
* The CRB macros are slightly complicated, since there are up to
* four registers associated with each CRB entry.
*/
#define IIO_NUM_CRBS 15 /* Number of CRBs */
#define IIO_NUM_NORMAL_CRBS 12 /* Number of regular CRB entries */
#define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */
#define IIO_ICRB_OFFSET 8
#define IIO_ICRB_0 0x400400
/* XXX - This is now tuneable:
#define IIO_FIRST_PC_ENTRY 12
*/
#define IIO_ICRB_A(_x) (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x)))
#define IIO_ICRB_B(_x) (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)
#define IIO_ICRB_C(_x) (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)
#define IIO_ICRB_D(_x) (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)
/* XXX - IBUE register coming for Hub 2 */
/*
*
* CRB Register description.
*
* WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
* WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
* WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
* WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
* WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
*
* Many of the fields in CRB are status bits used by hardware
* for implementation of the protocol. It's very dangerous to
* mess around with the CRB registers.
*
* It's OK to read the CRB registers and try to make sense out of the
* fields in CRB.
*
* Updating CRB requires all activities in Hub IIO to be quiesced.
* otherwise, a write to CRB could corrupt other CRB entries.
* CRBs are here only as a back door peek to hub IIO's status.
* Quiescing implies no dmas no PIOs
* either directly from the cpu or from sn0net.
* this is not something that can be done easily. So, AVOID updating
* CRBs.
*/
/*
* Fields in CRB Register A
*/
#ifndef __ASSEMBLY__
typedef union icrba_u {
u64 reg_value;
struct {
u64 resvd: 6,
stall_bte0: 1, /* Stall BTE 0 */
stall_bte1: 1, /* Stall BTE 1 */
error: 1, /* CRB has an error */
ecode: 3, /* Error Code */
lnetuce: 1, /* SN0net Uncorrectable error */
mark: 1, /* CRB Has been marked */
xerr: 1, /* Error bit set in xtalk header */
sidn: 4, /* SIDN field from xtalk */
tnum: 5, /* TNUM field in xtalk */
addr: 38, /* Address of request */
valid: 1, /* Valid status */
iow: 1; /* IO Write operation */
} icrba_fields_s;
} icrba_t;
/* This is an alternate typedef for the HUB1 CRB A in order to allow
runtime selection of the format based on the REV_ID field of the
NI_STATUS_REV_ID register. */
typedef union h1_icrba_u {
u64 reg_value;
struct {
u64 resvd: 6,
unused: 1, /* Unused but RW!! */
error: 1, /* CRB has an error */
ecode: 4, /* Error Code */
lnetuce: 1, /* SN0net Uncorrectable error */
mark: 1, /* CRB Has been marked */
xerr: 1, /* Error bit set in xtalk header */
sidn: 4, /* SIDN field from xtalk */
tnum: 5, /* TNUM field in xtalk */
addr: 38, /* Address of request */
valid: 1, /* Valid status */
iow: 1; /* IO Write operation */
} h1_icrba_fields_s;
} h1_icrba_t;
/* XXX - Is this still right? Check the spec. */
#define ICRBN_A_CERR_SHFT 54
#define ICRBN_A_ERR_MASK 0x3ff
#if 0 /* Disabled, this causes namespace polution and break allmodconfig */
/*
* Easy access macros.
*/
#define a_error icrba_fields_s.error
#define a_ecode icrba_fields_s.ecode
#define a_lnetuce icrba_fields_s.lnetuce
#define a_mark icrba_fields_s.mark
#define a_xerr icrba_fields_s.xerr
#define a_sidn icrba_fields_s.sidn
#define a_tnum icrba_fields_s.tnum
#define a_addr icrba_fields_s.addr
#define a_valid icrba_fields_s.valid
#define a_iow icrba_fields_s.iow
#endif
#endif /* !__ASSEMBLY__ */
#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */
/*
* values for "ecode" field
*/
#define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */
#define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */
#define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access
* e.g. WINV to a Read only line.
*/
#define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */
#define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */
#define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */
#define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */
#define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */
/*
* Fields in CRB Register B
*/
#ifndef __ASSEMBLY__
typedef union icrbb_u {
u64 reg_value;
struct {
u64 rsvd1: 5,
btenum: 1, /* BTE to which entry belongs to */
cohtrans: 1, /* Coherent transaction */
xtsize: 2, /* Xtalk operation size
* 0: Double Word
* 1: 32 Bytes.
* 2: 128 Bytes,
* 3: Reserved.
*/
srcnode: 9, /* Source Node ID */
srcinit: 2, /* Source Initiator:
* See below for field values.
*/
useold: 1, /* Use OLD command for processing */
imsgtype: 2, /* Incoming message type
* see below for field values
*/
imsg: 8, /* Incoming message */
initator: 3, /* Initiator of original request
* See below for field values.
*/
reqtype: 5, /* Identifies type of request
* See below for field values.
*/
rsvd2: 7,
ackcnt: 11, /* Invalidate ack count */
resp: 1, /* data response given to processor */
ack: 1, /* indicates data ack received */
hold: 1, /* entry is gathering inval acks */
wb_pend:1, /* waiting for writeback to complete */
intvn: 1, /* Intervention */
stall_ib: 1, /* Stall Ibuf (from crosstalk) */
stall_intr: 1; /* Stall internal interrupts */
} icrbb_field_s;
} icrbb_t;
/* This is an alternate typedef for the HUB1 CRB B in order to allow
runtime selection of the format based on the REV_ID field of the
NI_STATUS_REV_ID register. */
typedef union h1_icrbb_u {
u64 reg_value;
struct {
u64 rsvd1: 5,
btenum: 1, /* BTE to which entry belongs to */
cohtrans: 1, /* Coherent transaction */
xtsize: 2, /* Xtalk operation size
* 0: Double Word
* 1: 32 Bytes.
* 2: 128 Bytes,
* 3: Reserved.
*/
srcnode: 9, /* Source Node ID */
srcinit: 2, /* Source Initiator:
* See below for field values.
*/
useold: 1, /* Use OLD command for processing */
imsgtype: 2, /* Incoming message type
* see below for field values
*/
imsg: 8, /* Incoming message */
initator: 3, /* Initiator of original request
* See below for field values.
*/
rsvd2: 1,
pcache: 1, /* entry belongs to partial cache */
reqtype: 5, /* Identifies type of request
* See below for field values.
*/
stl_ib: 1, /* stall Ibus coming from xtalk */
stl_intr: 1, /* Stall internal interrupts */
stl_bte0: 1, /* Stall BTE 0 */
stl_bte1: 1, /* Stall BTE 1 */
intrvn: 1, /* Req was target of intervention */
ackcnt: 11, /* Invalidate ack count */
resp: 1, /* data response given to processor */
ack: 1, /* indicates data ack received */
hold: 1, /* entry is gathering inval acks */
wb_pend:1, /* waiting for writeback to complete */
sleep: 1, /* xtalk req sleeping till IO-sync */
pnd_reply: 1, /* replies not issed due to IOQ full */
pnd_req: 1; /* reqs not issued due to IOQ full */
} h1_icrbb_field_s;
} h1_icrbb_t;
#define b_imsgtype icrbb_field_s.imsgtype
#define b_btenum icrbb_field_s.btenum
#define b_cohtrans icrbb_field_s.cohtrans
#define b_xtsize icrbb_field_s.xtsize
#define b_srcnode icrbb_field_s.srcnode
#define b_srcinit icrbb_field_s.srcinit
#define b_imsgtype icrbb_field_s.imsgtype
#define b_imsg icrbb_field_s.imsg
#define b_initiator icrbb_field_s.initiator
#endif /* !__ASSEMBLY__ */
/*
* values for field xtsize
*/
#define IIO_ICRB_XTSIZE_DW 0 /* Xtalk operation size is 8 bytes */
#define IIO_ICRB_XTSIZE_32 1 /* Xtalk operation size is 32 bytes */
#define IIO_ICRB_XTSIZE_128 2 /* Xtalk operation size is 128 bytes */
/*
* values for field srcinit
*/
#define IIO_ICRB_PROC0 0 /* Source of request is Proc 0 */
#define IIO_ICRB_PROC1 1 /* Source of request is Proc 1 */
#define IIO_ICRB_GB_REQ 2 /* Source is Guranteed BW request */
#define IIO_ICRB_IO_REQ 3 /* Source is Normal IO request */
/*
* Values for field imsgtype
*/
#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */
#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */
#define IIO_ICRB_IMSGT_SN0NET 2 /* Incoming message from SN0 net */
#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */
/*
* values for field initiator.
*/
#define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */
#define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */
#define IIO_ICRB_INIT_SN0NET 0x2 /* Message originated in SN0net */
#define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */
#define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */
/*
* Values for field reqtype.
*/
/* XXX - Need to fix this for Hub 2 */
#define IIO_ICRB_REQ_DWRD 0 /* Request type double word */
#define IIO_ICRB_REQ_QCLRD 1 /* Request is Qrtr Caceh line Rd */
#define IIO_ICRB_REQ_BLKRD 2 /* Request is block read */
#define IIO_ICRB_REQ_RSHU 6 /* Request is BTE block read */
#define IIO_ICRB_REQ_REXU 7 /* request is BTE Excl Read */
#define IIO_ICRB_REQ_RDEX 8 /* Request is Read Exclusive */
#define IIO_ICRB_REQ_WINC 9 /* Request is Write Invalidate */
#define IIO_ICRB_REQ_BWINV 10 /* Request is BTE Winv */
#define IIO_ICRB_REQ_PIORD 11 /* Request is PIO read */
#define IIO_ICRB_REQ_PIOWR 12 /* Request is PIO Write */
#define IIO_ICRB_REQ_PRDM 13 /* Request is Fetch&Op */
#define IIO_ICRB_REQ_PWRM 14 /* Request is Store &Op */
#define IIO_ICRB_REQ_PTPWR 15 /* Request is Peer to peer */
#define IIO_ICRB_REQ_WB 16 /* Request is Write back */
#define IIO_ICRB_REQ_DEX 17 /* Retained DEX Cache line */
/*
* Fields in CRB Register C
*/
#ifndef __ASSEMBLY__
typedef union icrbc_s {
u64 reg_value;
struct {
u64 rsvd: 6,
sleep: 1,
pricnt: 4, /* Priority count sent with Read req */
pripsc: 4, /* Priority Pre scalar */
bteop: 1, /* BTE Operation */
push_be: 34, /* Push address Byte enable
* Holds push addr, if CRB is for BTE
* If CRB belongs to Partial cache,
* this contains byte enables bits
* ([47:46] = 0)
*/
suppl: 11, /* Supplemental field */
barrop: 1, /* Barrier Op bit set in xtalk req */
doresp: 1, /* Xtalk req needs a response */
gbr: 1; /* GBR bit set in xtalk packet */
} icrbc_field_s;
} icrbc_t;
#define c_pricnt icrbc_field_s.pricnt
#define c_pripsc icrbc_field_s.pripsc
#define c_bteop icrbc_field_s.bteop
#define c_bteaddr icrbc_field_s.push_be /* push_be field has 2 names */
#define c_benable icrbc_field_s.push_be /* push_be field has 2 names */
#define c_suppl icrbc_field_s.suppl
#define c_barrop icrbc_field_s.barrop
#define c_doresp icrbc_field_s.doresp
#define c_gbr icrbc_field_s.gbr
#endif /* !__ASSEMBLY__ */
/*
* Fields in CRB Register D
*/
#ifndef __ASSEMBLY__
typedef union icrbd_s {
u64 reg_value;
struct {
u64 rsvd: 38,
toutvld: 1, /* Timeout in progress for this CRB */
ctxtvld: 1, /* Context field below is valid */
rsvd2: 1,
context: 15, /* Bit vector:
* Has a bit set for each CRB entry
* which needs to be deallocated
* before this CRB entry is processed.
* Set only for barrier operations.
*/
timeout: 8; /* Timeout Upper 8 bits */
} icrbd_field_s;
} icrbd_t;
#define icrbd_toutvld icrbd_field_s.toutvld
#define icrbd_ctxtvld icrbd_field_s.ctxtvld
#define icrbd_context icrbd_field_s.context
typedef union hubii_ifdr_u {
u64 hi_ifdr_value;
struct {
u64 ifdr_rsvd: 49,
ifdr_maxrp: 7,
ifdr_rsvd1: 1,
ifdr_maxrq: 7;
} hi_ifdr_fields;
} hubii_ifdr_t;
#endif /* !__ASSEMBLY__ */
/*
* Hardware designed names for the BTE control registers.
*/
#define IIO_IBLS_0 0x410000 /* BTE length/status 0 */
#define IIO_IBSA_0 0x410008 /* BTE source address 0 */
#define IIO_IBDA_0 0x410010 /* BTE destination address 0 */
#define IIO_IBCT_0 0x410018 /* BTE control/terminate 0 */
#define IIO_IBNA_0 0x410020 /* BTE notification address 0 */
#define IIO_IBNR_0 IIO_IBNA_0
#define IIO_IBIA_0 0x410028 /* BTE interrupt address 0 */
#define IIO_IBLS_1 0x420000 /* BTE length/status 1 */
#define IIO_IBSA_1 0x420008 /* BTE source address 1 */
#define IIO_IBDA_1 0x420010 /* BTE destination address 1 */
#define IIO_IBCT_1 0x420018 /* BTE control/terminate 1 */
#define IIO_IBNA_1 0x420020 /* BTE notification address 1 */
#define IIO_IBNR_1 IIO_IBNA_1
#define IIO_IBIA_1 0x420028 /* BTE interrupt address 1 */
/*
* More miscellaneous registers
*/
#define IIO_IPCR 0x430000 /* Performance Control */
#define IIO_IPPR 0x430008 /* Performance Profiling */
/*
* IO Error Clear register bit field definitions
*/
#define IECLR_BTE1 (1 << 18) /* clear bte error 1 ??? */
#define IECLR_BTE0 (1 << 17) /* clear bte error 0 ??? */
#define IECLR_CRAZY (1 << 16) /* clear crazy bit in wstat reg */
#define IECLR_PRB_F (1 << 15) /* clear err bit in PRB_F reg */
#define IECLR_PRB_E (1 << 14) /* clear err bit in PRB_E reg */
#define IECLR_PRB_D (1 << 13) /* clear err bit in PRB_D reg */
#define IECLR_PRB_C (1 << 12) /* clear err bit in PRB_C reg */
#define IECLR_PRB_B (1 << 11) /* clear err bit in PRB_B reg */
#define IECLR_PRB_A (1 << 10) /* clear err bit in PRB_A reg */
#define IECLR_PRB_9 (1 << 9) /* clear err bit in PRB_9 reg */
#define IECLR_PRB_8 (1 << 8) /* clear err bit in PRB_8 reg */
#define IECLR_PRB_0 (1 << 0) /* clear err bit in PRB_0 reg */
/*
* IO PIO Read Table Entry format
*/
#ifndef __ASSEMBLY__
typedef union iprte_a {
u64 entry;
struct {
u64 rsvd1 : 7, /* Reserved field */
valid : 1, /* Maps to a timeout entry */
rsvd2 : 1,
srcnode : 9, /* Node which did this PIO */
initiator : 2, /* If T5A or T5B or IO */
rsvd3 : 3,
addr : 38, /* Physical address of PIO */
rsvd4 : 3;
} iprte_fields;
} iprte_a_t;
#define iprte_valid iprte_fields.valid
#define iprte_timeout iprte_fields.timeout
#define iprte_srcnode iprte_fields.srcnode
#define iprte_init iprte_fields.initiator
#define iprte_addr iprte_fields.addr
#endif /* !__ASSEMBLY__ */
#define IPRTE_ADDRSHFT 3
/*
* Hub IIO PRB Register format.
*/
#ifndef __ASSEMBLY__
/*
* Note: Fields bnakctr, anakctr, xtalkctrmode, ovflow fields are
* "Status" fields, and should only be used in case of clean up after errors.
*/
typedef union iprb_u {
u64 reg_value;
struct {
u64 rsvd1: 15,
error: 1, /* Widget rcvd wr resp pkt w/ error */
ovflow: 5, /* Over flow count. perf measurement */
fire_and_forget: 1, /* Launch Write without response */
mode: 2, /* Widget operation Mode */
rsvd2: 2,
bnakctr: 14,
rsvd3: 2,
anakctr: 14,
xtalkctr: 8;
} iprb_fields_s;
} iprb_t;
#define iprb_regval reg_value
#define iprb_error iprb_fields_s.error
#define iprb_ovflow iprb_fields_s.ovflow
#define iprb_ff iprb_fields_s.fire_and_forget
#define iprb_mode iprb_fields_s.mode
#define iprb_bnakctr iprb_fields_s.bnakctr
#define iprb_anakctr iprb_fields_s.anakctr
#define iprb_xtalkctr iprb_fields_s.xtalkctr
#endif /* !__ASSEMBLY__ */
/*
* values for mode field in iprb_t.
* For details of the meanings of NAK and Accept, refer the PIO flow
* document
*/
#define IPRB_MODE_NORMAL (0)
#define IPRB_MODE_COLLECT_A (1) /* PRB in collect A mode */
#define IPRB_MODE_SERVICE_A (2) /* NAK B and Accept A */
#define IPRB_MODE_SERVICE_B (3) /* NAK A and Accept B */
/*
* IO CRB entry C_A to E_A : Partial (cache) CRBS
*/
#ifndef __ASSEMBLY__
typedef union icrbp_a {
u64 ip_reg; /* the entire register value */
struct {
u64 error: 1, /* 63, error occurred */
ln_uce: 1, /* 62: uncorrectable memory */
ln_ae: 1, /* 61: protection violation */
ln_werr:1, /* 60: write access error */
ln_aerr:1, /* 59: sn0net: Address error */
ln_perr:1, /* 58: sn0net: poison error */
timeout:1, /* 57: CRB timed out */
l_bdpkt:1, /* 56: truncated pkt on sn0net */
c_bdpkt:1, /* 55: truncated pkt on xtalk */
c_err: 1, /* 54: incoming xtalk req, err set*/
rsvd1: 12, /* 53-42: reserved */
valid: 1, /* 41: Valid status */
sidn: 4, /* 40-37: SIDN field of xtalk rqst */
tnum: 5, /* 36-32: TNUM of xtalk request */
bo: 1, /* 31: barrier op set in xtalk rqst*/
resprqd:1, /* 30: xtalk rqst requires response*/
gbr: 1, /* 29: gbr bit set in xtalk rqst */
size: 2, /* 28-27: size of xtalk request */
excl: 4, /* 26-23: exclusive bit(s) */
stall: 3, /* 22-20: stall (xtalk, bte 0/1) */
intvn: 1, /* 19: rqst target of intervention*/
resp: 1, /* 18: Data response given to t5 */
ack: 1, /* 17: Data ack received. */
hold: 1, /* 16: crb gathering invalidate acks*/
wb: 1, /* 15: writeback pending. */
ack_cnt:11, /* 14-04: counter of invalidate acks*/
tscaler:4; /* 03-00: Timeout prescaler */
} ip_fmt;
} icrbp_a_t;
#endif /* !__ASSEMBLY__ */
/*
* A couple of defines to go with the above structure.
*/
#define ICRBP_A_CERR_SHFT 54
#define ICRBP_A_ERR_MASK 0x3ff
#ifndef __ASSEMBLY__
typedef union hubii_idsr {
u64 iin_reg;
struct {
u64 rsvd1 : 35,
isent : 1,
rsvd2 : 3,
ienable: 1,
rsvd : 7,
node : 9,
rsvd4 : 1,
level : 7;
} iin_fmt;
} hubii_idsr_t;
#endif /* !__ASSEMBLY__ */
/*
* IO BTE Length/Status (IIO_IBLS) register bit field definitions
*/
#define IBLS_BUSY (0x1 << 20)
#define IBLS_ERROR_SHFT 16
#define IBLS_ERROR (0x1 << IBLS_ERROR_SHFT)
#define IBLS_LENGTH_MASK 0xffff
/*
* IO BTE Control/Terminate register (IBCT) register bit field definitions
*/
#define IBCT_POISON (0x1 << 8)
#define IBCT_NOTIFY (0x1 << 4)
#define IBCT_ZFIL_MODE (0x1 << 0)
/*
* IO BTE Interrupt Address Register (IBIA) register bit field definitions
*/
#define IBIA_LEVEL_SHFT 16
#define IBIA_LEVEL_MASK (0x7f << IBIA_LEVEL_SHFT)
#define IBIA_NODE_ID_SHFT 0
#define IBIA_NODE_ID_MASK (0x1ff)
/*
* Miscellaneous hub constants
*/
/* Number of widgets supported by hub */
#define HUB_NUM_WIDGET 9
#define HUB_WIDGET_ID_MIN 0x8
#define HUB_WIDGET_ID_MAX 0xf
#define HUB_WIDGET_PART_NUM 0xc101
#define MAX_HUBS_PER_XBOW 2
/*
* Get a hub's widget id from widget control register
*/
#define IIO_WCR_WID_GET(nasid) (REMOTE_HUB_L(nasid, III_WCR) & 0xf)
#define IIO_WST_ERROR_MASK (UINT64_CAST 1 << 32) /* Widget status error */
/*
* Number of credits Hub widget has while sending req/response to
* xbow.
* Value of 3 is required by Xbow 1.1
* We may be able to increase this to 4 with Xbow 1.2.
*/
#define HUBII_XBOW_CREDIT 3
#define HUBII_XBOW_REV2_CREDIT 4
#endif /* _ASM_SGI_SN_SN0_HUBIO_H */
include/asm-mips/sn/sn0/hubmd.h
+790
View File
@@ -0,0 +1,790 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Derived from IRIX <sys/SN/SN0/hubmd.h>, revision 1.59.
*
* Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
* Copyright (C) 1999 by Ralf Baechle
*/
#ifndef _ASM_SN_SN0_HUBMD_H
#define _ASM_SN_SN0_HUBMD_H
#include <linux/config.h>
/*
* Hub Memory/Directory interface registers
*/
#define CACHE_SLINE_SIZE 128 /* Secondary cache line size on SN0 */
#define MAX_REGIONS 64
/* Hardware page size and shift */
#define MD_PAGE_SIZE 4096 /* Page size in bytes */
#define MD_PAGE_NUM_SHFT 12 /* Address to page number shift */
/* Register offsets from LOCAL_HUB or REMOTE_HUB */
#define MD_BASE 0x200000
#define MD_BASE_PERF 0x210000
#define MD_BASE_JUNK 0x220000
#define MD_IO_PROTECT 0x200000 /* MD and core register protection */
#define MD_IO_PROT_OVRRD 0x200008 /* Clear my bit in MD_IO_PROTECT */
#define MD_HSPEC_PROTECT 0x200010 /* BDDIR, LBOOT, RBOOT protection */
#define MD_MEMORY_CONFIG 0x200018 /* Memory/Directory DIMM control */
#define MD_REFRESH_CONTROL 0x200020 /* Memory/Directory refresh ctrl */
#define MD_FANDOP_CAC_STAT 0x200028 /* Fetch-and-op cache status */
#define MD_MIG_DIFF_THRESH 0x200030 /* Page migr. count diff thresh. */
#define MD_MIG_VALUE_THRESH 0x200038 /* Page migr. count abs. thresh. */
#define MD_MIG_CANDIDATE 0x200040 /* Latest page migration candidate */
#define MD_MIG_CANDIDATE_CLR 0x200048 /* Clear page migration candidate */
#define MD_DIR_ERROR 0x200050 /* Directory DIMM error */
#define MD_DIR_ERROR_CLR 0x200058 /* Directory DIMM error clear */
#define MD_PROTOCOL_ERROR 0x200060 /* Directory protocol error */
#define MD_PROTOCOL_ERROR_CLR 0x200068 /* Directory protocol error clear */
#define MD_MEM_ERROR 0x200070 /* Memory DIMM error */
#define MD_MEM_ERROR_CLR 0x200078 /* Memory DIMM error clear */
#define MD_MISC_ERROR 0x200080 /* Miscellaneous MD error */
#define MD_MISC_ERROR_CLR 0x200088 /* Miscellaneous MD error clear */
#define MD_MEM_DIMM_INIT 0x200090 /* Memory DIMM mode initization. */
#define MD_DIR_DIMM_INIT 0x200098 /* Directory DIMM mode init. */
#define MD_MOQ_SIZE 0x2000a0 /* MD outgoing queue size */
#define MD_MLAN_CTL 0x2000a8 /* NIC (Microlan) control register */
#define MD_PERF_SEL 0x210000 /* Select perf monitor events */
#define MD_PERF_CNT0 0x210010 /* Performance counter 0 */
#define MD_PERF_CNT1 0x210018 /* Performance counter 1 */
#define MD_PERF_CNT2 0x210020 /* Performance counter 2 */
#define MD_PERF_CNT3 0x210028 /* Performance counter 3 */
#define MD_PERF_CNT4 0x210030 /* Performance counter 4 */
#define MD_PERF_CNT5 0x210038 /* Performance counter 5 */
#define MD_UREG0_0 0x220000 /* uController/UART 0 register */
#define MD_UREG0_1 0x220008 /* uController/UART 0 register */
#define MD_UREG0_2 0x220010 /* uController/UART 0 register */
#define MD_UREG0_3 0x220018 /* uController/UART 0 register */
#define MD_UREG0_4 0x220020 /* uController/UART 0 register */
#define MD_UREG0_5 0x220028 /* uController/UART 0 register */
#define MD_UREG0_6 0x220030 /* uController/UART 0 register */
#define MD_UREG0_7 0x220038 /* uController/UART 0 register */
#define MD_SLOTID_USTAT 0x220048 /* Hub slot ID & UART/uCtlr status */
#define MD_LED0 0x220050 /* Eight-bit LED for CPU A */
#define MD_LED1 0x220058 /* Eight-bit LED for CPU B */
#define MD_UREG1_0 0x220080 /* uController/UART 1 register */
#define MD_UREG1_1 0x220088 /* uController/UART 1 register */
#define MD_UREG1_2 0x220090 /* uController/UART 1 register */
#define MD_UREG1_3 0x220098 /* uController/UART 1 register */
#define MD_UREG1_4 0x2200a0 /* uController/UART 1 register */
#define MD_UREG1_5 0x2200a8 /* uController/UART 1 register */
#define MD_UREG1_6 0x2200b0 /* uController/UART 1 register */
#define MD_UREG1_7 0x2200b8 /* uController/UART 1 register */
#define MD_UREG1_8 0x2200c0 /* uController/UART 1 register */
#define MD_UREG1_9 0x2200c8 /* uController/UART 1 register */
#define MD_UREG1_10 0x2200d0 /* uController/UART 1 register */
#define MD_UREG1_11 0x2200d8 /* uController/UART 1 register */
#define MD_UREG1_12 0x2200e0 /* uController/UART 1 register */
#define MD_UREG1_13 0x2200e8 /* uController/UART 1 register */
#define MD_UREG1_14 0x2200f0 /* uController/UART 1 register */
#define MD_UREG1_15 0x2200f8 /* uController/UART 1 register */
#ifdef CONFIG_SGI_SN0_N_MODE
#define MD_MEM_BANKS 4 /* 4 banks of memory max in N mode */
#else
#define MD_MEM_BANKS 8 /* 8 banks of memory max in M mode */
#endif
/*
* MD_MEMORY_CONFIG fields
*
* MD_SIZE_xxx are useful for representing the size of a SIMM or bank
* (SIMM pair). They correspond to the values needed for the bit
* triplets (MMC_BANK_MASK) in the MD_MEMORY_CONFIG register for bank size.
* Bits not used by the MD are used by software.
*/
#define MD_SIZE_EMPTY 0 /* Valid in MEMORY_CONFIG */
#define MD_SIZE_8MB 1
#define MD_SIZE_16MB 2
#define MD_SIZE_32MB 3 /* Broken in Hub 1 */
#define MD_SIZE_64MB 4 /* Valid in MEMORY_CONFIG */
#define MD_SIZE_128MB 5 /* Valid in MEMORY_CONFIG */
#define MD_SIZE_256MB 6
#define MD_SIZE_512MB 7 /* Valid in MEMORY_CONFIG */
#define MD_SIZE_1GB 8
#define MD_SIZE_2GB 9
#define MD_SIZE_4GB 10
#define MD_SIZE_BYTES(size) ((size) == 0 ? 0 : 0x400000L << (size))
#define MD_SIZE_MBYTES(size) ((size) == 0 ? 0 : 4 << (size))
#define MMC_FPROM_CYC_SHFT 49 /* Have to use UINT64_CAST, instead */
#define MMC_FPROM_CYC_MASK (UINT64_CAST 31 << 49) /* of 'L' suffix, */
#define MMC_FPROM_WR_SHFT 44 /* for assembler */
#define MMC_FPROM_WR_MASK (UINT64_CAST 31 << 44)
#define MMC_UCTLR_CYC_SHFT 39
#define MMC_UCTLR_CYC_MASK (UINT64_CAST 31 << 39)
#define MMC_UCTLR_WR_SHFT 34
#define MMC_UCTLR_WR_MASK (UINT64_CAST 31 << 34)
#define MMC_DIMM0_SEL_SHFT 32
#define MMC_DIMM0_SEL_MASK (UINT64_CAST 3 << 32)
#define MMC_IO_PROT_EN_SHFT 31
#define MMC_IO_PROT_EN_MASK (UINT64_CAST 1 << 31)
#define MMC_IO_PROT (UINT64_CAST 1 << 31)
#define MMC_ARB_MLSS_SHFT 30
#define MMC_ARB_MLSS_MASK (UINT64_CAST 1 << 30)
#define MMC_ARB_MLSS (UINT64_CAST 1 << 30)
#define MMC_IGNORE_ECC_SHFT 29
#define MMC_IGNORE_ECC_MASK (UINT64_CAST 1 << 29)
#define MMC_IGNORE_ECC (UINT64_CAST 1 << 29)
#define MMC_DIR_PREMIUM_SHFT 28
#define MMC_DIR_PREMIUM_MASK (UINT64_CAST 1 << 28)
#define MMC_DIR_PREMIUM (UINT64_CAST 1 << 28)
#define MMC_REPLY_GUAR_SHFT 24
#define MMC_REPLY_GUAR_MASK (UINT64_CAST 15 << 24)
#define MMC_BANK_SHFT(_b) ((_b) * 3)
#define MMC_BANK_MASK(_b) (UINT64_CAST 7 << MMC_BANK_SHFT(_b))
#define MMC_BANK_ALL_MASK 0xffffff
#define MMC_RESET_DEFAULTS (UINT64_CAST 0x0f << MMC_FPROM_CYC_SHFT | \
UINT64_CAST 0x07 << MMC_FPROM_WR_SHFT | \
UINT64_CAST 0x1f << MMC_UCTLR_CYC_SHFT | \
UINT64_CAST 0x0f << MMC_UCTLR_WR_SHFT | \
MMC_IGNORE_ECC | MMC_DIR_PREMIUM | \
UINT64_CAST 0x0f << MMC_REPLY_GUAR_SHFT | \
MMC_BANK_ALL_MASK)
/* MD_REFRESH_CONTROL fields */
#define MRC_ENABLE_SHFT 63
#define MRC_ENABLE_MASK (UINT64_CAST 1 << 63)
#define MRC_ENABLE (UINT64_CAST 1 << 63)
#define MRC_COUNTER_SHFT 12
#define MRC_COUNTER_MASK (UINT64_CAST 0xfff << 12)
#define MRC_CNT_THRESH_MASK 0xfff
#define MRC_RESET_DEFAULTS (UINT64_CAST 0x400)
/* MD_MEM_DIMM_INIT and MD_DIR_DIMM_INIT fields */
#define MDI_SELECT_SHFT 32
#define MDI_SELECT_MASK (UINT64_CAST 0x0f << 32)
#define MDI_DIMM_MODE_MASK (UINT64_CAST 0xfff)
/* MD_MOQ_SIZE fields */
#define MMS_RP_SIZE_SHFT 8
#define MMS_RP_SIZE_MASK (UINT64_CAST 0x3f << 8)
#define MMS_RQ_SIZE_SHFT 0
#define MMS_RQ_SIZE_MASK (UINT64_CAST 0x1f)
#define MMS_RESET_DEFAULTS (0x32 << 8 | 0x12)
/* MD_FANDOP_CAC_STAT fields */
#define MFC_VALID_SHFT 63
#define MFC_VALID_MASK (UINT64_CAST 1 << 63)
#define MFC_VALID (UINT64_CAST 1 << 63)
#define MFC_ADDR_SHFT 6
#define MFC_ADDR_MASK (UINT64_CAST 0x3ffffff)
/* MD_MLAN_CTL fields */
#define MLAN_PHI1_SHFT 27
#define MLAN_PHI1_MASK (UINT64_CAST 0x7f << 27)
#define MLAN_PHI0_SHFT 20
#define MLAN_PHI0_MASK (UINT64_CAST 0x7f << 27)
#define MLAN_PULSE_SHFT 10
#define MLAN_PULSE_MASK (UINT64_CAST 0x3ff << 10)
#define MLAN_SAMPLE_SHFT 2
#define MLAN_SAMPLE_MASK (UINT64_CAST 0xff << 2)
#define MLAN_DONE_SHFT 1
#define MLAN_DONE_MASK 2
#define MLAN_DONE (UINT64_CAST 0x02)
#define MLAN_RD_DATA (UINT64_CAST 0x01)
#define MLAN_RESET_DEFAULTS (UINT64_CAST 0x31 << MLAN_PHI1_SHFT | \
UINT64_CAST 0x31 << MLAN_PHI0_SHFT)
/* MD_SLOTID_USTAT bit definitions */
#define MSU_CORECLK_TST_SHFT 7 /* You don't wanna know */
#define MSU_CORECLK_TST_MASK (UINT64_CAST 1 << 7)
#define MSU_CORECLK_TST (UINT64_CAST 1 << 7)
#define MSU_CORECLK_SHFT 6 /* You don't wanna know */
#define MSU_CORECLK_MASK (UINT64_CAST 1 << 6)
#define MSU_CORECLK (UINT64_CAST 1 << 6)
#define MSU_NETSYNC_SHFT 5 /* You don't wanna know */
#define MSU_NETSYNC_MASK (UINT64_CAST 1 << 5)
#define MSU_NETSYNC (UINT64_CAST 1 << 5)
#define MSU_FPROMRDY_SHFT 4 /* Flash PROM ready bit */
#define MSU_FPROMRDY_MASK (UINT64_CAST 1 << 4)
#define MSU_FPROMRDY (UINT64_CAST 1 << 4)
#define MSU_I2CINTR_SHFT 3 /* I2C interrupt bit */
#define MSU_I2CINTR_MASK (UINT64_CAST 1 << 3)
#define MSU_I2CINTR (UINT64_CAST 1 << 3)
#define MSU_SLOTID_MASK 0xff
#define MSU_SN0_SLOTID_SHFT 0 /* Slot ID */
#define MSU_SN0_SLOTID_MASK (UINT64_CAST 7)
#define MSU_SN00_SLOTID_SHFT 7
#define MSU_SN00_SLOTID_MASK (UINT64_CAST 0x80)
#define MSU_PIMM_PSC_SHFT 4
#define MSU_PIMM_PSC_MASK (0xf << MSU_PIMM_PSC_SHFT)
/* MD_MIG_DIFF_THRESH bit definitions */
#define MD_MIG_DIFF_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
#define MD_MIG_DIFF_THRES_VALID_SHFT 63
#define MD_MIG_DIFF_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
/* MD_MIG_VALUE_THRESH bit definitions */
#define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
#define MD_MIG_VALUE_THRES_VALID_SHFT 63
#define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
/* MD_MIG_CANDIDATE bit definitions */
#define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63)
#define MD_MIG_CANDIDATE_VALID_SHFT 63
#define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30)
#define MD_MIG_CANDIDATE_TYPE_SHFT 30
#define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29)
#define MD_MIG_CANDIDATE_OVERRUN_SHFT 29
#define MD_MIG_CANDIDATE_INITIATOR_MASK (UINT64_CAST 0x7ff << 18)
#define MD_MIG_CANDIDATE_INITIATOR_SHFT 18
#define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20)
#define MD_MIG_CANDIDATE_NODEID_SHFT 20
#define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff)
#define MD_MIG_CANDIDATE_ADDR_SHFT 14 /* The address starts at bit 14 */
/* Other MD definitions */
#define MD_BANK_SHFT 29 /* log2(512 MB) */
#define MD_BANK_MASK (UINT64_CAST 7 << 29)
#define MD_BANK_SIZE (UINT64_CAST 1 << MD_BANK_SHFT) /* 512 MB */
#define MD_BANK_OFFSET(_b) (UINT64_CAST (_b) << MD_BANK_SHFT)
/*
* The following definitions cover the bit field definitions for the
* various MD registers. For multi-bit registers, we define both
* a shift amount and a mask value. By convention, if you want to
* isolate a field, you should mask the field and then shift it down,
* since this makes the masks useful without a shift.
*/
/* Directory entry states for both premium and standard SIMMs. */
#define MD_DIR_SHARED (UINT64_CAST 0x0) /* 000 */
#define MD_DIR_POISONED (UINT64_CAST 0x1) /* 001 */
#define MD_DIR_EXCLUSIVE (UINT64_CAST 0x2) /* 010 */
#define MD_DIR_BUSY_SHARED (UINT64_CAST 0x3) /* 011 */
#define MD_DIR_BUSY_EXCL (UINT64_CAST 0x4) /* 100 */
#define MD_DIR_WAIT (UINT64_CAST 0x5) /* 101 */
#define MD_DIR_UNOWNED (UINT64_CAST 0x7) /* 111 */
/*
* The MD_DIR_FORCE_ECC bit can be added directory entry write data
* to forcing the ECC to be written as-is instead of recalculated.
*/
#define MD_DIR_FORCE_ECC (UINT64_CAST 1 << 63)
/*
* Premium SIMM directory entry shifts and masks. Each is valid only in the
* context(s) indicated, where A, B, and C indicate the directory entry format
* as shown, and low and/or high indicates which double-word of the entry.
*
* Format A: STATE = shared, FINE = 1
* Format B: STATE = shared, FINE = 0
* Format C: STATE != shared (FINE must be 0)
*/
#define MD_PDIR_MASK 0xffffffffffff /* Whole entry */
#define MD_PDIR_ECC_SHFT 0 /* ABC low or high */
#define MD_PDIR_ECC_MASK 0x7f
#define MD_PDIR_PRIO_SHFT 8 /* ABC low */
#define MD_PDIR_PRIO_MASK (0xf << 8)
#define MD_PDIR_AX_SHFT 7 /* ABC low */
#define MD_PDIR_AX_MASK (1 << 7)
#define MD_PDIR_AX (1 << 7)
#define MD_PDIR_FINE_SHFT 12 /* ABC low */
#define MD_PDIR_FINE_MASK (1 << 12)
#define MD_PDIR_FINE (1 << 12)
#define MD_PDIR_OCT_SHFT 13 /* A low */
#define MD_PDIR_OCT_MASK (7 << 13)
#define MD_PDIR_STATE_SHFT 13 /* BC low */
#define MD_PDIR_STATE_MASK (7 << 13)
#define MD_PDIR_ONECNT_SHFT 16 /* BC low */
#define MD_PDIR_ONECNT_MASK (0x3f << 16)
#define MD_PDIR_PTR_SHFT 22 /* C low */
#define MD_PDIR_PTR_MASK (UINT64_CAST 0x7ff << 22)
#define MD_PDIR_VECMSB_SHFT 22 /* AB low */
#define MD_PDIR_VECMSB_BITMASK 0x3ffffff
#define MD_PDIR_VECMSB_BITSHFT 27
#define MD_PDIR_VECMSB_MASK (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22)
#define MD_PDIR_CWOFF_SHFT 7 /* C high */
#define MD_PDIR_CWOFF_MASK (7 << 7)
#define MD_PDIR_VECLSB_SHFT 10 /* AB high */
#define MD_PDIR_VECLSB_BITMASK (UINT64_CAST 0x3fffffffff)
#define MD_PDIR_VECLSB_BITSHFT 0
#define MD_PDIR_VECLSB_MASK (MD_PDIR_VECLSB_BITMASK << 10)
/*
* Directory initialization values
*/
#define MD_PDIR_INIT_LO (MD_DIR_UNOWNED << MD_PDIR_STATE_SHFT | \
MD_PDIR_AX)
#define MD_PDIR_INIT_HI 0
#define MD_PDIR_INIT_PROT (MD_PROT_RW << MD_PPROT_IO_SHFT | \
MD_PROT_RW << MD_PPROT_SHFT)
/*
* Standard SIMM directory entry shifts and masks. Each is valid only in the
* context(s) indicated, where A and C indicate the directory entry format
* as shown, and low and/or high indicates which double-word of the entry.
*
* Format A: STATE == shared
* Format C: STATE != shared
*/
#define MD_SDIR_MASK 0xffff /* Whole entry */
#define MD_SDIR_ECC_SHFT 0 /* AC low or high */
#define MD_SDIR_ECC_MASK 0x1f
#define MD_SDIR_PRIO_SHFT 6 /* AC low */
#define MD_SDIR_PRIO_MASK (1 << 6)
#define MD_SDIR_AX_SHFT 5 /* AC low */
#define MD_SDIR_AX_MASK (1 << 5)
#define MD_SDIR_AX (1 << 5)
#define MD_SDIR_STATE_SHFT 7 /* AC low */
#define MD_SDIR_STATE_MASK (7 << 7)
#define MD_SDIR_PTR_SHFT 10 /* C low */
#define MD_SDIR_PTR_MASK (0x3f << 10)
#define MD_SDIR_CWOFF_SHFT 5 /* C high */
#define MD_SDIR_CWOFF_MASK (7 << 5)
#define MD_SDIR_VECMSB_SHFT 11 /* A low */
#define MD_SDIR_VECMSB_BITMASK 0x1f
#define MD_SDIR_VECMSB_BITSHFT 7
#define MD_SDIR_VECMSB_MASK (MD_SDIR_VECMSB_BITMASK << 11)
#define MD_SDIR_VECLSB_SHFT 5 /* A high */
#define MD_SDIR_VECLSB_BITMASK 0x7ff
#define MD_SDIR_VECLSB_BITSHFT 0
#define MD_SDIR_VECLSB_MASK (MD_SDIR_VECLSB_BITMASK << 5)
/*
* Directory initialization values
*/
#define MD_SDIR_INIT_LO (MD_DIR_UNOWNED << MD_SDIR_STATE_SHFT | \
MD_SDIR_AX)
#define MD_SDIR_INIT_HI 0
#define MD_SDIR_INIT_PROT (MD_PROT_RW << MD_SPROT_SHFT)
/* Protection and migration field values */
#define MD_PROT_RW (UINT64_CAST 0x6)
#define MD_PROT_RO (UINT64_CAST 0x3)
#define MD_PROT_NO (UINT64_CAST 0x0)
#define MD_PROT_BAD (UINT64_CAST 0x5)
/* Premium SIMM protection entry shifts and masks. */
#define MD_PPROT_SHFT 0 /* Prot. field */
#define MD_PPROT_MASK 7
#define MD_PPROT_MIGMD_SHFT 3 /* Migration mode */
#define MD_PPROT_MIGMD_MASK (3 << 3)
#define MD_PPROT_REFCNT_SHFT 5 /* Reference count */
#define MD_PPROT_REFCNT_WIDTH 0x7ffff
#define MD_PPROT_REFCNT_MASK (MD_PPROT_REFCNT_WIDTH << 5)
#define MD_PPROT_IO_SHFT 45 /* I/O Prot field */
#define MD_PPROT_IO_MASK (UINT64_CAST 7 << 45)
/* Standard SIMM protection entry shifts and masks. */
#define MD_SPROT_SHFT 0 /* Prot. field */
#define MD_SPROT_MASK 7
#define MD_SPROT_MIGMD_SHFT 3 /* Migration mode */
#define MD_SPROT_MIGMD_MASK (3 << 3)
#define MD_SPROT_REFCNT_SHFT 5 /* Reference count */
#define MD_SPROT_REFCNT_WIDTH 0x7ff
#define MD_SPROT_REFCNT_MASK (MD_SPROT_REFCNT_WIDTH << 5)
/* Migration modes used in protection entries */
#define MD_PROT_MIGMD_IREL (UINT64_CAST 0x3 << 3)
#define MD_PROT_MIGMD_IABS (UINT64_CAST 0x2 << 3)
#define MD_PROT_MIGMD_PREL (UINT64_CAST 0x1 << 3)
#define MD_PROT_MIGMD_OFF (UINT64_CAST 0x0 << 3)
/*
* Operations on page migration threshold register
*/
#ifndef __ASSEMBLY__
/*
* LED register macros
*/
#define CPU_LED_ADDR(_nasid, _slice) \
(private.p_sn00 ? \
REMOTE_HUB_ADDR((_nasid), MD_UREG1_0 + ((_slice) << 5)) : \
REMOTE_HUB_ADDR((_nasid), MD_LED0 + ((_slice) << 3)))
#define SET_CPU_LEDS(_nasid, _slice, _val) \
(HUB_S(CPU_LED_ADDR(_nasid, _slice), (_val)))
#define SET_MY_LEDS(_v) \
SET_CPU_LEDS(get_nasid(), get_slice(), (_v))
/*
* Operations on Memory/Directory DIMM control register
*/
#define DIRTYPE_PREMIUM 1
#define DIRTYPE_STANDARD 0
#define MD_MEMORY_CONFIG_DIR_TYPE_GET(region) (\
(REMOTE_HUB_L(region, MD_MEMORY_CONFIG) & MMC_DIR_PREMIUM_MASK) >> \
MMC_DIR_PREMIUM_SHFT)
/*
* Operations on page migration count difference and absolute threshold
* registers
*/
#define MD_MIG_DIFF_THRESH_GET(region) ( \
REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) & \
MD_MIG_DIFF_THRES_VALUE_MASK)
#define MD_MIG_DIFF_THRESH_SET(region, value) ( \
REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH, \
MD_MIG_DIFF_THRES_VALID_MASK | (value)))
#define MD_MIG_DIFF_THRESH_DISABLE(region) ( \
REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH, \
REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) \
& ~MD_MIG_DIFF_THRES_VALID_MASK))
#define MD_MIG_DIFF_THRESH_ENABLE(region) ( \
REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH, \
REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) \
| MD_MIG_DIFF_THRES_VALID_MASK))
#define MD_MIG_DIFF_THRESH_IS_ENABLED(region) ( \
REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) & \
MD_MIG_DIFF_THRES_VALID_MASK)
#define MD_MIG_VALUE_THRESH_GET(region) ( \
REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) & \
MD_MIG_VALUE_THRES_VALUE_MASK)
#define MD_MIG_VALUE_THRESH_SET(region, value) ( \
REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \
MD_MIG_VALUE_THRES_VALID_MASK | (value)))
#define MD_MIG_VALUE_THRESH_DISABLE(region) ( \
REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \
REMOTE_HUB_L(region, MD_MIG_VALUE_THRESH) \
& ~MD_MIG_VALUE_THRES_VALID_MASK))
#define MD_MIG_VALUE_THRESH_ENABLE(region) ( \
REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \
REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) \
| MD_MIG_VALUE_THRES_VALID_MASK))
#define MD_MIG_VALUE_THRESH_IS_ENABLED(region) ( \
REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) & \
MD_MIG_VALUE_THRES_VALID_MASK)
/*
* Operations on page migration candidate register
*/
#define MD_MIG_CANDIDATE_GET(my_region_id) ( \
REMOTE_HUB_L((my_region_id), MD_MIG_CANDIDATE_CLR))
#define MD_MIG_CANDIDATE_HWPFN(value) ((value) & MD_MIG_CANDIDATE_ADDR_MASK)
#define MD_MIG_CANDIDATE_NODEID(value) ( \
((value) & MD_MIG_CANDIDATE_NODEID_MASK) >> MD_MIG_CANDIDATE_NODEID_SHFT)
#define MD_MIG_CANDIDATE_TYPE(value) ( \
((value) & MD_MIG_CANDIDATE_TYPE_MASK) >> MD_MIG_CANDIDATE_TYPE_SHFT)
#define MD_MIG_CANDIDATE_VALID(value) ( \
((value) & MD_MIG_CANDIDATE_VALID_MASK) >> MD_MIG_CANDIDATE_VALID_SHFT)
/*
* Macros to retrieve fields in the protection entry
*/
/* for Premium SIMM */
#define MD_PPROT_REFCNT_GET(value) ( \
((value) & MD_PPROT_REFCNT_MASK) >> MD_PPROT_REFCNT_SHFT)
#define MD_PPROT_MIGMD_GET(value) ( \
((value) & MD_PPROT_MIGMD_MASK) >> MD_PPROT_MIGMD_SHFT)
/* for Standard SIMM */
#define MD_SPROT_REFCNT_GET(value) ( \
((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT)
#define MD_SPROT_MIGMD_GET(value) ( \
((value) & MD_SPROT_MIGMD_MASK) >> MD_SPROT_MIGMD_SHFT)
/*
* Format of dir_error, mem_error, protocol_error and misc_error registers
*/
struct dir_error_reg {
u64 uce_vld: 1, /* 63: valid directory uce */
ae_vld: 1, /* 62: valid dir prot ecc error */
ce_vld: 1, /* 61: valid correctable ECC err*/
rsvd1: 19, /* 60-42: reserved */
bad_prot: 3, /* 41-39: encoding, bad access rights*/
bad_syn: 7, /* 38-32: bad dir syndrome */
rsvd2: 2, /* 31-30: reserved */
hspec_addr:27, /* 29-03: bddir space bad entry */
uce_ovr: 1, /* 2: multiple dir uce's */
ae_ovr: 1, /* 1: multiple prot ecc errs*/
ce_ovr: 1; /* 0: multiple correctable errs */
};
typedef union md_dir_error {
u64 derr_reg; /* the entire register */
struct dir_error_reg derr_fmt; /* the register format */
} md_dir_error_t;
struct mem_error_reg {
u64 uce_vld: 1, /* 63: valid memory uce */
ce_vld: 1, /* 62: valid correctable ECC err*/
rsvd1: 22, /* 61-40: reserved */
bad_syn: 8, /* 39-32: bad mem ecc syndrome */
address: 29, /* 31-03: bad entry pointer */
rsvd2: 1, /* 2: reserved */
uce_ovr: 1, /* 1: multiple mem uce's */
ce_ovr: 1; /* 0: multiple correctable errs */
};
typedef union md_mem_error {
u64 merr_reg; /* the entire register */
struct mem_error_reg merr_fmt; /* format of the mem_error reg */
} md_mem_error_t;
struct proto_error_reg {
u64 valid: 1, /* 63: valid protocol error */
rsvd1: 2, /* 62-61: reserved */
initiator:11, /* 60-50: id of request initiator*/
backoff: 2, /* 49-48: backoff control */
msg_type: 8, /* 47-40: type of request */
access: 2, /* 39-38: access rights of initiator*/
priority: 1, /* 37: priority level of requestor*/
dir_state: 4, /* 36-33: state of directory */
pointer_me:1, /* 32: initiator same as dir ptr */
address: 29, /* 31-03: request address */
rsvd2: 2, /* 02-01: reserved */
overrun: 1; /* 0: multiple protocol errs */
};
typedef union md_proto_error {
u64 perr_reg; /* the entire register */
struct proto_error_reg perr_fmt; /* format of the register */
} md_proto_error_t;
struct md_sdir_high_fmt {
unsigned short sd_hi_bvec : 11,
sd_hi_ecc : 5;
};
typedef union md_sdir_high {
/* The 16 bits of standard directory, upper word */
unsigned short sd_hi_val;
struct md_sdir_high_fmt sd_hi_fmt;
}md_sdir_high_t;
struct md_sdir_low_shared_fmt {
/* The meaning of lower directory, shared */
unsigned short sds_lo_bvec : 5,
sds_lo_unused: 1,
sds_lo_state : 3,
sds_lo_prio : 1,
sds_lo_ax : 1,
sds_lo_ecc : 5;
};
struct md_sdir_low_exclusive_fmt {
/* The meaning of lower directory, exclusive */
unsigned short sde_lo_ptr : 6,
sde_lo_state : 3,
sde_lo_prio : 1,
sde_lo_ax : 1,
sde_lo_ecc : 5;
};
typedef union md_sdir_low {
/* The 16 bits of standard directory, lower word */
unsigned short sd_lo_val;
struct md_sdir_low_exclusive_fmt sde_lo_fmt;
struct md_sdir_low_shared_fmt sds_lo_fmt;
}md_sdir_low_t;
struct md_pdir_high_fmt {
u64 pd_hi_unused : 16,
pd_hi_bvec : 38,
pd_hi_unused1 : 3,
pd_hi_ecc : 7;
};
typedef union md_pdir_high {
/* The 48 bits of standard directory, upper word */
u64 pd_hi_val;
struct md_pdir_high_fmt pd_hi_fmt;
}md_pdir_high_t;
struct md_pdir_low_shared_fmt {
/* The meaning of lower directory, shared */
u64 pds_lo_unused : 16,
pds_lo_bvec : 26,
pds_lo_cnt : 6,
pds_lo_state : 3,
pds_lo_ste : 1,
pds_lo_prio : 4,
pds_lo_ax : 1,
pds_lo_ecc : 7;
};
struct md_pdir_low_exclusive_fmt {
/* The meaning of lower directory, exclusive */
u64 pde_lo_unused : 31,
pde_lo_ptr : 11,
pde_lo_unused1 : 6,
pde_lo_state : 3,
pde_lo_ste : 1,
pde_lo_prio : 4,
pde_lo_ax : 1,
pde_lo_ecc : 7;
};
typedef union md_pdir_loent {
/* The 48 bits of premium directory, lower word */
u64 pd_lo_val;
struct md_pdir_low_exclusive_fmt pde_lo_fmt;
struct md_pdir_low_shared_fmt pds_lo_fmt;
}md_pdir_low_t;
/*
* the following two "union" definitions and two
* "struct" definitions are used in vmdump.c to
* represent directory memory information.
*/
typedef union md_dir_high {
md_sdir_high_t md_sdir_high;
md_pdir_high_t md_pdir_high;
} md_dir_high_t;
typedef union md_dir_low {
md_sdir_low_t md_sdir_low;
md_pdir_low_t md_pdir_low;
} md_dir_low_t;
typedef struct bddir_entry {
md_dir_low_t md_dir_low;
md_dir_high_t md_dir_high;
} bddir_entry_t;
typedef struct dir_mem_entry {
u64 prcpf[MAX_REGIONS];
bddir_entry_t directory_words[MD_PAGE_SIZE/CACHE_SLINE_SIZE];
} dir_mem_entry_t;
typedef union md_perf_sel {
u64 perf_sel_reg;
struct {
u64 perf_rsvd : 60,
perf_en : 1,
perf_sel : 3;
} perf_sel_bits;
} md_perf_sel_t;
typedef union md_perf_cnt {
u64 perf_cnt;
struct {
u64 perf_rsvd : 44,
perf_cnt : 20;
} perf_cnt_bits;
} md_perf_cnt_t;
#endif /* !__ASSEMBLY__ */
#define DIR_ERROR_VALID_MASK 0xe000000000000000
#define DIR_ERROR_VALID_SHFT 61
#define DIR_ERROR_VALID_UCE 0x8000000000000000
#define DIR_ERROR_VALID_AE 0x4000000000000000
#define DIR_ERROR_VALID_CE 0x2000000000000000
#define MEM_ERROR_VALID_MASK 0xc000000000000000
#define MEM_ERROR_VALID_SHFT 62
#define MEM_ERROR_VALID_UCE 0x8000000000000000
#define MEM_ERROR_VALID_CE 0x4000000000000000
#define PROTO_ERROR_VALID_MASK 0x8000000000000000
#define MISC_ERROR_VALID_MASK 0x3ff
/*
* Mask for hspec address that is stored in the dir error register.
* This represents bits 29 through 3.
*/
#define DIR_ERR_HSPEC_MASK 0x3ffffff8
#define ERROR_HSPEC_MASK 0x3ffffff8
#define ERROR_HSPEC_SHFT 3
#define ERROR_ADDR_MASK 0xfffffff8
#define ERROR_ADDR_SHFT 3
/*
* MD_MISC_ERROR register defines.
*/
#define MMCE_VALID_MASK 0x3ff
#define MMCE_ILL_MSG_SHFT 8
#define MMCE_ILL_MSG_MASK (UINT64_CAST 0x03 << MMCE_ILL_MSG_SHFT)
#define MMCE_ILL_REV_SHFT 6
#define MMCE_ILL_REV_MASK (UINT64_CAST 0x03 << MMCE_ILL_REV_SHFT)
#define MMCE_LONG_PACK_SHFT 4
#define MMCE_LONG_PACK_MASK (UINT64_CAST 0x03 << MMCE_lONG_PACK_SHFT)
#define MMCE_SHORT_PACK_SHFT 2
#define MMCE_SHORT_PACK_MASK (UINT64_CAST 0x03 << MMCE_SHORT_PACK_SHFT)
#define MMCE_BAD_DATA_SHFT 0
#define MMCE_BAD_DATA_MASK (UINT64_CAST 0x03 << MMCE_BAD_DATA_SHFT)
#define MD_PERF_COUNTERS 6
#define MD_PERF_SETS 6
#define MEM_DIMM_MASK 0xe0000000
#define MEM_DIMM_SHFT 29
#endif /* _ASM_SN_SN0_HUBMD_H */
include/asm-mips/sn/sn0/hubni.h
+255
View File
@@ -0,0 +1,255 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Derived from IRIX <sys/SN/SN0/hubni.h>, Revision 1.27.
*
* Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc.
* Copyright (C) 1999 by Ralf Baechle
*/
#ifndef _ASM_SGI_SN0_HUBNI_H
#define _ASM_SGI_SN0_HUBNI_H
#ifndef __ASSEMBLY__
#include <linux/types.h>
#endif
/*
* Hub Network Interface registers
*
* All registers in this file are subject to change until Hub chip tapeout.
*/
#define NI_BASE 0x600000
#define NI_BASE_TABLES 0x630000
#define NI_STATUS_REV_ID 0x600000 /* Hub network status, rev, and ID */
#define NI_PORT_RESET 0x600008 /* Reset the network interface */
#define NI_PROTECTION 0x600010 /* NI register access permissions */
#define NI_GLOBAL_PARMS 0x600018 /* LLP parameters */
#define NI_SCRATCH_REG0 0x600100 /* Scratch register 0 (64 bits) */
#define NI_SCRATCH_REG1 0x600108 /* Scratch register 1 (64 bits) */
#define NI_DIAG_PARMS 0x600110 /* Parameters for diags */
#define NI_VECTOR_PARMS 0x600200 /* Vector PIO routing parameters */
#define NI_VECTOR 0x600208 /* Vector PIO route */
#define NI_VECTOR_DATA 0x600210 /* Vector PIO data */
#define NI_VECTOR_STATUS 0x600300 /* Vector PIO return status */
#define NI_RETURN_VECTOR 0x600308 /* Vector PIO return vector */
#define NI_VECTOR_READ_DATA 0x600310 /* Vector PIO read data */
#define NI_VECTOR_CLEAR 0x600380 /* Vector PIO read & clear status */
#define NI_IO_PROTECT 0x600400 /* PIO protection bits */
#define NI_IO_PROT_OVRRD 0x600408 /* PIO protection bit override */
#define NI_AGE_CPU0_MEMORY 0x600500 /* CPU 0 memory age control */
#define NI_AGE_CPU0_PIO 0x600508 /* CPU 0 PIO age control */
#define NI_AGE_CPU1_MEMORY 0x600510 /* CPU 1 memory age control */
#define NI_AGE_CPU1_PIO 0x600518 /* CPU 1 PIO age control */
#define NI_AGE_GBR_MEMORY 0x600520 /* GBR memory age control */
#define NI_AGE_GBR_PIO 0x600528 /* GBR PIO age control */
#define NI_AGE_IO_MEMORY 0x600530 /* IO memory age control */
#define NI_AGE_IO_PIO 0x600538 /* IO PIO age control */
#define NI_AGE_REG_MIN NI_AGE_CPU0_MEMORY
#define NI_AGE_REG_MAX NI_AGE_IO_PIO
#define NI_PORT_PARMS 0x608000 /* LLP Parameters */
#define NI_PORT_ERROR 0x608008 /* LLP Errors */
#define NI_PORT_ERROR_CLEAR 0x608088 /* Clear the error bits */
#define NI_META_TABLE0 0x638000 /* First meta routing table entry */
#define NI_META_TABLE(_x) (NI_META_TABLE0 + (8 * (_x)))
#define NI_META_ENTRIES 32
#define NI_LOCAL_TABLE0 0x638100 /* First local routing table entry */
#define NI_LOCAL_TABLE(_x) (NI_LOCAL_TABLE0 + (8 * (_x)))
#define NI_LOCAL_ENTRIES 16
/*
* NI_STATUS_REV_ID mask and shift definitions
* Have to use UINT64_CAST instead of 'L' suffix, for assembler.
*/
#define NSRI_8BITMODE_SHFT 30
#define NSRI_8BITMODE_MASK (UINT64_CAST 0x1 << 30)
#define NSRI_LINKUP_SHFT 29
#define NSRI_LINKUP_MASK (UINT64_CAST 0x1 << 29)
#define NSRI_DOWNREASON_SHFT 28 /* 0=failed, 1=never came */
#define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28) /* out of reset. */
#define NSRI_MORENODES_SHFT 18
#define NSRI_MORENODES_MASK (UINT64_CAST 1 << 18) /* Max. # of nodes */
#define MORE_MEMORY 0
#define MORE_NODES 1
#define NSRI_REGIONSIZE_SHFT 17
#define NSRI_REGIONSIZE_MASK (UINT64_CAST 1 << 17) /* Granularity */
#define REGIONSIZE_FINE 1
#define REGIONSIZE_COARSE 0
#define NSRI_NODEID_SHFT 8
#define NSRI_NODEID_MASK (UINT64_CAST 0x1ff << 8)/* Node (Hub) ID */
#define NSRI_REV_SHFT 4
#define NSRI_REV_MASK (UINT64_CAST 0xf << 4) /* Chip Revision */
#define NSRI_CHIPID_SHFT 0
#define NSRI_CHIPID_MASK (UINT64_CAST 0xf) /* Chip type ID */
/*
* In fine mode, each node is a region. In coarse mode, there are
* eight nodes per region.
*/
#define NASID_TO_FINEREG_SHFT 0
#define NASID_TO_COARSEREG_SHFT 3
/* NI_PORT_RESET mask definitions */
#define NPR_PORTRESET (UINT64_CAST 1 << 7) /* Send warm reset */
#define NPR_LINKRESET (UINT64_CAST 1 << 1) /* Send link reset */
#define NPR_LOCALRESET (UINT64_CAST 1) /* Reset entire hub */
/* NI_PROTECTION mask and shift definitions */
#define NPROT_RESETOK (UINT64_CAST 1)
/* NI_GLOBAL_PARMS mask and shift definitions */
#define NGP_MAXRETRY_SHFT 48 /* Maximum retries */
#define NGP_MAXRETRY_MASK (UINT64_CAST 0x3ff << 48)
#define NGP_TAILTOWRAP_SHFT 32 /* Tail timeout wrap */
#define NGP_TAILTOWRAP_MASK (UINT64_CAST 0xffff << 32)
#define NGP_CREDITTOVAL_SHFT 16 /* Tail timeout wrap */
#define NGP_CREDITTOVAL_MASK (UINT64_CAST 0xf << 16)
#define NGP_TAILTOVAL_SHFT 4 /* Tail timeout value */
#define NGP_TAILTOVAL_MASK (UINT64_CAST 0xf << 4)
/* NI_DIAG_PARMS mask and shift definitions */
#define NDP_PORTTORESET (UINT64_CAST 1 << 18) /* Port tmout reset */
#define NDP_LLP8BITMODE (UINT64_CAST 1 << 12) /* LLP 8-bit mode */
#define NDP_PORTDISABLE (UINT64_CAST 1 << 6) /* Port disable */
#define NDP_SENDERROR (UINT64_CAST 1) /* Send data error */
/*
* NI_VECTOR_PARMS mask and shift definitions.
* TYPE may be any of the first four PIOTYPEs defined under NI_VECTOR_STATUS.
*/
#define NVP_PIOID_SHFT 40
#define NVP_PIOID_MASK (UINT64_CAST 0x3ff << 40)
#define NVP_WRITEID_SHFT 32
#define NVP_WRITEID_MASK (UINT64_CAST 0xff << 32)
#define NVP_ADDRESS_MASK (UINT64_CAST 0xffff8) /* Bits 19:3 */
#define NVP_TYPE_SHFT 0
#define NVP_TYPE_MASK (UINT64_CAST 0x3)
/* NI_VECTOR_STATUS mask and shift definitions */
#define NVS_VALID (UINT64_CAST 1 << 63)
#define NVS_OVERRUN (UINT64_CAST 1 << 62)
#define NVS_TARGET_SHFT 51
#define NVS_TARGET_MASK (UINT64_CAST 0x3ff << 51)
#define NVS_PIOID_SHFT 40
#define NVS_PIOID_MASK (UINT64_CAST 0x3ff << 40)
#define NVS_WRITEID_SHFT 32
#define NVS_WRITEID_MASK (UINT64_CAST 0xff << 32)
#define NVS_ADDRESS_MASK (UINT64_CAST 0xfffffff8) /* Bits 31:3 */
#define NVS_TYPE_SHFT 0
#define NVS_TYPE_MASK (UINT64_CAST 0x7)
#define NVS_ERROR_MASK (UINT64_CAST 0x4) /* bit set means error */
#define PIOTYPE_READ 0 /* VECTOR_PARMS and VECTOR_STATUS */
#define PIOTYPE_WRITE 1 /* VECTOR_PARMS and VECTOR_STATUS */
#define PIOTYPE_UNDEFINED 2 /* VECTOR_PARMS and VECTOR_STATUS */
#define PIOTYPE_EXCHANGE 3 /* VECTOR_PARMS and VECTOR_STATUS */
#define PIOTYPE_ADDR_ERR 4 /* VECTOR_STATUS only */
#define PIOTYPE_CMD_ERR 5 /* VECTOR_STATUS only */
#define PIOTYPE_PROT_ERR 6 /* VECTOR_STATUS only */
#define PIOTYPE_UNKNOWN 7 /* VECTOR_STATUS only */
/* NI_AGE_XXX mask and shift definitions */
#define NAGE_VCH_SHFT 10
#define NAGE_VCH_MASK (UINT64_CAST 3 << 10)
#define NAGE_CC_SHFT 8
#define NAGE_CC_MASK (UINT64_CAST 3 << 8)
#define NAGE_AGE_SHFT 0
#define NAGE_AGE_MASK (UINT64_CAST 0xff)
#define NAGE_MASK (NAGE_VCH_MASK | NAGE_CC_MASK | NAGE_AGE_MASK)
#define VCHANNEL_A 0
#define VCHANNEL_B 1
#define VCHANNEL_ANY 2
/* NI_PORT_PARMS mask and shift definitions */
#define NPP_NULLTO_SHFT 10
#define NPP_NULLTO_MASK (UINT64_CAST 0x3f << 16)
#define NPP_MAXBURST_SHFT 0
#define NPP_MAXBURST_MASK (UINT64_CAST 0x3ff)
#define NPP_RESET_DFLT_HUB20 ((UINT64_CAST 1 << NPP_NULLTO_SHFT) | \
(UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
#define NPP_RESET_DEFAULTS ((UINT64_CAST 6 << NPP_NULLTO_SHFT) | \
(UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
/* NI_PORT_ERROR mask and shift definitions */
#define NPE_LINKRESET (UINT64_CAST 1 << 37)
#define NPE_INTERNALERROR (UINT64_CAST 1 << 36)
#define NPE_BADMESSAGE (UINT64_CAST 1 << 35)
#define NPE_BADDEST (UINT64_CAST 1 << 34)
#define NPE_FIFOOVERFLOW (UINT64_CAST 1 << 33)
#define NPE_CREDITTO_SHFT 28
#define NPE_CREDITTO_MASK (UINT64_CAST 0xf << 28)
#define NPE_TAILTO_SHFT 24
#define NPE_TAILTO_MASK (UINT64_CAST 0xf << 24)
#define NPE_RETRYCOUNT_SHFT 16
#define NPE_RETRYCOUNT_MASK (UINT64_CAST 0xff << 16)
#define NPE_CBERRCOUNT_SHFT 8
#define NPE_CBERRCOUNT_MASK (UINT64_CAST 0xff << 8)
#define NPE_SNERRCOUNT_SHFT 0
#define NPE_SNERRCOUNT_MASK (UINT64_CAST 0xff << 0)
#define NPE_MASK 0x3effffffff
#define NPE_COUNT_MAX 0xff
#define NPE_FATAL_ERRORS (NPE_LINKRESET | NPE_INTERNALERROR | \
NPE_BADMESSAGE | NPE_BADDEST | \
NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \
NPE_TAILTO_MASK)
/* NI_META_TABLE mask and shift definitions */
#define NMT_EXIT_PORT_MASK (UINT64_CAST 0xf)
/* NI_LOCAL_TABLE mask and shift definitions */
#define NLT_EXIT_PORT_MASK (UINT64_CAST 0xf)
#ifndef __ASSEMBLY__
typedef union hubni_port_error_u {
u64 nipe_reg_value;
struct {
u64 nipe_rsvd: 26, /* unused */
nipe_lnk_reset: 1, /* link reset */
nipe_intl_err: 1, /* internal error */
nipe_bad_msg: 1, /* bad message */
nipe_bad_dest: 1, /* bad dest */
nipe_fifo_ovfl: 1, /* fifo overflow */
nipe_rsvd1: 1, /* unused */
nipe_credit_to: 4, /* credit timeout */
nipe_tail_to: 4, /* tail timeout */
nipe_retry_cnt: 8, /* retry error count */
nipe_cb_cnt: 8, /* checkbit error count */
nipe_sn_cnt: 8; /* sequence number count */
} nipe_fields_s;
} hubni_port_error_t;
#define NI_LLP_RETRY_MAX 0xff
#define NI_LLP_CB_MAX 0xff
#define NI_LLP_SN_MAX 0xff
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_SGI_SN0_HUBNI_H */
include/asm-mips/sn/sn0/hubpi.h
+427
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@@ -0,0 +1,427 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Derived from IRIX <sys/SN/SN0/hubpi.h>, revision 1.28.
*
* Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
* Copyright (C) 1999 by Ralf Baechle
*/
#ifndef _ASM_SN_SN0_HUBPI_H
#define _ASM_SN_SN0_HUBPI_H
#include <linux/types.h>
/*
* Hub I/O interface registers
*
* All registers in this file are subject to change until Hub chip tapeout.
* All register "addresses" are actually offsets. Use the LOCAL_HUB
* or REMOTE_HUB macros to synthesize an actual address
*/
#define PI_BASE 0x000000
/* General protection and control registers */
#define PI_CPU_PROTECT 0x000000 /* CPU Protection */
#define PI_PROT_OVERRD 0x000008 /* Clear CPU Protection bit */
#define PI_IO_PROTECT 0x000010 /* Interrupt Pending Protection */
#define PI_REGION_PRESENT 0x000018 /* Indicates whether region exists */
#define PI_CPU_NUM 0x000020 /* CPU Number ID */
#define PI_CALIAS_SIZE 0x000028 /* Cached Alias Size */
#define PI_MAX_CRB_TIMEOUT 0x000030 /* Maximum Timeout for CRB */
#define PI_CRB_SFACTOR 0x000038 /* Scale factor for CRB timeout */
/* CALIAS values */
#define PI_CALIAS_SIZE_0 0
#define PI_CALIAS_SIZE_4K 1
#define PI_CALIAS_SIZE_8K 2
#define PI_CALIAS_SIZE_16K 3
#define PI_CALIAS_SIZE_32K 4
#define PI_CALIAS_SIZE_64K 5
#define PI_CALIAS_SIZE_128K 6
#define PI_CALIAS_SIZE_256K 7
#define PI_CALIAS_SIZE_512K 8
#define PI_CALIAS_SIZE_1M 9
#define PI_CALIAS_SIZE_2M 10
#define PI_CALIAS_SIZE_4M 11
#define PI_CALIAS_SIZE_8M 12
#define PI_CALIAS_SIZE_16M 13
#define PI_CALIAS_SIZE_32M 14
#define PI_CALIAS_SIZE_64M 15
/* Processor control and status checking */
#define PI_CPU_PRESENT_A 0x000040 /* CPU Present A */
#define PI_CPU_PRESENT_B 0x000048 /* CPU Present B */
#define PI_CPU_ENABLE_A 0x000050 /* CPU Enable A */
#define PI_CPU_ENABLE_B 0x000058 /* CPU Enable B */
#define PI_REPLY_LEVEL 0x000060 /* Reply Level */
#define PI_HARDRESET_BIT 0x020068 /* Bit cleared by s/w on SR */
#define PI_NMI_A 0x000070 /* NMI to CPU A */
#define PI_NMI_B 0x000078 /* NMI to CPU B */
#define PI_NMI_OFFSET (PI_NMI_B - PI_NMI_A)
#define PI_SOFTRESET 0x000080 /* Softreset (to both CPUs) */
/* Regular Interrupt register checking. */
#define PI_INT_PEND_MOD 0x000090 /* Write to set pending ints */
#define PI_INT_PEND0 0x000098 /* Read to get pending ints */
#define PI_INT_PEND1 0x0000a0 /* Read to get pending ints */
#define PI_INT_MASK0_A 0x0000a8 /* Interrupt Mask 0 for CPU A */
#define PI_INT_MASK1_A 0x0000b0 /* Interrupt Mask 1 for CPU A */
#define PI_INT_MASK0_B 0x0000b8 /* Interrupt Mask 0 for CPU B */
#define PI_INT_MASK1_B 0x0000c0 /* Interrupt Mask 1 for CPU B */
#define PI_INT_MASK_OFFSET 0x10 /* Offset from A to B */
/* Crosscall interrupts */
#define PI_CC_PEND_SET_A 0x0000c8 /* CC Interrupt Pending Set, CPU A */
#define PI_CC_PEND_SET_B 0x0000d0 /* CC Interrupt Pending Set, CPU B */
#define PI_CC_PEND_CLR_A 0x0000d8 /* CC Interrupt Pending Clr, CPU A */
#define PI_CC_PEND_CLR_B 0x0000e0 /* CC Interrupt Pending Clr, CPU B */
#define PI_CC_MASK 0x0000e8 /* CC Interrupt mask */
#define PI_INT_SET_OFFSET 0x08 /* Offset from A to B */
/* Realtime Counter and Profiler control registers */
#define PI_RT_COUNT 0x030100 /* Real Time Counter */
#define PI_RT_COMPARE_A 0x000108 /* Real Time Compare A */
#define PI_RT_COMPARE_B 0x000110 /* Real Time Compare B */
#define PI_PROFILE_COMPARE 0x000118 /* L5 int to both cpus when == RTC */
#define PI_RT_PEND_A 0x000120 /* Set if RT int for A pending */
#define PI_RT_PEND_B 0x000128 /* Set if RT int for B pending */
#define PI_PROF_PEND_A 0x000130 /* Set if Prof int for A pending */
#define PI_PROF_PEND_B 0x000138 /* Set if Prof int for B pending */
#define PI_RT_EN_A 0x000140 /* RT int for CPU A enable */
#define PI_RT_EN_B 0x000148 /* RT int for CPU B enable */
#define PI_PROF_EN_A 0x000150 /* PROF int for CPU A enable */
#define PI_PROF_EN_B 0x000158 /* PROF int for CPU B enable */
#define PI_RT_LOCAL_CTRL 0x000160 /* RT control register */
#define PI_RT_FILTER_CTRL 0x000168 /* GCLK Filter control register */
#define PI_COUNT_OFFSET 0x08 /* A to B offset for all counts */
/* Built-In Self Test support */
#define PI_BIST_WRITE_DATA 0x000200 /* BIST write data */
#define PI_BIST_READ_DATA 0x000208 /* BIST read data */
#define PI_BIST_COUNT_TARG 0x000210 /* BIST Count and Target */
#define PI_BIST_READY 0x000218 /* BIST Ready indicator */
#define PI_BIST_SHIFT_LOAD 0x000220 /* BIST control */
#define PI_BIST_SHIFT_UNLOAD 0x000228 /* BIST control */
#define PI_BIST_ENTER_RUN 0x000230 /* BIST control */
/* Graphics control registers */
#define PI_GFX_PAGE_A 0x000300 /* Graphics page A */
#define PI_GFX_CREDIT_CNTR_A 0x000308 /* Graphics credit counter A */
#define PI_GFX_BIAS_A 0x000310 /* Graphics bias A */
#define PI_GFX_INT_CNTR_A 0x000318 /* Graphics interrupt counter A */
#define PI_GFX_INT_CMP_A 0x000320 /* Graphics interrupt comparator A */
#define PI_GFX_PAGE_B 0x000328 /* Graphics page B */
#define PI_GFX_CREDIT_CNTR_B 0x000330 /* Graphics credit counter B */
#define PI_GFX_BIAS_B 0x000338 /* Graphics bias B */
#define PI_GFX_INT_CNTR_B 0x000340 /* Graphics interrupt counter B */
#define PI_GFX_INT_CMP_B 0x000348 /* Graphics interrupt comparator B */
#define PI_GFX_OFFSET (PI_GFX_PAGE_B - PI_GFX_PAGE_A)
#define PI_GFX_PAGE_ENABLE 0x0000010000000000LL
/* Error and timeout registers */
#define PI_ERR_INT_PEND 0x000400 /* Error Interrupt Pending */
#define PI_ERR_INT_MASK_A 0x000408 /* Error Interrupt mask for CPU A */
#define PI_ERR_INT_MASK_B 0x000410 /* Error Interrupt mask for CPU B */
#define PI_ERR_STACK_ADDR_A 0x000418 /* Error stack address for CPU A */
#define PI_ERR_STACK_ADDR_B 0x000420 /* Error stack address for CPU B */
#define PI_ERR_STACK_SIZE 0x000428 /* Error Stack Size */
#define PI_ERR_STATUS0_A 0x000430 /* Error Status 0A */
#define PI_ERR_STATUS0_A_RCLR 0x000438 /* Error Status 0A clear on read */
#define PI_ERR_STATUS1_A 0x000440 /* Error Status 1A */
#define PI_ERR_STATUS1_A_RCLR 0x000448 /* Error Status 1A clear on read */
#define PI_ERR_STATUS0_B 0x000450 /* Error Status 0B */
#define PI_ERR_STATUS0_B_RCLR 0x000458 /* Error Status 0B clear on read */
#define PI_ERR_STATUS1_B 0x000460 /* Error Status 1B */
#define PI_ERR_STATUS1_B_RCLR 0x000468 /* Error Status 1B clear on read */
#define PI_SPOOL_CMP_A 0x000470 /* Spool compare for CPU A */
#define PI_SPOOL_CMP_B 0x000478 /* Spool compare for CPU B */
#define PI_CRB_TIMEOUT_A 0x000480 /* Timed out CRB entries for A */
#define PI_CRB_TIMEOUT_B 0x000488 /* Timed out CRB entries for B */
#define PI_SYSAD_ERRCHK_EN 0x000490 /* Enables SYSAD error checking */
#define PI_BAD_CHECK_BIT_A 0x000498 /* Force SYSAD check bit error */
#define PI_BAD_CHECK_BIT_B 0x0004a0 /* Force SYSAD check bit error */
#define PI_NACK_CNT_A 0x0004a8 /* Consecutive NACK counter */
#define PI_NACK_CNT_B 0x0004b0 /* " " for CPU B */
#define PI_NACK_CMP 0x0004b8 /* NACK count compare */
#define PI_STACKADDR_OFFSET (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A)
#define PI_ERRSTAT_OFFSET (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A)
#define PI_RDCLR_OFFSET (PI_ERR_STATUS0_A_RCLR - PI_ERR_STATUS0_A)
/* Bits in PI_ERR_INT_PEND */
#define PI_ERR_SPOOL_CMP_B 0x00000001 /* Spool end hit high water */
#define PI_ERR_SPOOL_CMP_A 0x00000002
#define PI_ERR_SPUR_MSG_B 0x00000004 /* Spurious message intr. */
#define PI_ERR_SPUR_MSG_A 0x00000008
#define PI_ERR_WRB_TERR_B 0x00000010 /* WRB TERR */
#define PI_ERR_WRB_TERR_A 0x00000020
#define PI_ERR_WRB_WERR_B 0x00000040 /* WRB WERR */
#define PI_ERR_WRB_WERR_A 0x00000080
#define PI_ERR_SYSSTATE_B 0x00000100 /* SysState parity error */
#define PI_ERR_SYSSTATE_A 0x00000200
#define PI_ERR_SYSAD_DATA_B 0x00000400 /* SysAD data parity error */
#define PI_ERR_SYSAD_DATA_A 0x00000800
#define PI_ERR_SYSAD_ADDR_B 0x00001000 /* SysAD addr parity error */
#define PI_ERR_SYSAD_ADDR_A 0x00002000
#define PI_ERR_SYSCMD_DATA_B 0x00004000 /* SysCmd data parity error */
#define PI_ERR_SYSCMD_DATA_A 0x00008000
#define PI_ERR_SYSCMD_ADDR_B 0x00010000 /* SysCmd addr parity error */
#define PI_ERR_SYSCMD_ADDR_A 0x00020000
#define PI_ERR_BAD_SPOOL_B 0x00040000 /* Error spooling to memory */
#define PI_ERR_BAD_SPOOL_A 0x00080000
#define PI_ERR_UNCAC_UNCORR_B 0x00100000 /* Uncached uncorrectable */
#define PI_ERR_UNCAC_UNCORR_A 0x00200000
#define PI_ERR_SYSSTATE_TAG_B 0x00400000 /* SysState tag parity error */
#define PI_ERR_SYSSTATE_TAG_A 0x00800000
#define PI_ERR_MD_UNCORR 0x01000000 /* Must be cleared in MD */
#define PI_ERR_CLEAR_ALL_A 0x00aaaaaa
#define PI_ERR_CLEAR_ALL_B 0x00555555
/*
* The following three macros define all possible error int pends.
*/
#define PI_FATAL_ERR_CPU_A (PI_ERR_SYSSTATE_TAG_A | \
PI_ERR_BAD_SPOOL_A | \
PI_ERR_SYSCMD_ADDR_A | \
PI_ERR_SYSCMD_DATA_A | \
PI_ERR_SYSAD_ADDR_A | \
PI_ERR_SYSAD_DATA_A | \
PI_ERR_SYSSTATE_A)
#define PI_MISC_ERR_CPU_A (PI_ERR_UNCAC_UNCORR_A | \
PI_ERR_WRB_WERR_A | \
PI_ERR_WRB_TERR_A | \
PI_ERR_SPUR_MSG_A | \
PI_ERR_SPOOL_CMP_A)
#define PI_FATAL_ERR_CPU_B (PI_ERR_SYSSTATE_TAG_B | \
PI_ERR_BAD_SPOOL_B | \
PI_ERR_SYSCMD_ADDR_B | \
PI_ERR_SYSCMD_DATA_B | \
PI_ERR_SYSAD_ADDR_B | \
PI_ERR_SYSAD_DATA_B | \
PI_ERR_SYSSTATE_B)
#define PI_MISC_ERR_CPU_B (PI_ERR_UNCAC_UNCORR_B | \
PI_ERR_WRB_WERR_B | \
PI_ERR_WRB_TERR_B | \
PI_ERR_SPUR_MSG_B | \
PI_ERR_SPOOL_CMP_B)
#define PI_ERR_GENERIC (PI_ERR_MD_UNCORR)
/*
* Error types for PI_ERR_STATUS0_[AB] and error stack:
* Use the write types if WRBRRB is 1 else use the read types
*/
/* Fields in PI_ERR_STATUS0_[AB] */
#define PI_ERR_ST0_TYPE_MASK 0x0000000000000007
#define PI_ERR_ST0_TYPE_SHFT 0
#define PI_ERR_ST0_REQNUM_MASK 0x0000000000000038
#define PI_ERR_ST0_REQNUM_SHFT 3
#define PI_ERR_ST0_SUPPL_MASK 0x000000000001ffc0
#define PI_ERR_ST0_SUPPL_SHFT 6
#define PI_ERR_ST0_CMD_MASK 0x0000000001fe0000
#define PI_ERR_ST0_CMD_SHFT 17
#define PI_ERR_ST0_ADDR_MASK 0x3ffffffffe000000
#define PI_ERR_ST0_ADDR_SHFT 25
#define PI_ERR_ST0_OVERRUN_MASK 0x4000000000000000
#define PI_ERR_ST0_OVERRUN_SHFT 62
#define PI_ERR_ST0_VALID_MASK 0x8000000000000000
#define PI_ERR_ST0_VALID_SHFT 63
/* Fields in PI_ERR_STATUS1_[AB] */
#define PI_ERR_ST1_SPOOL_MASK 0x00000000001fffff
#define PI_ERR_ST1_SPOOL_SHFT 0
#define PI_ERR_ST1_TOUTCNT_MASK 0x000000001fe00000
#define PI_ERR_ST1_TOUTCNT_SHFT 21
#define PI_ERR_ST1_INVCNT_MASK 0x0000007fe0000000
#define PI_ERR_ST1_INVCNT_SHFT 29
#define PI_ERR_ST1_CRBNUM_MASK 0x0000038000000000
#define PI_ERR_ST1_CRBNUM_SHFT 39
#define PI_ERR_ST1_WRBRRB_MASK 0x0000040000000000
#define PI_ERR_ST1_WRBRRB_SHFT 42
#define PI_ERR_ST1_CRBSTAT_MASK 0x001ff80000000000
#define PI_ERR_ST1_CRBSTAT_SHFT 43
#define PI_ERR_ST1_MSGSRC_MASK 0xffe0000000000000
#define PI_ERR_ST1_MSGSRC_SHFT 53
/* Fields in the error stack */
#define PI_ERR_STK_TYPE_MASK 0x0000000000000003
#define PI_ERR_STK_TYPE_SHFT 0
#define PI_ERR_STK_SUPPL_MASK 0x0000000000000038
#define PI_ERR_STK_SUPPL_SHFT 3
#define PI_ERR_STK_REQNUM_MASK 0x00000000000001c0
#define PI_ERR_STK_REQNUM_SHFT 6
#define PI_ERR_STK_CRBNUM_MASK 0x0000000000000e00
#define PI_ERR_STK_CRBNUM_SHFT 9
#define PI_ERR_STK_WRBRRB_MASK 0x0000000000001000
#define PI_ERR_STK_WRBRRB_SHFT 12
#define PI_ERR_STK_CRBSTAT_MASK 0x00000000007fe000
#define PI_ERR_STK_CRBSTAT_SHFT 13
#define PI_ERR_STK_CMD_MASK 0x000000007f800000
#define PI_ERR_STK_CMD_SHFT 23
#define PI_ERR_STK_ADDR_MASK 0xffffffff80000000
#define PI_ERR_STK_ADDR_SHFT 31
/* Error type in the error status or stack on Read CRBs */
#define PI_ERR_RD_PRERR 1
#define PI_ERR_RD_DERR 2
#define PI_ERR_RD_TERR 3
/* Error type in the error status or stack on Write CRBs */
#define PI_ERR_WR_WERR 0
#define PI_ERR_WR_PWERR 1
#define PI_ERR_WR_TERR 3
/* Read or Write CRB in error status or stack */
#define PI_ERR_RRB 0
#define PI_ERR_WRB 1
#define PI_ERR_ANY_CRB 2
/* Address masks in the error status and error stack are not the same */
#define ERR_STK_ADDR_SHFT 7
#define ERR_STAT0_ADDR_SHFT 3
#define PI_MIN_STACK_SIZE 4096 /* For figuring out the size to set */
#define PI_STACK_SIZE_SHFT 12 /* 4k */
#define ERR_STACK_SIZE_BYTES(_sz) \
((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0)
#ifndef __ASSEMBLY__
/*
* format of error stack and error status registers.
*/
struct err_stack_format {
u64 sk_addr : 33, /* address */
sk_cmd : 8, /* message command */
sk_crb_sts : 10, /* status from RRB or WRB */
sk_rw_rb : 1, /* RRB == 0, WRB == 1 */
sk_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */
sk_t5_req : 3, /* RRB T5 request number */
sk_suppl : 3, /* lowest 3 bit of supplemental */
sk_err_type: 3; /* error type */
};
typedef union pi_err_stack {
u64 pi_stk_word;
struct err_stack_format pi_stk_fmt;
} pi_err_stack_t;
struct err_status0_format {
u64 s0_valid : 1, /* Valid */
s0_ovr_run : 1, /* Overrun, spooled to memory */
s0_addr : 37, /* address */
s0_cmd : 8, /* message command */
s0_supl : 11, /* message supplemental field */
s0_t5_req : 3, /* RRB T5 request number */
s0_err_type: 3; /* error type */
};
typedef union pi_err_stat0 {
u64 pi_stat0_word;
struct err_status0_format pi_stat0_fmt;
} pi_err_stat0_t;
struct err_status1_format {
u64 s1_src : 11, /* message source */
s1_crb_sts : 10, /* status from RRB or WRB */
s1_rw_rb : 1, /* RRB == 0, WRB == 1 */
s1_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */
s1_inval_cnt:10, /* signed invalidate counter RRB */
s1_to_cnt : 8, /* crb timeout counter */
s1_spl_cnt : 21; /* number spooled to memory */
};
typedef union pi_err_stat1 {
u64 pi_stat1_word;
struct err_status1_format pi_stat1_fmt;
} pi_err_stat1_t;
typedef u64 rtc_time_t;
#endif /* !__ASSEMBLY__ */
/* Bits in PI_SYSAD_ERRCHK_EN */
#define PI_SYSAD_ERRCHK_ECCGEN 0x01 /* Enable ECC generation */
#define PI_SYSAD_ERRCHK_QUALGEN 0x02 /* Enable data quality signal gen. */
#define PI_SYSAD_ERRCHK_SADP 0x04 /* Enable SysAD parity checking */
#define PI_SYSAD_ERRCHK_CMDP 0x08 /* Enable SysCmd parity checking */
#define PI_SYSAD_ERRCHK_STATE 0x10 /* Enable SysState parity checking */
#define PI_SYSAD_ERRCHK_QUAL 0x20 /* Enable data quality checking */
#define PI_SYSAD_CHECK_ALL 0x3f /* Generate and check all signals. */
/* Interrupt pending bits on R10000 */
#define HUB_IP_PEND0 0x0400
#define HUB_IP_PEND1_CC 0x0800
#define HUB_IP_RT 0x1000
#define HUB_IP_PROF 0x2000
#define HUB_IP_ERROR 0x4000
#define HUB_IP_MASK 0x7c00
/* PI_RT_LOCAL_CTRL mask and shift definitions */
#define PRLC_USE_INT_SHFT 16
#define PRLC_USE_INT_MASK (UINT64_CAST 1 << 16)
#define PRLC_USE_INT (UINT64_CAST 1 << 16)
#define PRLC_GCLK_SHFT 15
#define PRLC_GCLK_MASK (UINT64_CAST 1 << 15)
#define PRLC_GCLK (UINT64_CAST 1 << 15)
#define PRLC_GCLK_COUNT_SHFT 8
#define PRLC_GCLK_COUNT_MASK (UINT64_CAST 0x7f << 8)
#define PRLC_MAX_COUNT_SHFT 1
#define PRLC_MAX_COUNT_MASK (UINT64_CAST 0x7f << 1)
#define PRLC_GCLK_EN_SHFT 0
#define PRLC_GCLK_EN_MASK (UINT64_CAST 1)
#define PRLC_GCLK_EN (UINT64_CAST 1)
/* PI_RT_FILTER_CTRL mask and shift definitions */
#if 0
/*
* XXX - This register's definition has changed, but it's only implemented
* in Hub 2.
*/
#define PRFC_DROP_COUNT_SHFT 27
#define PRFC_DROP_COUNT_MASK (UINT64_CAST 0x3ff << 27)
#define PRFC_DROP_CTR_SHFT 18
#define PRFC_DROP_CTR_MASK (UINT64_CAST 0x1ff << 18)
#define PRFC_MASK_ENABLE_SHFT 10
#define PRFC_MASK_ENABLE_MASK (UINT64_CAST 0x7f << 10)
#define PRFC_MASK_CTR_SHFT 2
#define PRFC_MASK_CTR_MASK (UINT64_CAST 0xff << 2)
#define PRFC_OFFSET_SHFT 0
#define PRFC_OFFSET_MASK (UINT64_CAST 3)
#endif /* 0 */
/*
* Bits for NACK_CNT_A/B and NACK_CMP
*/
#define PI_NACK_CNT_EN_SHFT 20
#define PI_NACK_CNT_EN_MASK 0x100000
#define PI_NACK_CNT_MASK 0x0fffff
#define PI_NACK_CNT_MAX 0x0fffff
#endif /* _ASM_SN_SN0_HUBPI_H */
include/asm-mips/sn/sn0/ip27.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Derived from IRIX <sys/SN/SN0/IP27.h>.
*
* Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
* Copyright (C) 1999 by Ralf Baechle
*/
#ifndef _ASM_SN_SN0_IP27_H
#define _ASM_SN_SN0_IP27_H
#include <asm/mipsregs.h>
/*
* Simple definitions for the masks which remove SW bits from pte.
*/
#define TLBLO_HWBITSHIFT 0 /* Shift value, for masking */
#ifndef __ASSEMBLY__
#define CAUSE_BERRINTR IE_IRQ5
#define ECCF_CACHE_ERR 0
#define ECCF_TAGLO 1
#define ECCF_ECC 2
#define ECCF_ERROREPC 3
#define ECCF_PADDR 4
#define ECCF_SIZE (5 * sizeof(long))
#endif /* !__ASSEMBLY__ */
#ifdef __ASSEMBLY__
/*
* KL_GET_CPUNUM (similar to EV_GET_SPNUM for EVEREST platform) reads
* the processor number of the calling processor. The proc parameters
* must be a register.
*/
#define KL_GET_CPUNUM(proc) \
dli proc, LOCAL_HUB(0); \
ld proc, PI_CPU_NUM(proc)
#endif /* __ASSEMBLY__ */
/*
* R10000 status register interrupt bit mask usage for IP27.
*/
#define SRB_SWTIMO IE_SW0 /* 0x0100 */
#define SRB_NET IE_SW1 /* 0x0200 */
#define SRB_DEV0 IE_IRQ0 /* 0x0400 */
#define SRB_DEV1 IE_IRQ1 /* 0x0800 */
#define SRB_TIMOCLK IE_IRQ2 /* 0x1000 */
#define SRB_PROFCLK IE_IRQ3 /* 0x2000 */
#define SRB_ERR IE_IRQ4 /* 0x4000 */
#define SRB_SCHEDCLK IE_IRQ5 /* 0x8000 */
#define SR_IBIT_HI SRB_DEV0
#define SR_IBIT_PROF SRB_PROFCLK
#define SRB_SWTIMO_IDX 0
#define SRB_NET_IDX 1
#define SRB_DEV0_IDX 2
#define SRB_DEV1_IDX 3
#define SRB_TIMOCLK_IDX 4
#define SRB_PROFCLK_IDX 5
#define SRB_ERR_IDX 6
#define SRB_SCHEDCLK_IDX 7
#define NUM_CAUSE_INTRS 8
#define SCACHE_LINESIZE 128
#define SCACHE_LINEMASK (SCACHE_LINESIZE - 1)
#include <asm/sn/addrs.h>
#define LED_CYCLE_MASK 0x0f
#define LED_CYCLE_SHFT 4
#define SEND_NMI(_nasid, _slice) \
REMOTE_HUB_S((_nasid), (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1)
/* Sanity hazzard ... Below all the Origin hacks are following. */
#define SN00_BRIDGE 0x9200000008000000
#define SN00I_BRIDGE0 0x920000000b000000
#define SN00I_BRIDGE1 0x920000000e000000
#define SN00I_BRIDGE2 0x920000000f000000
#endif /* _ASM_SN_SN0_IP27_H */
include/asm-mips/sn/sn0/sn0_fru.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Derived from IRIX <sys/SN/SN0/sn0_fru.h>
*
* Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
* Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
*/
#ifndef _ASM_SN_SN0_SN0_FRU_H
#define _ASM_SN_SN0_SN0_FRU_H
#define MAX_DIMMS 8 /* max # of dimm banks */
#define MAX_PCIDEV 8 /* max # of pci devices on a pci bus */
typedef unsigned char confidence_t;
typedef struct kf_mem_s {
confidence_t km_confidence; /* confidence level that the memory is bad
* is this necessary ?
*/
confidence_t km_dimm[MAX_DIMMS];
/* confidence level that dimm[i] is bad
*I think this is the right number
*/
} kf_mem_t;
typedef struct kf_cpu_s {
confidence_t kc_confidence; /* confidence level that cpu is bad */
confidence_t kc_icache; /* confidence level that instr. cache is bad */
confidence_t kc_dcache; /* confidence level that data cache is bad */
confidence_t kc_scache; /* confidence level that sec. cache is bad */
confidence_t kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */
} kf_cpu_t;
typedef struct kf_pci_bus_s {
confidence_t kpb_belief; /* confidence level that the pci bus is bad */
confidence_t kpb_pcidev_belief[MAX_PCIDEV];
/* confidence level that the pci dev is bad */
} kf_pci_bus_t;
#endif /* _ASM_SN_SN0_SN0_FRU_H */
include/asm-mips/sn/sn_private.h
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#ifndef __ASM_SN_SN_PRIVATE_H
#define __ASM_SN_SN_PRIVATE_H
#include <asm/sn/types.h>
extern nasid_t master_nasid;
extern void cpu_node_probe(void);
extern cnodeid_t get_compact_nodeid(void);
extern void hub_rtc_init(cnodeid_t);
extern void cpu_time_init(void);
extern void per_cpu_init(void);
extern void install_cpu_nmi_handler(int slice);
extern void install_ipi(void);
extern void setup_replication_mask(void);
extern void replicate_kernel_text(void);
extern pfn_t node_getfirstfree(cnodeid_t);
#endif /* __ASM_SN_SN_PRIVATE_H */
include/asm-mips/sn/types.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999 Silicon Graphics, Inc.
* Copyright (C) 1999 by Ralf Baechle
*/
#ifndef _ASM_SN_TYPES_H
#define _ASM_SN_TYPES_H
#include <linux/types.h>
typedef unsigned long cpuid_t;
typedef unsigned long cnodemask_t;
typedef signed short nasid_t; /* node id in numa-as-id space */
typedef signed short cnodeid_t; /* node id in compact-id space */
typedef signed char partid_t; /* partition ID type */
typedef signed short moduleid_t; /* user-visible module number type */
typedef signed short cmoduleid_t; /* kernel compact module id type */
typedef unsigned char clusterid_t; /* Clusterid of the cell */
typedef unsigned long pfn_t;
typedef dev_t vertex_hdl_t; /* hardware graph vertex handle */
#endif /* _ASM_SN_TYPES_H */