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Merge tag 'v3.14-rc4' into next

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Merge with Linux 3.14-rc4 to bring devm_request_any_context_irq().
This commit is contained in:
Dmitry Torokhov
2014-03-01 10:31:53 -08:00
parent 7fb45edba8 cfbf8d4857
commit 04421fe267
10279 changed files with 559449 additions and 218608 deletions
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include/uapi/asm-generic/ipcbuf.h
+2 -2
View File
@@ -27,8 +27,8 @@ struct ipc64_perm {
unsigned char __pad1[4 - sizeof(__kernel_mode_t)];
unsigned short seq;
unsigned short __pad2;
unsigned long __unused1;
unsigned long __unused2;
__kernel_ulong_t __unused1;
__kernel_ulong_t __unused2;
};
#endif /* __ASM_GENERIC_IPCBUF_H */
include/uapi/asm-generic/msgbuf.h
+5 -5
View File
@@ -35,13 +35,13 @@ struct msqid64_ds {
#if __BITS_PER_LONG != 64
unsigned long __unused3;
#endif
unsigned long msg_cbytes; /* current number of bytes on queue */
unsigned long msg_qnum; /* number of messages in queue */
unsigned long msg_qbytes; /* max number of bytes on queue */
__kernel_ulong_t msg_cbytes; /* current number of bytes on queue */
__kernel_ulong_t msg_qnum; /* number of messages in queue */
__kernel_ulong_t msg_qbytes; /* max number of bytes on queue */
__kernel_pid_t msg_lspid; /* pid of last msgsnd */
__kernel_pid_t msg_lrpid; /* last receive pid */
unsigned long __unused4;
unsigned long __unused5;
__kernel_ulong_t __unused4;
__kernel_ulong_t __unused5;
};
#endif /* __ASM_GENERIC_MSGBUF_H */
include/uapi/asm-generic/shmbuf.h
+12 -12
View File
@@ -39,21 +39,21 @@ struct shmid64_ds {
#endif
__kernel_pid_t shm_cpid; /* pid of creator */
__kernel_pid_t shm_lpid; /* pid of last operator */
unsigned long shm_nattch; /* no. of current attaches */
unsigned long __unused4;
unsigned long __unused5;
__kernel_ulong_t shm_nattch; /* no. of current attaches */
__kernel_ulong_t __unused4;
__kernel_ulong_t __unused5;
};
struct shminfo64 {
unsigned long shmmax;
unsigned long shmmin;
unsigned long shmmni;
unsigned long shmseg;
unsigned long shmall;
unsigned long __unused1;
unsigned long __unused2;
unsigned long __unused3;
unsigned long __unused4;
__kernel_ulong_t shmmax;
__kernel_ulong_t shmmin;
__kernel_ulong_t shmmni;
__kernel_ulong_t shmseg;
__kernel_ulong_t shmall;
__kernel_ulong_t __unused1;
__kernel_ulong_t __unused2;
__kernel_ulong_t __unused3;
__kernel_ulong_t __unused4;
};
#endif /* __ASM_GENERIC_SHMBUF_H */
include/uapi/asm-generic/socket.h
+2
View File
@@ -80,4 +80,6 @@
#define SO_MAX_PACING_RATE 47
#define SO_BPF_EXTENSIONS 48
#endif /* __ASM_GENERIC_SOCKET_H */
include/uapi/asm-generic/statfs.h
+1 -1
View File
@@ -13,7 +13,7 @@
*/
#ifndef __statfs_word
#if __BITS_PER_LONG == 64
#define __statfs_word long
#define __statfs_word __kernel_long_t
#else
#define __statfs_word __u32
#endif
include/uapi/asm-generic/types.h
+1 -2
View File
@@ -1,8 +1,7 @@
#ifndef _ASM_GENERIC_TYPES_H
#define _ASM_GENERIC_TYPES_H
/*
* int-ll64 is used practically everywhere now,
* so use it as a reasonable default.
* int-ll64 is used everywhere now.
*/
#include <asm-generic/int-ll64.h>
include/uapi/drm/drm.h
+2 -1
View File
@@ -181,7 +181,6 @@ enum drm_map_type {
_DRM_AGP = 3, /**< AGP/GART */
_DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
_DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
_DRM_GEM = 6, /**< GEM object (obsolete) */
};
/**
@@ -620,6 +619,8 @@ struct drm_gem_open {
#define DRM_PRIME_CAP_EXPORT 0x2
#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
#define DRM_CAP_CURSOR_WIDTH 0x8
#define DRM_CAP_CURSOR_HEIGHT 0x9
/** DRM_IOCTL_GET_CAP ioctl argument type */
struct drm_get_cap {
include/uapi/drm/i915_drm.h
+20 -1
View File
@@ -222,6 +222,7 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_GEM_SET_CACHING 0x2f
#define DRM_I915_GEM_GET_CACHING 0x30
#define DRM_I915_REG_READ 0x31
#define DRM_I915_GET_RESET_STATS 0x32
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -271,6 +272,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
/* Allow drivers to submit batchbuffers directly to hardware, relying
* on the security mechanisms provided by hardware.
@@ -719,7 +721,7 @@ struct drm_i915_gem_execbuffer2 {
*/
#define I915_EXEC_IS_PINNED (1<<10)
/** Provide a hint to the kernel that the command stream and auxilliary
/** Provide a hint to the kernel that the command stream and auxiliary
* state buffers already holds the correct presumed addresses and so the
* relocation process may be skipped if no buffers need to be moved in
* preparation for the execbuffer.
@@ -1030,4 +1032,21 @@ struct drm_i915_reg_read {
__u64 offset;
__u64 val; /* Return value */
};
struct drm_i915_reset_stats {
__u32 ctx_id;
__u32 flags;
/* All resets since boot/module reload, for all contexts */
__u32 reset_count;
/* Number of batches lost when active in GPU, for this context */
__u32 batch_active;
/* Number of batches lost pending for execution, for this context */
__u32 batch_pending;
__u32 pad;
};
#endif /* _UAPI_I915_DRM_H_ */
include/uapi/drm/radeon_drm.h
+4
View File
@@ -983,6 +983,10 @@ struct drm_radeon_cs {
#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17
/* CIK macrotile mode array */
#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18
/* query the number of render backends */
#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19
/* max engine clock - needed for OpenCL */
#define RADEON_INFO_MAX_SCLK 0x1a
struct drm_radeon_info {
include/uapi/drm/vmwgfx_drm.h
+262
View File
@@ -28,6 +28,10 @@
#ifndef __VMWGFX_DRM_H__
#define __VMWGFX_DRM_H__
#ifndef __KERNEL__
#include <drm.h>
#endif
#define DRM_VMW_MAX_SURFACE_FACES 6
#define DRM_VMW_MAX_MIP_LEVELS 24
@@ -55,6 +59,11 @@
#define DRM_VMW_PRESENT 18
#define DRM_VMW_PRESENT_READBACK 19
#define DRM_VMW_UPDATE_LAYOUT 20
#define DRM_VMW_CREATE_SHADER 21
#define DRM_VMW_UNREF_SHADER 22
#define DRM_VMW_GB_SURFACE_CREATE 23
#define DRM_VMW_GB_SURFACE_REF 24
#define DRM_VMW_SYNCCPU 25
/*************************************************************************/
/**
@@ -75,6 +84,10 @@
#define DRM_VMW_PARAM_FIFO_CAPS 4
#define DRM_VMW_PARAM_MAX_FB_SIZE 5
#define DRM_VMW_PARAM_FIFO_HW_VERSION 6
#define DRM_VMW_PARAM_MAX_SURF_MEMORY 7
#define DRM_VMW_PARAM_3D_CAPS_SIZE 8
#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9
#define DRM_VMW_PARAM_MAX_MOB_SIZE 10
/**
* struct drm_vmw_getparam_arg
@@ -787,4 +800,253 @@ struct drm_vmw_update_layout_arg {
uint64_t rects;
};
/*************************************************************************/
/**
* DRM_VMW_CREATE_SHADER - Create shader
*
* Creates a shader and optionally binds it to a dma buffer containing
* the shader byte-code.
*/
/**
* enum drm_vmw_shader_type - Shader types
*/
enum drm_vmw_shader_type {
drm_vmw_shader_type_vs = 0,
drm_vmw_shader_type_ps,
drm_vmw_shader_type_gs
};
/**
* struct drm_vmw_shader_create_arg
*
* @shader_type: Shader type of the shader to create.
* @size: Size of the byte-code in bytes.
* where the shader byte-code starts
* @buffer_handle: Buffer handle identifying the buffer containing the
* shader byte-code
* @shader_handle: On successful completion contains a handle that
* can be used to subsequently identify the shader.
* @offset: Offset in bytes into the buffer given by @buffer_handle,
*
* Input / Output argument to the DRM_VMW_CREATE_SHADER Ioctl.
*/
struct drm_vmw_shader_create_arg {
enum drm_vmw_shader_type shader_type;
uint32_t size;
uint32_t buffer_handle;
uint32_t shader_handle;
uint64_t offset;
};
/*************************************************************************/
/**
* DRM_VMW_UNREF_SHADER - Unreferences a shader
*
* Destroys a user-space reference to a shader, optionally destroying
* it.
*/
/**
* struct drm_vmw_shader_arg
*
* @handle: Handle identifying the shader to destroy.
*
* Input argument to the DRM_VMW_UNREF_SHADER ioctl.
*/
struct drm_vmw_shader_arg {
uint32_t handle;
uint32_t pad64;
};
/*************************************************************************/
/**
* DRM_VMW_GB_SURFACE_CREATE - Create a host guest-backed surface.
*
* Allocates a surface handle and queues a create surface command
* for the host on the first use of the surface. The surface ID can
* be used as the surface ID in commands referencing the surface.
*/
/**
* enum drm_vmw_surface_flags
*
* @drm_vmw_surface_flag_shareable: Whether the surface is shareable
* @drm_vmw_surface_flag_scanout: Whether the surface is a scanout
* surface.
* @drm_vmw_surface_flag_create_buffer: Create a backup buffer if none is
* given.
*/
enum drm_vmw_surface_flags {
drm_vmw_surface_flag_shareable = (1 << 0),
drm_vmw_surface_flag_scanout = (1 << 1),
drm_vmw_surface_flag_create_buffer = (1 << 2)
};
/**
* struct drm_vmw_gb_surface_create_req
*
* @svga3d_flags: SVGA3d surface flags for the device.
* @format: SVGA3d format.
* @mip_level: Number of mip levels for all faces.
* @drm_surface_flags Flags as described above.
* @multisample_count Future use. Set to 0.
* @autogen_filter Future use. Set to 0.
* @buffer_handle Buffer handle of backup buffer. SVGA3D_INVALID_ID
* if none.
* @base_size Size of the base mip level for all faces.
*
* Input argument to the DRM_VMW_GB_SURFACE_CREATE Ioctl.
* Part of output argument for the DRM_VMW_GB_SURFACE_REF Ioctl.
*/
struct drm_vmw_gb_surface_create_req {
uint32_t svga3d_flags;
uint32_t format;
uint32_t mip_levels;
enum drm_vmw_surface_flags drm_surface_flags;
uint32_t multisample_count;
uint32_t autogen_filter;
uint32_t buffer_handle;
uint32_t pad64;
struct drm_vmw_size base_size;
};
/**
* struct drm_vmw_gb_surface_create_rep
*
* @handle: Surface handle.
* @backup_size: Size of backup buffers for this surface.
* @buffer_handle: Handle of backup buffer. SVGA3D_INVALID_ID if none.
* @buffer_size: Actual size of the buffer identified by
* @buffer_handle
* @buffer_map_handle: Offset into device address space for the buffer
* identified by @buffer_handle.
*
* Part of output argument for the DRM_VMW_GB_SURFACE_REF ioctl.
* Output argument for the DRM_VMW_GB_SURFACE_CREATE ioctl.
*/
struct drm_vmw_gb_surface_create_rep {
uint32_t handle;
uint32_t backup_size;
uint32_t buffer_handle;
uint32_t buffer_size;
uint64_t buffer_map_handle;
};
/**
* union drm_vmw_gb_surface_create_arg
*
* @req: Input argument as described above.
* @rep: Output argument as described above.
*
* Argument to the DRM_VMW_GB_SURFACE_CREATE ioctl.
*/
union drm_vmw_gb_surface_create_arg {
struct drm_vmw_gb_surface_create_rep rep;
struct drm_vmw_gb_surface_create_req req;
};
/*************************************************************************/
/**
* DRM_VMW_GB_SURFACE_REF - Reference a host surface.
*
* Puts a reference on a host surface with a given handle, as previously
* returned by the DRM_VMW_GB_SURFACE_CREATE ioctl.
* A reference will make sure the surface isn't destroyed while we hold
* it and will allow the calling client to use the surface handle in
* the command stream.
*
* On successful return, the Ioctl returns the surface information given
* to and returned from the DRM_VMW_GB_SURFACE_CREATE ioctl.
*/
/**
* struct drm_vmw_gb_surface_reference_arg
*
* @creq: The data used as input when the surface was created, as described
* above at "struct drm_vmw_gb_surface_create_req"
* @crep: Additional data output when the surface was created, as described
* above at "struct drm_vmw_gb_surface_create_rep"
*
* Output Argument to the DRM_VMW_GB_SURFACE_REF ioctl.
*/
struct drm_vmw_gb_surface_ref_rep {
struct drm_vmw_gb_surface_create_req creq;
struct drm_vmw_gb_surface_create_rep crep;
};
/**
* union drm_vmw_gb_surface_reference_arg
*
* @req: Input data as described above at "struct drm_vmw_surface_arg"
* @rep: Output data as described above at "struct drm_vmw_gb_surface_ref_rep"
*
* Argument to the DRM_VMW_GB_SURFACE_REF Ioctl.
*/
union drm_vmw_gb_surface_reference_arg {
struct drm_vmw_gb_surface_ref_rep rep;
struct drm_vmw_surface_arg req;
};
/*************************************************************************/
/**
* DRM_VMW_SYNCCPU - Sync a DMA buffer / MOB for CPU access.
*
* Idles any previously submitted GPU operations on the buffer and
* by default blocks command submissions that reference the buffer.
* If the file descriptor used to grab a blocking CPU sync is closed, the
* cpu sync is released.
* The flags argument indicates how the grab / release operation should be
* performed:
*/
/**
* enum drm_vmw_synccpu_flags - Synccpu flags:
*
* @drm_vmw_synccpu_read: Sync for read. If sync is done for read only, it's a
* hint to the kernel to allow command submissions that references the buffer
* for read-only.
* @drm_vmw_synccpu_write: Sync for write. Block all command submissions
* referencing this buffer.
* @drm_vmw_synccpu_dontblock: Dont wait for GPU idle, but rather return
* -EBUSY should the buffer be busy.
* @drm_vmw_synccpu_allow_cs: Allow command submission that touches the buffer
* while the buffer is synced for CPU. This is similar to the GEM bo idle
* behavior.
*/
enum drm_vmw_synccpu_flags {
drm_vmw_synccpu_read = (1 << 0),
drm_vmw_synccpu_write = (1 << 1),
drm_vmw_synccpu_dontblock = (1 << 2),
drm_vmw_synccpu_allow_cs = (1 << 3)
};
/**
* enum drm_vmw_synccpu_op - Synccpu operations:
*
* @drm_vmw_synccpu_grab: Grab the buffer for CPU operations
* @drm_vmw_synccpu_release: Release a previous grab.
*/
enum drm_vmw_synccpu_op {
drm_vmw_synccpu_grab,
drm_vmw_synccpu_release
};
/**
* struct drm_vmw_synccpu_arg
*
* @op: The synccpu operation as described above.
* @handle: Handle identifying the buffer object.
* @flags: Flags as described above.
*/
struct drm_vmw_synccpu_arg {
enum drm_vmw_synccpu_op op;
enum drm_vmw_synccpu_flags flags;
uint32_t handle;
uint32_t pad64;
};
#endif
include/uapi/linux/Kbuild
+2
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@@ -426,3 +426,5 @@ header-y += x25.h
header-y += xattr.h
header-y += xfrm.h
header-y += hw_breakpoint.h
header-y += zorro.h
header-y += zorro_ids.h
include/uapi/linux/apm_bios.h
+2
View File
@@ -67,6 +67,8 @@ struct apm_bios_info {
#define APM_USER_SUSPEND 0x000a
#define APM_STANDBY_RESUME 0x000b
#define APM_CAPABILITY_CHANGE 0x000c
#define APM_USER_HIBERNATION 0x000d
#define APM_HIBERNATION_RESUME 0x000e
/*
* Error codes
include/uapi/linux/audit.h
+8
View File
@@ -319,6 +319,12 @@ enum {
#define AUDIT_STATUS_PID 0x0004
#define AUDIT_STATUS_RATE_LIMIT 0x0008
#define AUDIT_STATUS_BACKLOG_LIMIT 0x0010
#define AUDIT_STATUS_BACKLOG_WAIT_TIME 0x0020
#define AUDIT_VERSION_BACKLOG_LIMIT 1
#define AUDIT_VERSION_BACKLOG_WAIT_TIME 2
#define AUDIT_VERSION_LATEST AUDIT_VERSION_BACKLOG_WAIT_TIME
/* Failure-to-log actions */
#define AUDIT_FAIL_SILENT 0
#define AUDIT_FAIL_PRINTK 1
@@ -375,6 +381,8 @@ struct audit_status {
__u32 backlog_limit; /* waiting messages limit */
__u32 lost; /* messages lost */
__u32 backlog; /* messages waiting in queue */
__u32 version; /* audit api version number */
__u32 backlog_wait_time;/* message queue wait timeout */
};
struct audit_features {
include/uapi/linux/bcache.h
+2 -1
View File
@@ -39,6 +39,7 @@ static inline void SET_##name(struct bkey *k, unsigned i, __u64 v) \
}
#define KEY_SIZE_BITS 16
#define KEY_MAX_U64S 8
KEY_FIELD(KEY_PTRS, high, 60, 3)
KEY_FIELD(HEADER_SIZE, high, 58, 2)
@@ -118,7 +119,7 @@ static inline struct bkey *bkey_next(const struct bkey *k)
return (struct bkey *) (d + bkey_u64s(k));
}
static inline struct bkey *bkey_last(const struct bkey *k, unsigned nr_keys)
static inline struct bkey *bkey_idx(const struct bkey *k, unsigned nr_keys)
{
__u64 *d = (void *) k;
return (struct bkey *) (d + nr_keys);
include/uapi/linux/btrfs.h
+12
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@@ -184,6 +184,12 @@ struct btrfs_ioctl_fs_info_args {
__u64 reserved[124]; /* pad to 1k */
};
struct btrfs_ioctl_feature_flags {
__u64 compat_flags;
__u64 compat_ro_flags;
__u64 incompat_flags;
};
/* balance control ioctl modes */
#define BTRFS_BALANCE_CTL_PAUSE 1
#define BTRFS_BALANCE_CTL_CANCEL 2
@@ -606,5 +612,11 @@ static inline char *btrfs_err_str(enum btrfs_err_code err_code)
struct btrfs_ioctl_dev_replace_args)
#define BTRFS_IOC_FILE_EXTENT_SAME _IOWR(BTRFS_IOCTL_MAGIC, 54, \
struct btrfs_ioctl_same_args)
#define BTRFS_IOC_GET_FEATURES _IOR(BTRFS_IOCTL_MAGIC, 57, \
struct btrfs_ioctl_feature_flags)
#define BTRFS_IOC_SET_FEATURES _IOW(BTRFS_IOCTL_MAGIC, 57, \
struct btrfs_ioctl_feature_flags[2])
#define BTRFS_IOC_GET_SUPPORTED_FEATURES _IOR(BTRFS_IOCTL_MAGIC, 57, \
struct btrfs_ioctl_feature_flags[3])
#endif /* _UAPI_LINUX_BTRFS_H */
include/uapi/linux/dm-log-userspace.h
+17 -3
View File
@@ -201,11 +201,18 @@
* int (*flush)(struct dm_dirty_log *log);
*
* Payload-to-userspace:
* None.
* If the 'integrated_flush' directive is present in the constructor
* table, the payload is as same as DM_ULOG_MARK_REGION:
* uint64_t [] - region(s) to mark
* else
* None
* Payload-to-kernel:
* None.
*
* No incoming or outgoing payload. Simply flush log state to disk.
* If the 'integrated_flush' option was used during the creation of the
* log, mark region requests are carried as payload in the flush request.
* Piggybacking the mark requests in this way allows for fewer communications
* between kernel and userspace.
*
* When the request has been processed, user-space must return the
* dm_ulog_request to the kernel - setting the 'error' field and clearing
@@ -385,8 +392,15 @@
* version 2: DM_ULOG_CTR allowed to return a string containing a
* device name that is to be registered with DM via
* 'dm_get_device'.
* version 3: DM_ULOG_FLUSH is capable of carrying payload for marking
* regions. This "integrated flush" reduces the number of
* requests between the kernel and userspace by effectively
* merging 'mark' and 'flush' requests. A constructor table
* argument ('integrated_flush') is required to turn this
* feature on, so it is backwards compatible with older
* userspace versions.
*/
#define DM_ULOG_REQUEST_VERSION 2
#define DM_ULOG_REQUEST_VERSION 3
struct dm_ulog_request {
/*
include/uapi/linux/dn.h
+1
View File
@@ -1,6 +1,7 @@
#ifndef _LINUX_DN_H
#define _LINUX_DN_H
#include <linux/ioctl.h>
#include <linux/types.h>
#include <linux/if_ether.h>
include/uapi/linux/fd.h
+2 -1
View File
@@ -185,7 +185,8 @@ enum {
* to clear media change status */
FD_UNUSED_BIT,
FD_DISK_CHANGED_BIT, /* disk has been changed since last i/o */
FD_DISK_WRITABLE_BIT /* disk is writable */
FD_DISK_WRITABLE_BIT, /* disk is writable */
FD_OPEN_SHOULD_FAIL_BIT
};
#define FDSETDRVPRM _IOW(2, 0x90, struct floppy_drive_params)
include/uapi/linux/genwqe/genwqe_card.h
+500
View File
@@ -0,0 +1,500 @@
#ifndef __GENWQE_CARD_H__
#define __GENWQE_CARD_H__
/**
* IBM Accelerator Family 'GenWQE'
*
* (C) Copyright IBM Corp. 2013
*
* Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
* Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
* Author: Michael Jung <mijung@de.ibm.com>
* Author: Michael Ruettger <michael@ibmra.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License (version 2 only)
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* User-space API for the GenWQE card. For debugging and test purposes
* the register addresses are included here too.
*/
#include <linux/types.h>
#include <linux/ioctl.h>
/* Basename of sysfs, debugfs and /dev interfaces */
#define GENWQE_DEVNAME "genwqe"
#define GENWQE_TYPE_ALTERA_230 0x00 /* GenWQE4 Stratix-IV-230 */
#define GENWQE_TYPE_ALTERA_530 0x01 /* GenWQE4 Stratix-IV-530 */
#define GENWQE_TYPE_ALTERA_A4 0x02 /* GenWQE5 A4 Stratix-V-A4 */
#define GENWQE_TYPE_ALTERA_A7 0x03 /* GenWQE5 A7 Stratix-V-A7 */
/* MMIO Unit offsets: Each UnitID occupies a defined address range */
#define GENWQE_UID_OFFS(uid) ((uid) << 24)
#define GENWQE_SLU_OFFS GENWQE_UID_OFFS(0)
#define GENWQE_HSU_OFFS GENWQE_UID_OFFS(1)
#define GENWQE_APP_OFFS GENWQE_UID_OFFS(2)
#define GENWQE_MAX_UNITS 3
/* Common offsets per UnitID */
#define IO_EXTENDED_ERROR_POINTER 0x00000048
#define IO_ERROR_INJECT_SELECTOR 0x00000060
#define IO_EXTENDED_DIAG_SELECTOR 0x00000070
#define IO_EXTENDED_DIAG_READ_MBX 0x00000078
#define IO_EXTENDED_DIAG_MAP(ring) (0x00000500 | ((ring) << 3))
#define GENWQE_EXTENDED_DIAG_SELECTOR(ring, trace) (((ring) << 8) | (trace))
/* UnitID 0: Service Layer Unit (SLU) */
/* SLU: Unit Configuration Register */
#define IO_SLU_UNITCFG 0x00000000
#define IO_SLU_UNITCFG_TYPE_MASK 0x000000000ff00000 /* 27:20 */
/* SLU: Fault Isolation Register (FIR) (ac_slu_fir) */
#define IO_SLU_FIR 0x00000008 /* read only, wr direct */
#define IO_SLU_FIR_CLR 0x00000010 /* read and clear */
/* SLU: First Error Capture Register (FEC/WOF) */
#define IO_SLU_FEC 0x00000018
#define IO_SLU_ERR_ACT_MASK 0x00000020
#define IO_SLU_ERR_ATTN_MASK 0x00000028
#define IO_SLU_FIRX1_ACT_MASK 0x00000030
#define IO_SLU_FIRX0_ACT_MASK 0x00000038
#define IO_SLU_SEC_LEM_DEBUG_OVR 0x00000040
#define IO_SLU_EXTENDED_ERR_PTR 0x00000048
#define IO_SLU_COMMON_CONFIG 0x00000060
#define IO_SLU_FLASH_FIR 0x00000108
#define IO_SLU_SLC_FIR 0x00000110
#define IO_SLU_RIU_TRAP 0x00000280
#define IO_SLU_FLASH_FEC 0x00000308
#define IO_SLU_SLC_FEC 0x00000310
/*
* The Virtual Function's Access is from offset 0x00010000
* The Physical Function's Access is from offset 0x00050000
* Single Shared Registers exists only at offset 0x00060000
*
* SLC: Queue Virtual Window Window for accessing into a specific VF
* queue. When accessing the 0x10000 space using the 0x50000 address
* segment, the value indicated here is used to specify which VF
* register is decoded. This register, and the 0x50000 register space
* can only be accessed by the PF. Example, if this register is set to
* 0x2, then a read from 0x50000 is the same as a read from 0x10000
* from VF=2.
*/
/* SLC: Queue Segment */
#define IO_SLC_QUEUE_SEGMENT 0x00010000
#define IO_SLC_VF_QUEUE_SEGMENT 0x00050000
/* SLC: Queue Offset */
#define IO_SLC_QUEUE_OFFSET 0x00010008
#define IO_SLC_VF_QUEUE_OFFSET 0x00050008
/* SLC: Queue Configuration */
#define IO_SLC_QUEUE_CONFIG 0x00010010
#define IO_SLC_VF_QUEUE_CONFIG 0x00050010
/* SLC: Job Timout/Only accessible for the PF */
#define IO_SLC_APPJOB_TIMEOUT 0x00010018
#define IO_SLC_VF_APPJOB_TIMEOUT 0x00050018
#define TIMEOUT_250MS 0x0000000f
#define HEARTBEAT_DISABLE 0x0000ff00
/* SLC: Queue InitSequence Register */
#define IO_SLC_QUEUE_INITSQN 0x00010020
#define IO_SLC_VF_QUEUE_INITSQN 0x00050020
/* SLC: Queue Wrap */
#define IO_SLC_QUEUE_WRAP 0x00010028
#define IO_SLC_VF_QUEUE_WRAP 0x00050028
/* SLC: Queue Status */
#define IO_SLC_QUEUE_STATUS 0x00010100
#define IO_SLC_VF_QUEUE_STATUS 0x00050100
/* SLC: Queue Working Time */
#define IO_SLC_QUEUE_WTIME 0x00010030
#define IO_SLC_VF_QUEUE_WTIME 0x00050030
/* SLC: Queue Error Counts */
#define IO_SLC_QUEUE_ERRCNTS 0x00010038
#define IO_SLC_VF_QUEUE_ERRCNTS 0x00050038
/* SLC: Queue Loast Response Word */
#define IO_SLC_QUEUE_LRW 0x00010040
#define IO_SLC_VF_QUEUE_LRW 0x00050040
/* SLC: Freerunning Timer */
#define IO_SLC_FREE_RUNNING_TIMER 0x00010108
#define IO_SLC_VF_FREE_RUNNING_TIMER 0x00050108
/* SLC: Queue Virtual Access Region */
#define IO_PF_SLC_VIRTUAL_REGION 0x00050000
/* SLC: Queue Virtual Window */
#define IO_PF_SLC_VIRTUAL_WINDOW 0x00060000
/* SLC: DDCB Application Job Pending [n] (n=0:63) */
#define IO_PF_SLC_JOBPEND(n) (0x00061000 + 8*(n))
#define IO_SLC_JOBPEND(n) IO_PF_SLC_JOBPEND(n)
/* SLC: Parser Trap RAM [n] (n=0:31) */
#define IO_SLU_SLC_PARSE_TRAP(n) (0x00011000 + 8*(n))
/* SLC: Dispatcher Trap RAM [n] (n=0:31) */
#define IO_SLU_SLC_DISP_TRAP(n) (0x00011200 + 8*(n))
/* Global Fault Isolation Register (GFIR) */
#define IO_SLC_CFGREG_GFIR 0x00020000
#define GFIR_ERR_TRIGGER 0x0000ffff
/* SLU: Soft Reset Register */
#define IO_SLC_CFGREG_SOFTRESET 0x00020018
/* SLU: Misc Debug Register */
#define IO_SLC_MISC_DEBUG 0x00020060
#define IO_SLC_MISC_DEBUG_CLR 0x00020068
#define IO_SLC_MISC_DEBUG_SET 0x00020070
/* Temperature Sensor Reading */
#define IO_SLU_TEMPERATURE_SENSOR 0x00030000
#define IO_SLU_TEMPERATURE_CONFIG 0x00030008
/* Voltage Margining Control */
#define IO_SLU_VOLTAGE_CONTROL 0x00030080
#define IO_SLU_VOLTAGE_NOMINAL 0x00000000
#define IO_SLU_VOLTAGE_DOWN5 0x00000006
#define IO_SLU_VOLTAGE_UP5 0x00000007
/* Direct LED Control Register */
#define IO_SLU_LEDCONTROL 0x00030100
/* SLU: Flashbus Direct Access -A5 */
#define IO_SLU_FLASH_DIRECTACCESS 0x00040010
/* SLU: Flashbus Direct Access2 -A5 */
#define IO_SLU_FLASH_DIRECTACCESS2 0x00040020
/* SLU: Flashbus Command Interface -A5 */
#define IO_SLU_FLASH_CMDINTF 0x00040030
/* SLU: BitStream Loaded */
#define IO_SLU_BITSTREAM 0x00040040
/* This Register has a switch which will change the CAs to UR */
#define IO_HSU_ERR_BEHAVIOR 0x01001010
#define IO_SLC2_SQB_TRAP 0x00062000
#define IO_SLC2_QUEUE_MANAGER_TRAP 0x00062008
#define IO_SLC2_FLS_MASTER_TRAP 0x00062010
/* UnitID 1: HSU Registers */
#define IO_HSU_UNITCFG 0x01000000
#define IO_HSU_FIR 0x01000008
#define IO_HSU_FIR_CLR 0x01000010
#define IO_HSU_FEC 0x01000018
#define IO_HSU_ERR_ACT_MASK 0x01000020
#define IO_HSU_ERR_ATTN_MASK 0x01000028
#define IO_HSU_FIRX1_ACT_MASK 0x01000030
#define IO_HSU_FIRX0_ACT_MASK 0x01000038
#define IO_HSU_SEC_LEM_DEBUG_OVR 0x01000040
#define IO_HSU_EXTENDED_ERR_PTR 0x01000048
#define IO_HSU_COMMON_CONFIG 0x01000060
/* UnitID 2: Application Unit (APP) */
#define IO_APP_UNITCFG 0x02000000
#define IO_APP_FIR 0x02000008
#define IO_APP_FIR_CLR 0x02000010
#define IO_APP_FEC 0x02000018
#define IO_APP_ERR_ACT_MASK 0x02000020
#define IO_APP_ERR_ATTN_MASK 0x02000028
#define IO_APP_FIRX1_ACT_MASK 0x02000030
#define IO_APP_FIRX0_ACT_MASK 0x02000038
#define IO_APP_SEC_LEM_DEBUG_OVR 0x02000040
#define IO_APP_EXTENDED_ERR_PTR 0x02000048
#define IO_APP_COMMON_CONFIG 0x02000060
#define IO_APP_DEBUG_REG_01 0x02010000
#define IO_APP_DEBUG_REG_02 0x02010008
#define IO_APP_DEBUG_REG_03 0x02010010
#define IO_APP_DEBUG_REG_04 0x02010018
#define IO_APP_DEBUG_REG_05 0x02010020
#define IO_APP_DEBUG_REG_06 0x02010028
#define IO_APP_DEBUG_REG_07 0x02010030
#define IO_APP_DEBUG_REG_08 0x02010038
#define IO_APP_DEBUG_REG_09 0x02010040
#define IO_APP_DEBUG_REG_10 0x02010048
#define IO_APP_DEBUG_REG_11 0x02010050
#define IO_APP_DEBUG_REG_12 0x02010058
#define IO_APP_DEBUG_REG_13 0x02010060
#define IO_APP_DEBUG_REG_14 0x02010068
#define IO_APP_DEBUG_REG_15 0x02010070
#define IO_APP_DEBUG_REG_16 0x02010078
#define IO_APP_DEBUG_REG_17 0x02010080
#define IO_APP_DEBUG_REG_18 0x02010088
/* Read/write from/to registers */
struct genwqe_reg_io {
__u64 num; /* register offset/address */
__u64 val64;
};
/*
* All registers of our card will return values not equal this values.
* If we see IO_ILLEGAL_VALUE on any of our MMIO register reads, the
* card can be considered as unusable. It will need recovery.
*/
#define IO_ILLEGAL_VALUE 0xffffffffffffffffull
/*
* Generic DDCB execution interface.
*
* This interface is a first prototype resulting from discussions we
* had with other teams which wanted to use the Genwqe card. It allows
* to issue a DDCB request in a generic way. The request will block
* until it finishes or time out with error.
*
* Some DDCBs require DMA addresses to be specified in the ASIV
* block. The interface provies the capability to let the kernel
* driver know where those addresses are by specifying the ATS field,
* such that it can replace the user-space addresses with appropriate
* DMA addresses or DMA addresses of a scatter gather list which is
* dynamically created.
*
* Our hardware will refuse DDCB execution if the ATS field is not as
* expected. That means the DDCB execution engine in the chip knows
* where it expects DMA addresses within the ASIV part of the DDCB and
* will check that against the ATS field definition. Any invalid or
* unknown ATS content will lead to DDCB refusal.
*/
/* Genwqe chip Units */
#define DDCB_ACFUNC_SLU 0x00 /* chip service layer unit */
#define DDCB_ACFUNC_APP 0x01 /* chip application */
/* DDCB return codes (RETC) */
#define DDCB_RETC_IDLE 0x0000 /* Unexecuted/DDCB created */
#define DDCB_RETC_PENDING 0x0101 /* Pending Execution */
#define DDCB_RETC_COMPLETE 0x0102 /* Cmd complete. No error */
#define DDCB_RETC_FAULT 0x0104 /* App Err, recoverable */
#define DDCB_RETC_ERROR 0x0108 /* App Err, non-recoverable */
#define DDCB_RETC_FORCED_ERROR 0x01ff /* overwritten by driver */
#define DDCB_RETC_UNEXEC 0x0110 /* Unexe/Removed from queue */
#define DDCB_RETC_TERM 0x0120 /* Terminated */
#define DDCB_RETC_RES0 0x0140 /* Reserved */
#define DDCB_RETC_RES1 0x0180 /* Reserved */
/* DDCB Command Options (CMDOPT) */
#define DDCB_OPT_ECHO_FORCE_NO 0x0000 /* ECHO DDCB */
#define DDCB_OPT_ECHO_FORCE_102 0x0001 /* force return code */
#define DDCB_OPT_ECHO_FORCE_104 0x0002
#define DDCB_OPT_ECHO_FORCE_108 0x0003
#define DDCB_OPT_ECHO_FORCE_110 0x0004 /* only on PF ! */
#define DDCB_OPT_ECHO_FORCE_120 0x0005
#define DDCB_OPT_ECHO_FORCE_140 0x0006
#define DDCB_OPT_ECHO_FORCE_180 0x0007
#define DDCB_OPT_ECHO_COPY_NONE (0 << 5)
#define DDCB_OPT_ECHO_COPY_ALL (1 << 5)
/* Definitions of Service Layer Commands */
#define SLCMD_ECHO_SYNC 0x00 /* PF/VF */
#define SLCMD_MOVE_FLASH 0x06 /* PF only */
#define SLCMD_MOVE_FLASH_FLAGS_MODE 0x03 /* bit 0 and 1 used for mode */
#define SLCMD_MOVE_FLASH_FLAGS_DLOAD 0 /* mode: download */
#define SLCMD_MOVE_FLASH_FLAGS_EMUL 1 /* mode: emulation */
#define SLCMD_MOVE_FLASH_FLAGS_UPLOAD 2 /* mode: upload */
#define SLCMD_MOVE_FLASH_FLAGS_VERIFY 3 /* mode: verify */
#define SLCMD_MOVE_FLASH_FLAG_NOTAP (1 << 2)/* just dump DDCB and exit */
#define SLCMD_MOVE_FLASH_FLAG_POLL (1 << 3)/* wait for RETC >= 0102 */
#define SLCMD_MOVE_FLASH_FLAG_PARTITION (1 << 4)
#define SLCMD_MOVE_FLASH_FLAG_ERASE (1 << 5)
enum genwqe_card_state {
GENWQE_CARD_UNUSED = 0,
GENWQE_CARD_USED = 1,
GENWQE_CARD_FATAL_ERROR = 2,
GENWQE_CARD_STATE_MAX,
};
/* common struct for chip image exchange */
struct genwqe_bitstream {
__u64 data_addr; /* pointer to image data */
__u32 size; /* size of image file */
__u32 crc; /* crc of this image */
__u64 target_addr; /* starting address in Flash */
__u32 partition; /* '0', '1', or 'v' */
__u32 uid; /* 1=host/x=dram */
__u64 slu_id; /* informational/sim: SluID */
__u64 app_id; /* informational/sim: AppID */
__u16 retc; /* returned from processing */
__u16 attn; /* attention code from processing */
__u32 progress; /* progress code from processing */
};
/* Issuing a specific DDCB command */
#define DDCB_LENGTH 256 /* for debug data */
#define DDCB_ASIV_LENGTH 104 /* len of the DDCB ASIV array */
#define DDCB_ASIV_LENGTH_ATS 96 /* ASIV in ATS architecture */
#define DDCB_ASV_LENGTH 64 /* len of the DDCB ASV array */
#define DDCB_FIXUPS 12 /* maximum number of fixups */
struct genwqe_debug_data {
char driver_version[64];
__u64 slu_unitcfg;
__u64 app_unitcfg;
__u8 ddcb_before[DDCB_LENGTH];
__u8 ddcb_prev[DDCB_LENGTH];
__u8 ddcb_finished[DDCB_LENGTH];
};
/*
* Address Translation Specification (ATS) definitions
*
* Each 4 bit within the ATS 64-bit word specify the required address
* translation at the defined offset.
*
* 63 LSB
* 6666.5555.5555.5544.4444.4443.3333.3333 ... 11
* 3210.9876.5432.1098.7654.3210.9876.5432 ... 1098.7654.3210
*
* offset: 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 ... 0x68 0x70 0x78
* res res res res ASIV ...
* The first 4 entries in the ATS word are reserved. The following nibbles
* each describe at an 8 byte offset the format of the required data.
*/
#define ATS_TYPE_DATA 0x0ull /* data */
#define ATS_TYPE_FLAT_RD 0x4ull /* flat buffer read only */
#define ATS_TYPE_FLAT_RDWR 0x5ull /* flat buffer read/write */
#define ATS_TYPE_SGL_RD 0x6ull /* sgl read only */
#define ATS_TYPE_SGL_RDWR 0x7ull /* sgl read/write */
#define ATS_SET_FLAGS(_struct, _field, _flags) \
(((_flags) & 0xf) << (44 - (4 * (offsetof(_struct, _field) / 8))))
#define ATS_GET_FLAGS(_ats, _byte_offs) \
(((_ats) >> (44 - (4 * ((_byte_offs) / 8)))) & 0xf)
/**
* struct genwqe_ddcb_cmd - User parameter for generic DDCB commands
*
* On the way into the kernel the driver will read the whole data
* structure. On the way out the driver will not copy the ASIV data
* back to user-space.
*/
struct genwqe_ddcb_cmd {
/* START of data copied to/from driver */
__u64 next_addr; /* chaining genwqe_ddcb_cmd */
__u64 flags; /* reserved */
__u8 acfunc; /* accelerators functional unit */
__u8 cmd; /* command to execute */
__u8 asiv_length; /* used parameter length */
__u8 asv_length; /* length of valid return values */
__u16 cmdopts; /* command options */
__u16 retc; /* return code from processing */
__u16 attn; /* attention code from processing */
__u16 vcrc; /* variant crc16 */
__u32 progress; /* progress code from processing */
__u64 deque_ts; /* dequeue time stamp */
__u64 cmplt_ts; /* completion time stamp */
__u64 disp_ts; /* SW processing start */
/* move to end and avoid copy-back */
__u64 ddata_addr; /* collect debug data */
/* command specific values */
__u8 asv[DDCB_ASV_LENGTH];
/* END of data copied from driver */
union {
struct {
__u64 ats;
__u8 asiv[DDCB_ASIV_LENGTH_ATS];
};
/* used for flash update to keep it backward compatible */
__u8 __asiv[DDCB_ASIV_LENGTH];
};
/* END of data copied to driver */
};
#define GENWQE_IOC_CODE 0xa5
/* Access functions */
#define GENWQE_READ_REG64 _IOR(GENWQE_IOC_CODE, 30, struct genwqe_reg_io)
#define GENWQE_WRITE_REG64 _IOW(GENWQE_IOC_CODE, 31, struct genwqe_reg_io)
#define GENWQE_READ_REG32 _IOR(GENWQE_IOC_CODE, 32, struct genwqe_reg_io)
#define GENWQE_WRITE_REG32 _IOW(GENWQE_IOC_CODE, 33, struct genwqe_reg_io)
#define GENWQE_READ_REG16 _IOR(GENWQE_IOC_CODE, 34, struct genwqe_reg_io)
#define GENWQE_WRITE_REG16 _IOW(GENWQE_IOC_CODE, 35, struct genwqe_reg_io)
#define GENWQE_GET_CARD_STATE _IOR(GENWQE_IOC_CODE, 36, enum genwqe_card_state)
/**
* struct genwqe_mem - Memory pinning/unpinning information
* @addr: virtual user space address
* @size: size of the area pin/dma-map/unmap
* direction: 0: read/1: read and write
*
* Avoid pinning and unpinning of memory pages dynamically. Instead
* the idea is to pin the whole buffer space required for DDCB
* opertionas in advance. The driver will reuse this pinning and the
* memory associated with it to setup the sglists for the DDCB
* requests without the need to allocate and free memory or map and
* unmap to get the DMA addresses.
*
* The inverse operation needs to be called after the pinning is not
* needed anymore. The pinnings else the pinnings will get removed
* after the device is closed. Note that pinnings will required
* memory.
*/
struct genwqe_mem {
__u64 addr;
__u64 size;
__u64 direction;
__u64 flags;
};
#define GENWQE_PIN_MEM _IOWR(GENWQE_IOC_CODE, 40, struct genwqe_mem)
#define GENWQE_UNPIN_MEM _IOWR(GENWQE_IOC_CODE, 41, struct genwqe_mem)
/*
* Generic synchronous DDCB execution interface.
* Synchronously execute a DDCB.
*
* Return: 0 on success or negative error code.
* -EINVAL: Invalid parameters (ASIV_LEN, ASV_LEN, illegal fixups
* no mappings found/could not create mappings
* -EFAULT: illegal addresses in fixups, purging failed
* -EBADMSG: enqueing failed, retc != DDCB_RETC_COMPLETE
*/
#define GENWQE_EXECUTE_DDCB \
_IOWR(GENWQE_IOC_CODE, 50, struct genwqe_ddcb_cmd)
#define GENWQE_EXECUTE_RAW_DDCB \
_IOWR(GENWQE_IOC_CODE, 51, struct genwqe_ddcb_cmd)
/* Service Layer functions (PF only) */
#define GENWQE_SLU_UPDATE _IOWR(GENWQE_IOC_CODE, 80, struct genwqe_bitstream)
#define GENWQE_SLU_READ _IOWR(GENWQE_IOC_CODE, 81, struct genwqe_bitstream)
#endif /* __GENWQE_CARD_H__ */
include/uapi/linux/gfs2_ondisk.h
+10 -1
View File
@@ -319,7 +319,16 @@ struct gfs2_leaf {
__be32 lf_dirent_format; /* Format of the dirents */
__be64 lf_next; /* Next leaf, if overflow */
__u8 lf_reserved[64];
union {
__u8 lf_reserved[64];
struct {
__be64 lf_inode; /* Dir inode number */
__be32 lf_dist; /* Dist from inode on chain */
__be32 lf_nsec; /* Last ins/del usecs */
__be64 lf_sec; /* Last ins/del in secs */
__u8 lf_reserved2[40];
};
};
};
/*
include/uapi/linux/if_addr.h
+6
View File
@@ -18,6 +18,9 @@ struct ifaddrmsg {
* It makes no difference for normally configured broadcast interfaces,
* but for point-to-point IFA_ADDRESS is DESTINATION address,
* local address is supplied in IFA_LOCAL attribute.
*
* IFA_FLAGS is a u32 attribute that extends the u8 field ifa_flags.
* If present, the value from struct ifaddrmsg will be ignored.
*/
enum {
IFA_UNSPEC,
@@ -28,6 +31,7 @@ enum {
IFA_ANYCAST,
IFA_CACHEINFO,
IFA_MULTICAST,
IFA_FLAGS,
__IFA_MAX,
};
@@ -44,6 +48,8 @@ enum {
#define IFA_F_DEPRECATED 0x20
#define IFA_F_TENTATIVE 0x40
#define IFA_F_PERMANENT 0x80
#define IFA_F_MANAGETEMPADDR 0x100
#define IFA_F_NOPREFIXROUTE 0x200
struct ifa_cacheinfo {
__u32 ifa_prefered;
include/uapi/linux/if_arp.h
+1
View File
@@ -94,6 +94,7 @@
#define ARPHRD_CAIF 822 /* CAIF media type */
#define ARPHRD_IP6GRE 823 /* GRE over IPv6 */
#define ARPHRD_NETLINK 824 /* Netlink header */
#define ARPHRD_6LOWPAN 825 /* IPv6 over LoWPAN */
#define ARPHRD_VOID 0xFFFF /* Void type, nothing is known */
#define ARPHRD_NONE 0xFFFE /* zero header length */
include/uapi/linux/if_link.h
+48
View File
@@ -240,6 +240,8 @@ enum {
IFLA_INFO_KIND,
IFLA_INFO_DATA,
IFLA_INFO_XSTATS,
IFLA_INFO_SLAVE_KIND,
IFLA_INFO_SLAVE_DATA,
__IFLA_INFO_MAX,
};
@@ -331,11 +333,57 @@ enum {
IFLA_BOND_UNSPEC,
IFLA_BOND_MODE,
IFLA_BOND_ACTIVE_SLAVE,
IFLA_BOND_MIIMON,
IFLA_BOND_UPDELAY,
IFLA_BOND_DOWNDELAY,
IFLA_BOND_USE_CARRIER,
IFLA_BOND_ARP_INTERVAL,
IFLA_BOND_ARP_IP_TARGET,
IFLA_BOND_ARP_VALIDATE,
IFLA_BOND_ARP_ALL_TARGETS,
IFLA_BOND_PRIMARY,
IFLA_BOND_PRIMARY_RESELECT,
IFLA_BOND_FAIL_OVER_MAC,
IFLA_BOND_XMIT_HASH_POLICY,
IFLA_BOND_RESEND_IGMP,
IFLA_BOND_NUM_PEER_NOTIF,
IFLA_BOND_ALL_SLAVES_ACTIVE,
IFLA_BOND_MIN_LINKS,
IFLA_BOND_LP_INTERVAL,
IFLA_BOND_PACKETS_PER_SLAVE,
IFLA_BOND_AD_LACP_RATE,
IFLA_BOND_AD_SELECT,
IFLA_BOND_AD_INFO,
__IFLA_BOND_MAX,
};
#define IFLA_BOND_MAX (__IFLA_BOND_MAX - 1)
enum {
IFLA_BOND_AD_INFO_UNSPEC,
IFLA_BOND_AD_INFO_AGGREGATOR,
IFLA_BOND_AD_INFO_NUM_PORTS,
IFLA_BOND_AD_INFO_ACTOR_KEY,
IFLA_BOND_AD_INFO_PARTNER_KEY,
IFLA_BOND_AD_INFO_PARTNER_MAC,
__IFLA_BOND_AD_INFO_MAX,
};
#define IFLA_BOND_AD_INFO_MAX (__IFLA_BOND_AD_INFO_MAX - 1)
enum {
IFLA_BOND_SLAVE_UNSPEC,
IFLA_BOND_SLAVE_STATE,
IFLA_BOND_SLAVE_MII_STATUS,
IFLA_BOND_SLAVE_LINK_FAILURE_COUNT,
IFLA_BOND_SLAVE_PERM_HWADDR,
IFLA_BOND_SLAVE_QUEUE_ID,
IFLA_BOND_SLAVE_AD_AGGREGATOR_ID,
__IFLA_BOND_SLAVE_MAX,
};
#define IFLA_BOND_SLAVE_MAX (__IFLA_BOND_SLAVE_MAX - 1)
/* SR-IOV virtual function management section */
enum {
include/uapi/linux/if_packet.h
+19 -10
View File
@@ -26,8 +26,10 @@ struct sockaddr_ll {
#define PACKET_MULTICAST 2 /* To group */
#define PACKET_OTHERHOST 3 /* To someone else */
#define PACKET_OUTGOING 4 /* Outgoing of any type */
/* These ones are invisible by user level */
#define PACKET_LOOPBACK 5 /* MC/BRD frame looped back */
#define PACKET_USER 6 /* To user space */
#define PACKET_KERNEL 7 /* To kernel space */
/* Unused, PACKET_FASTROUTE and PACKET_LOOPBACK are invisible to user space */
#define PACKET_FASTROUTE 6 /* Fastrouted frame */
/* Packet socket options */
@@ -51,12 +53,14 @@ struct sockaddr_ll {
#define PACKET_TIMESTAMP 17
#define PACKET_FANOUT 18
#define PACKET_TX_HAS_OFF 19
#define PACKET_QDISC_BYPASS 20
#define PACKET_FANOUT_HASH 0
#define PACKET_FANOUT_LB 1
#define PACKET_FANOUT_CPU 2
#define PACKET_FANOUT_ROLLOVER 3
#define PACKET_FANOUT_RND 4
#define PACKET_FANOUT_QM 5
#define PACKET_FANOUT_FLAG_ROLLOVER 0x1000
#define PACKET_FANOUT_FLAG_DEFRAG 0x8000
@@ -83,17 +87,18 @@ struct tpacket_auxdata {
__u16 tp_mac;
__u16 tp_net;
__u16 tp_vlan_tci;
__u16 tp_padding;
__u16 tp_vlan_tpid;
};
/* Rx ring - header status */
#define TP_STATUS_KERNEL 0
#define TP_STATUS_USER (1 << 0)
#define TP_STATUS_COPY (1 << 1)
#define TP_STATUS_LOSING (1 << 2)
#define TP_STATUS_CSUMNOTREADY (1 << 3)
#define TP_STATUS_VLAN_VALID (1 << 4) /* auxdata has valid tp_vlan_tci */
#define TP_STATUS_BLK_TMO (1 << 5)
#define TP_STATUS_KERNEL 0
#define TP_STATUS_USER (1 << 0)
#define TP_STATUS_COPY (1 << 1)
#define TP_STATUS_LOSING (1 << 2)
#define TP_STATUS_CSUMNOTREADY (1 << 3)
#define TP_STATUS_VLAN_VALID (1 << 4) /* auxdata has valid tp_vlan_tci */
#define TP_STATUS_BLK_TMO (1 << 5)
#define TP_STATUS_VLAN_TPID_VALID (1 << 6) /* auxdata has valid tp_vlan_tpid */
/* Tx ring - header status */
#define TP_STATUS_AVAILABLE 0
@@ -132,12 +137,15 @@ struct tpacket2_hdr {
__u32 tp_sec;
__u32 tp_nsec;
__u16 tp_vlan_tci;
__u16 tp_padding;
__u16 tp_vlan_tpid;
__u8 tp_padding[4];
};
struct tpacket_hdr_variant1 {
__u32 tp_rxhash;
__u32 tp_vlan_tci;
__u16 tp_vlan_tpid;
__u16 tp_padding;
};
struct tpacket3_hdr {
@@ -153,6 +161,7 @@ struct tpacket3_hdr {
union {
struct tpacket_hdr_variant1 hv1;
};
__u8 tp_padding[8];
};
struct tpacket_bd_ts {
include/uapi/linux/in6.h
+13 -16
View File
@@ -85,6 +85,8 @@ struct in6_flowlabel_req {
#define IPV6_FL_F_CREATE 1
#define IPV6_FL_F_EXCL 2
#define IPV6_FL_F_REFLECT 4
#define IPV6_FL_F_REMOTE 8
#define IPV6_FL_S_NONE 0
#define IPV6_FL_S_EXCL 1
@@ -126,22 +128,13 @@ struct in6_flowlabel_req {
* IPV6 extension headers
*/
#if __UAPI_DEF_IPPROTO_V6
enum {
IPPROTO_HOPOPTS = 0, /* IPv6 hop-by-hop options */
#define IPPROTO_HOPOPTS IPPROTO_HOPOPTS
IPPROTO_ROUTING = 43, /* IPv6 routing header */
#define IPPROTO_ROUTING IPPROTO_ROUTING
IPPROTO_FRAGMENT = 44, /* IPv6 fragmentation header */
#define IPPROTO_FRAGMENT IPPROTO_FRAGMENT
IPPROTO_ICMPV6 = 58, /* ICMPv6 */
#define IPPROTO_ICMPV6 IPPROTO_ICMPV6
IPPROTO_NONE = 59, /* IPv6 no next header */
#define IPPROTO_NONE IPPROTO_NONE
IPPROTO_DSTOPTS = 60, /* IPv6 destination options */
#define IPPROTO_DSTOPTS IPPROTO_DSTOPTS
IPPROTO_MH = 135, /* IPv6 mobility header */
#define IPPROTO_MH IPPROTO_MH
};
#define IPPROTO_HOPOPTS 0 /* IPv6 hop-by-hop options */
#define IPPROTO_ROUTING 43 /* IPv6 routing header */
#define IPPROTO_FRAGMENT 44 /* IPv6 fragmentation header */
#define IPPROTO_ICMPV6 58 /* ICMPv6 */
#define IPPROTO_NONE 59 /* IPv6 no next header */
#define IPPROTO_DSTOPTS 60 /* IPv6 destination options */
#define IPPROTO_MH 135 /* IPv6 mobility header */
#endif /* __UAPI_DEF_IPPROTO_V6 */
/*
@@ -188,6 +181,10 @@ enum {
#define IPV6_PMTUDISC_WANT 1
#define IPV6_PMTUDISC_DO 2
#define IPV6_PMTUDISC_PROBE 3
/* same as IPV6_PMTUDISC_PROBE, provided for symetry with IPv4
* also see comments on IP_PMTUDISC_INTERFACE
*/
#define IPV6_PMTUDISC_INTERFACE 4
/* Flowlabel */
#define IPV6_FLOWLABEL_MGR 32
include/uapi/linux/input.h
+2 -1
View File
@@ -464,7 +464,8 @@ struct input_keymap_entry {
#define KEY_BRIGHTNESS_ZERO 244 /* brightness off, use ambient */
#define KEY_DISPLAY_OFF 245 /* display device to off state */
#define KEY_WIMAX 246
#define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */
#define KEY_WIMAX KEY_WWAN
#define KEY_RFKILL 247 /* Key that controls all radios */
#define KEY_MICMUTE 248 /* Mute / unmute the microphone */
include/uapi/linux/kexec.h
+1
View File
@@ -18,6 +18,7 @@
*/
#define KEXEC_ARCH_DEFAULT ( 0 << 16)
#define KEXEC_ARCH_386 ( 3 << 16)
#define KEXEC_ARCH_68K ( 4 << 16)
#define KEXEC_ARCH_X86_64 (62 << 16)
#define KEXEC_ARCH_PPC (20 << 16)
#define KEXEC_ARCH_PPC64 (21 << 16)
include/uapi/linux/kvm.h
+2
View File
@@ -674,6 +674,7 @@ struct kvm_ppc_smmu_info {
#define KVM_CAP_ARM_EL1_32BIT 93
#define KVM_CAP_SPAPR_MULTITCE 94
#define KVM_CAP_EXT_EMUL_CPUID 95
#define KVM_CAP_HYPERV_TIME 96
#ifdef KVM_CAP_IRQ_ROUTING
@@ -853,6 +854,7 @@ struct kvm_device_attr {
#define KVM_DEV_VFIO_GROUP 1
#define KVM_DEV_VFIO_GROUP_ADD 1
#define KVM_DEV_VFIO_GROUP_DEL 2
#define KVM_DEV_TYPE_ARM_VGIC_V2 5
/*
* ioctls for VM fds
include/uapi/linux/media.h
+1
View File
@@ -98,6 +98,7 @@ struct media_entity_desc {
#define MEDIA_PAD_FL_SINK (1 << 0)
#define MEDIA_PAD_FL_SOURCE (1 << 1)
#define MEDIA_PAD_FL_MUST_CONNECT (1 << 2)
struct media_pad_desc {
__u32 entity; /* entity ID */
include/uapi/linux/mic_ioctl.h
+1 -1
View File
@@ -39,7 +39,7 @@ struct mic_copy_desc {
#else
struct iovec *iov;
#endif
int iovcnt;
__u32 iovcnt;
__u8 vr_idx;
__u8 update_used;
__u32 out_len;
include/uapi/linux/mqueue.h
+5 -5
View File
@@ -23,11 +23,11 @@
#define MQ_BYTES_MAX 819200
struct mq_attr {
long mq_flags; /* message queue flags */
long mq_maxmsg; /* maximum number of messages */
long mq_msgsize; /* maximum message size */
long mq_curmsgs; /* number of messages currently queued */
long __reserved[4]; /* ignored for input, zeroed for output */
__kernel_long_t mq_flags; /* message queue flags */
__kernel_long_t mq_maxmsg; /* maximum number of messages */
__kernel_long_t mq_msgsize; /* maximum message size */
__kernel_long_t mq_curmsgs; /* number of messages currently queued */
__kernel_long_t __reserved[4]; /* ignored for input, zeroed for output */
};
/*
include/uapi/linux/msg.h
+2 -2
View File
@@ -34,8 +34,8 @@ struct msqid_ds {
/* message buffer for msgsnd and msgrcv calls */
struct msgbuf {
long mtype; /* type of message */
char mtext[1]; /* message text */
__kernel_long_t mtype; /* type of message */
char mtext[1]; /* message text */
};
/* buffer for msgctl calls IPC_INFO, MSG_INFO */
include/uapi/linux/neighbour.h
+1 -1
View File
@@ -58,7 +58,7 @@ enum {
/* NUD_NOARP & NUD_PERMANENT are pseudostates, they never change
and make no address resolution or NUD.
NUD_PERMANENT is also cannot be deleted by garbage collectors.
NUD_PERMANENT also cannot be deleted by garbage collectors.
*/
struct nda_cacheinfo {
include/uapi/linux/net_tstamp.h
+8 -8
View File
@@ -26,17 +26,17 @@ enum {
};
/**
* struct hwtstamp_config - %SIOCSHWTSTAMP parameter
* struct hwtstamp_config - %SIOCGHWTSTAMP and %SIOCSHWTSTAMP parameter
*
* @flags: no flags defined right now, must be zero
* @flags: no flags defined right now, must be zero for %SIOCSHWTSTAMP
* @tx_type: one of HWTSTAMP_TX_*
* @rx_type: one of one of HWTSTAMP_FILTER_*
* @rx_filter: one of HWTSTAMP_FILTER_*
*
* %SIOCSHWTSTAMP expects a &struct ifreq with a ifr_data pointer to
* this structure. dev_ifsioc() in the kernel takes care of the
* translation between 32 bit userspace and 64 bit kernel. The
* structure is intentionally chosen so that it has the same layout on
* 32 and 64 bit systems, don't break this!
* %SIOCGHWTSTAMP and %SIOCSHWTSTAMP expect a &struct ifreq with a
* ifr_data pointer to this structure. For %SIOCSHWTSTAMP, if the
* driver or hardware does not support the requested @rx_filter value,
* the driver may use a more general filter mode. In this case
* @rx_filter will indicate the actual mode on return.
*/
struct hwtstamp_config {
int flags;
include/uapi/linux/netconf.h
+1
View File
@@ -14,6 +14,7 @@ enum {
NETCONFA_FORWARDING,
NETCONFA_RP_FILTER,
NETCONFA_MC_FORWARDING,
NETCONFA_PROXY_NEIGH,
__NETCONFA_MAX
};
#define NETCONFA_MAX (__NETCONFA_MAX - 1)
include/uapi/linux/netfilter.h
+1
View File
@@ -53,6 +53,7 @@ enum nf_inet_hooks {
enum {
NFPROTO_UNSPEC = 0,
NFPROTO_INET = 1,
NFPROTO_IPV4 = 2,
NFPROTO_ARP = 3,
NFPROTO_BRIDGE = 7,
include/uapi/linux/netfilter/Kbuild
+3
View File
@@ -39,6 +39,7 @@ header-y += xt_TEE.h
header-y += xt_TPROXY.h
header-y += xt_addrtype.h
header-y += xt_bpf.h
header-y += xt_cgroup.h
header-y += xt_cluster.h
header-y += xt_comment.h
header-y += xt_connbytes.h
@@ -54,8 +55,10 @@ header-y += xt_ecn.h
header-y += xt_esp.h
header-y += xt_hashlimit.h
header-y += xt_helper.h
header-y += xt_ipcomp.h
header-y += xt_iprange.h
header-y += xt_ipvs.h
header-y += xt_l2tp.h
header-y += xt_length.h
header-y += xt_limit.h
header-y += xt_mac.h
include/uapi/linux/netfilter/nf_nat.h
+8 -4
View File
@@ -4,10 +4,14 @@
#include <linux/netfilter.h>
#include <linux/netfilter/nf_conntrack_tuple_common.h>
#define NF_NAT_RANGE_MAP_IPS 1
#define NF_NAT_RANGE_PROTO_SPECIFIED 2
#define NF_NAT_RANGE_PROTO_RANDOM 4
#define NF_NAT_RANGE_PERSISTENT 8
#define NF_NAT_RANGE_MAP_IPS (1 << 0)
#define NF_NAT_RANGE_PROTO_SPECIFIED (1 << 1)
#define NF_NAT_RANGE_PROTO_RANDOM (1 << 2)
#define NF_NAT_RANGE_PERSISTENT (1 << 3)
#define NF_NAT_RANGE_PROTO_RANDOM_FULLY (1 << 4)
#define NF_NAT_RANGE_PROTO_RANDOM_ALL \
(NF_NAT_RANGE_PROTO_RANDOM | NF_NAT_RANGE_PROTO_RANDOM_FULLY)
struct nf_nat_ipv4_range {
unsigned int flags;
include/uapi/linux/netfilter/nf_tables.h
+30
View File
@@ -110,11 +110,13 @@ enum nft_table_flags {
*
* @NFTA_TABLE_NAME: name of the table (NLA_STRING)
* @NFTA_TABLE_FLAGS: bitmask of enum nft_table_flags (NLA_U32)
* @NFTA_TABLE_USE: number of chains in this table (NLA_U32)
*/
enum nft_table_attributes {
NFTA_TABLE_UNSPEC,
NFTA_TABLE_NAME,
NFTA_TABLE_FLAGS,
NFTA_TABLE_USE,
__NFTA_TABLE_MAX
};
#define NFTA_TABLE_MAX (__NFTA_TABLE_MAX - 1)
@@ -529,6 +531,8 @@ enum nft_exthdr_attributes {
* @NFT_META_NFTRACE: packet nftrace bit
* @NFT_META_RTCLASSID: realm value of packet's route (skb->dst->tclassid)
* @NFT_META_SECMARK: packet secmark (skb->secmark)
* @NFT_META_NFPROTO: netfilter protocol
* @NFT_META_L4PROTO: layer 4 protocol number
*/
enum nft_meta_keys {
NFT_META_LEN,
@@ -546,6 +550,8 @@ enum nft_meta_keys {
NFT_META_NFTRACE,
NFT_META_RTCLASSID,
NFT_META_SECMARK,
NFT_META_NFPROTO,
NFT_META_L4PROTO,
};
/**
@@ -553,11 +559,13 @@ enum nft_meta_keys {
*
* @NFTA_META_DREG: destination register (NLA_U32)
* @NFTA_META_KEY: meta data item to load (NLA_U32: nft_meta_keys)
* @NFTA_META_SREG: source register (NLA_U32)
*/
enum nft_meta_attributes {
NFTA_META_UNSPEC,
NFTA_META_DREG,
NFTA_META_KEY,
NFTA_META_SREG,
__NFTA_META_MAX
};
#define NFTA_META_MAX (__NFTA_META_MAX - 1)
@@ -601,12 +609,14 @@ enum nft_ct_keys {
* @NFTA_CT_DREG: destination register (NLA_U32)
* @NFTA_CT_KEY: conntrack data item to load (NLA_U32: nft_ct_keys)
* @NFTA_CT_DIRECTION: direction in case of directional keys (NLA_U8)
* @NFTA_CT_SREG: source register (NLA_U32)
*/
enum nft_ct_attributes {
NFTA_CT_UNSPEC,
NFTA_CT_DREG,
NFTA_CT_KEY,
NFTA_CT_DIRECTION,
NFTA_CT_SREG,
__NFTA_CT_MAX
};
#define NFTA_CT_MAX (__NFTA_CT_MAX - 1)
@@ -657,6 +667,26 @@ enum nft_log_attributes {
};
#define NFTA_LOG_MAX (__NFTA_LOG_MAX - 1)
/**
* enum nft_queue_attributes - nf_tables queue expression netlink attributes
*
* @NFTA_QUEUE_NUM: netlink queue to send messages to (NLA_U16)
* @NFTA_QUEUE_TOTAL: number of queues to load balance packets on (NLA_U16)
* @NFTA_QUEUE_FLAGS: various flags (NLA_U16)
*/
enum nft_queue_attributes {
NFTA_QUEUE_UNSPEC,
NFTA_QUEUE_NUM,
NFTA_QUEUE_TOTAL,
NFTA_QUEUE_FLAGS,
__NFTA_QUEUE_MAX
};
#define NFTA_QUEUE_MAX (__NFTA_QUEUE_MAX - 1)
#define NFT_QUEUE_FLAG_BYPASS 0x01 /* for compatibility with v2 */
#define NFT_QUEUE_FLAG_CPU_FANOUT 0x02 /* use current CPU (no hashing) */
#define NFT_QUEUE_FLAG_MASK 0x03
/**
* enum nft_reject_types - nf_tables reject expression reject types
*
include/uapi/linux/netfilter/nfnetlink_queue.h
+4 -1
View File
@@ -47,6 +47,8 @@ enum nfqnl_attr_type {
NFQA_CAP_LEN, /* __u32 length of captured packet */
NFQA_SKB_INFO, /* __u32 skb meta information */
NFQA_EXP, /* nf_conntrack_netlink.h */
NFQA_UID, /* __u32 sk uid */
NFQA_GID, /* __u32 sk gid */
__NFQA_MAX
};
@@ -99,7 +101,8 @@ enum nfqnl_attr_config {
#define NFQA_CFG_F_FAIL_OPEN (1 << 0)
#define NFQA_CFG_F_CONNTRACK (1 << 1)
#define NFQA_CFG_F_GSO (1 << 2)
#define NFQA_CFG_F_MAX (1 << 3)
#define NFQA_CFG_F_UID_GID (1 << 3)
#define NFQA_CFG_F_MAX (1 << 4)
/* flags for NFQA_SKB_INFO */
/* packet appears to have wrong checksums, but they are ok */
include/uapi/linux/netfilter/xt_cgroup.h
+11
View File
@@ -0,0 +1,11 @@
#ifndef _UAPI_XT_CGROUP_H
#define _UAPI_XT_CGROUP_H
#include <linux/types.h>
struct xt_cgroup_info {
__u32 id;
__u32 invert;
};
#endif /* _UAPI_XT_CGROUP_H */
include/uapi/linux/netfilter/xt_ipcomp.h
+16
View File
@@ -0,0 +1,16 @@
#ifndef _XT_IPCOMP_H
#define _XT_IPCOMP_H
#include <linux/types.h>
struct xt_ipcomp {
__u32 spis[2]; /* Security Parameter Index */
__u8 invflags; /* Inverse flags */
__u8 hdrres; /* Test of the Reserved Filed */
};
/* Values for "invflags" field in struct xt_ipcomp. */
#define XT_IPCOMP_INV_SPI 0x01 /* Invert the sense of spi. */
#define XT_IPCOMP_INV_MASK 0x01 /* All possible flags. */
#endif /*_XT_IPCOMP_H*/
include/uapi/linux/netfilter/xt_l2tp.h
+27
View File
@@ -0,0 +1,27 @@
#ifndef _LINUX_NETFILTER_XT_L2TP_H
#define _LINUX_NETFILTER_XT_L2TP_H
#include <linux/types.h>
enum xt_l2tp_type {
XT_L2TP_TYPE_CONTROL,
XT_L2TP_TYPE_DATA,
};
/* L2TP matching stuff */
struct xt_l2tp_info {
__u32 tid; /* tunnel id */
__u32 sid; /* session id */
__u8 version; /* L2TP protocol version */
__u8 type; /* L2TP packet type */
__u8 flags; /* which fields to match */
};
enum {
XT_L2TP_TID = (1 << 0), /* match L2TP tunnel id */
XT_L2TP_SID = (1 << 1), /* match L2TP session id */
XT_L2TP_VERSION = (1 << 2), /* match L2TP protocol version */
XT_L2TP_TYPE = (1 << 3), /* match L2TP packet type */
};
#endif /* _LINUX_NETFILTER_XT_L2TP_H */
include/uapi/linux/netfilter/xt_osf.h
+1 -2
View File
@@ -13,8 +13,7 @@
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _XT_OSF_H
include/uapi/linux/nfs4.h
+1 -1
View File
@@ -150,7 +150,7 @@
#define NFS4_SECINFO_STYLE4_CURRENT_FH 0
#define NFS4_SECINFO_STYLE4_PARENT 1
#define NFS4_MAX_UINT64 (~(u64)0)
#define NFS4_MAX_UINT64 (~(__u64)0)
/* An NFS4 sessions server must support at least NFS4_MAX_OPS operations.
* If a compound requires more operations, adjust NFS4_MAX_OPS accordingly.
include/uapi/linux/nl80211.h
+116 -13
View File
@@ -581,7 +581,14 @@
* operation, %NL80211_ATTR_MAC contains the peer MAC address, and
* %NL80211_ATTR_REASON_CODE the reason code to be used (only with
* %NL80211_TDLS_TEARDOWN).
* @NL80211_CMD_TDLS_MGMT: Send a TDLS management frame.
* @NL80211_CMD_TDLS_MGMT: Send a TDLS management frame. The
* %NL80211_ATTR_TDLS_ACTION attribute determines the type of frame to be
* sent. Public Action codes (802.11-2012 8.1.5.1) will be sent as
* 802.11 management frames, while TDLS action codes (802.11-2012
* 8.5.13.1) will be encapsulated and sent as data frames. The currently
* supported Public Action code is %WLAN_PUB_ACTION_TDLS_DISCOVER_RES
* and the currently supported TDLS actions codes are given in
* &enum ieee80211_tdls_actioncode.
*
* @NL80211_CMD_UNEXPECTED_FRAME: Used by an application controlling an AP
* (or GO) interface (i.e. hostapd) to ask for unexpected frames to
@@ -686,6 +693,21 @@
* other station that transmission must be blocked until the channel
* switch is complete.
*
* @NL80211_CMD_VENDOR: Vendor-specified command/event. The command is specified
* by the %NL80211_ATTR_VENDOR_ID attribute and a sub-command in
* %NL80211_ATTR_VENDOR_SUBCMD. Parameter(s) can be transported in
* %NL80211_ATTR_VENDOR_DATA.
* For feature advertisement, the %NL80211_ATTR_VENDOR_DATA attribute is
* used in the wiphy data as a nested attribute containing descriptions
* (&struct nl80211_vendor_cmd_info) of the supported vendor commands.
* This may also be sent as an event with the same attributes.
*
* @NL80211_CMD_SET_QOS_MAP: Set Interworking QoS mapping for IP DSCP values.
* The QoS mapping information is included in %NL80211_ATTR_QOS_MAP. If
* that attribute is not included, QoS mapping is disabled. Since this
* QoS mapping is relevant for IP packets, it is only valid during an
* association. This is cleared on disassociation and AP restart.
*
* @NL80211_CMD_MAX: highest used command number
* @__NL80211_CMD_AFTER_LAST: internal use
*/
@@ -853,6 +875,10 @@ enum nl80211_commands {
NL80211_CMD_CHANNEL_SWITCH,
NL80211_CMD_VENDOR,
NL80211_CMD_SET_QOS_MAP,
/* add new commands above here */
/* used to define NL80211_CMD_MAX below */
@@ -1508,6 +1534,27 @@ enum nl80211_commands {
* to react to radar events, e.g. initiate a channel switch or leave the
* IBSS network.
*
* @NL80211_ATTR_SUPPORT_5_MHZ: A flag indicating that the device supports
* 5 MHz channel bandwidth.
* @NL80211_ATTR_SUPPORT_10_MHZ: A flag indicating that the device supports
* 10 MHz channel bandwidth.
*
* @NL80211_ATTR_OPMODE_NOTIF: Operating mode field from Operating Mode
* Notification Element based on association request when used with
* %NL80211_CMD_NEW_STATION; u8 attribute.
*
* @NL80211_ATTR_VENDOR_ID: The vendor ID, either a 24-bit OUI or, if
* %NL80211_VENDOR_ID_IS_LINUX is set, a special Linux ID (not used yet)
* @NL80211_ATTR_VENDOR_SUBCMD: vendor sub-command
* @NL80211_ATTR_VENDOR_DATA: data for the vendor command, if any; this
* attribute is also used for vendor command feature advertisement
* @NL80211_ATTR_VENDOR_EVENTS: used for event list advertising in the wiphy
* info, containing a nested array of possible events
*
* @NL80211_ATTR_QOS_MAP: IP DSCP mapping for Interworking QoS mapping. This
* data is in the format defined for the payload of the QoS Map Set element
* in IEEE Std 802.11-2012, 8.4.2.97.
*
* @NL80211_ATTR_MAX: highest attribute number currently defined
* @__NL80211_ATTR_AFTER_LAST: internal use
*/
@@ -1824,6 +1871,18 @@ enum nl80211_attrs {
NL80211_ATTR_HANDLE_DFS,
NL80211_ATTR_SUPPORT_5_MHZ,
NL80211_ATTR_SUPPORT_10_MHZ,
NL80211_ATTR_OPMODE_NOTIF,
NL80211_ATTR_VENDOR_ID,
NL80211_ATTR_VENDOR_SUBCMD,
NL80211_ATTR_VENDOR_DATA,
NL80211_ATTR_VENDOR_EVENTS,
NL80211_ATTR_QOS_MAP,
/* add attributes here, update the policy in nl80211.c */
__NL80211_ATTR_AFTER_LAST,
@@ -2224,10 +2283,9 @@ enum nl80211_band_attr {
* @NL80211_FREQUENCY_ATTR_FREQ: Frequency in MHz
* @NL80211_FREQUENCY_ATTR_DISABLED: Channel is disabled in current
* regulatory domain.
* @NL80211_FREQUENCY_ATTR_PASSIVE_SCAN: Only passive scanning is
* permitted on this channel in current regulatory domain.
* @NL80211_FREQUENCY_ATTR_NO_IBSS: IBSS networks are not permitted
* on this channel in current regulatory domain.
* @NL80211_FREQUENCY_ATTR_NO_IR: no mechanisms that initiate radiation
* are permitted on this channel, this includes sending probe
* requests, or modes of operation that require beaconing.
* @NL80211_FREQUENCY_ATTR_RADAR: Radar detection is mandatory
* on this channel in current regulatory domain.
* @NL80211_FREQUENCY_ATTR_MAX_TX_POWER: Maximum transmission power in mBm
@@ -2254,8 +2312,8 @@ enum nl80211_frequency_attr {
__NL80211_FREQUENCY_ATTR_INVALID,
NL80211_FREQUENCY_ATTR_FREQ,
NL80211_FREQUENCY_ATTR_DISABLED,
NL80211_FREQUENCY_ATTR_PASSIVE_SCAN,
NL80211_FREQUENCY_ATTR_NO_IBSS,
NL80211_FREQUENCY_ATTR_NO_IR,
__NL80211_FREQUENCY_ATTR_NO_IBSS,
NL80211_FREQUENCY_ATTR_RADAR,
NL80211_FREQUENCY_ATTR_MAX_TX_POWER,
NL80211_FREQUENCY_ATTR_DFS_STATE,
@@ -2271,6 +2329,9 @@ enum nl80211_frequency_attr {
};
#define NL80211_FREQUENCY_ATTR_MAX_TX_POWER NL80211_FREQUENCY_ATTR_MAX_TX_POWER
#define NL80211_FREQUENCY_ATTR_PASSIVE_SCAN NL80211_FREQUENCY_ATTR_NO_IR
#define NL80211_FREQUENCY_ATTR_NO_IBSS NL80211_FREQUENCY_ATTR_NO_IR
#define NL80211_FREQUENCY_ATTR_NO_IR NL80211_FREQUENCY_ATTR_NO_IR
/**
* enum nl80211_bitrate_attr - bitrate attributes
@@ -2413,8 +2474,9 @@ enum nl80211_sched_scan_match_attr {
* @NL80211_RRF_DFS: DFS support is required to be used
* @NL80211_RRF_PTP_ONLY: this is only for Point To Point links
* @NL80211_RRF_PTMP_ONLY: this is only for Point To Multi Point links
* @NL80211_RRF_PASSIVE_SCAN: passive scan is required
* @NL80211_RRF_NO_IBSS: no IBSS is allowed
* @NL80211_RRF_NO_IR: no mechanisms that initiate radiation are allowed,
* this includes probe requests or modes of operation that require
* beaconing.
*/
enum nl80211_reg_rule_flags {
NL80211_RRF_NO_OFDM = 1<<0,
@@ -2424,10 +2486,17 @@ enum nl80211_reg_rule_flags {
NL80211_RRF_DFS = 1<<4,
NL80211_RRF_PTP_ONLY = 1<<5,
NL80211_RRF_PTMP_ONLY = 1<<6,
NL80211_RRF_PASSIVE_SCAN = 1<<7,
NL80211_RRF_NO_IBSS = 1<<8,
NL80211_RRF_NO_IR = 1<<7,
__NL80211_RRF_NO_IBSS = 1<<8,
};
#define NL80211_RRF_PASSIVE_SCAN NL80211_RRF_NO_IR
#define NL80211_RRF_NO_IBSS NL80211_RRF_NO_IR
#define NL80211_RRF_NO_IR NL80211_RRF_NO_IR
/* For backport compatibility with older userspace */
#define NL80211_RRF_NO_IR_ALL (NL80211_RRF_NO_IR | __NL80211_RRF_NO_IBSS)
/**
* enum nl80211_dfs_regions - regulatory DFS regions
*
@@ -3058,21 +3127,35 @@ enum nl80211_key_attributes {
* in an array of rates as defined in IEEE 802.11 7.3.2.2 (u8 values with
* 1 = 500 kbps) but without the IE length restriction (at most
* %NL80211_MAX_SUPP_RATES in a single array).
* @NL80211_TXRATE_MCS: HT (MCS) rates allowed for TX rate selection
* @NL80211_TXRATE_HT: HT (MCS) rates allowed for TX rate selection
* in an array of MCS numbers.
* @NL80211_TXRATE_VHT: VHT rates allowed for TX rate selection,
* see &struct nl80211_txrate_vht
* @__NL80211_TXRATE_AFTER_LAST: internal
* @NL80211_TXRATE_MAX: highest TX rate attribute
*/
enum nl80211_tx_rate_attributes {
__NL80211_TXRATE_INVALID,
NL80211_TXRATE_LEGACY,
NL80211_TXRATE_MCS,
NL80211_TXRATE_HT,
NL80211_TXRATE_VHT,
/* keep last */
__NL80211_TXRATE_AFTER_LAST,
NL80211_TXRATE_MAX = __NL80211_TXRATE_AFTER_LAST - 1
};
#define NL80211_TXRATE_MCS NL80211_TXRATE_HT
#define NL80211_VHT_NSS_MAX 8
/**
* struct nl80211_txrate_vht - VHT MCS/NSS txrate bitmap
* @mcs: MCS bitmap table for each NSS (array index 0 for 1 stream, etc.)
*/
struct nl80211_txrate_vht {
__u16 mcs[NL80211_VHT_NSS_MAX];
};
/**
* enum nl80211_band - Frequency band
* @NL80211_BAND_2GHZ: 2.4 GHz ISM band
@@ -3934,4 +4017,24 @@ enum nl80211_rxmgmt_flags {
NL80211_RXMGMT_FLAG_ANSWERED = 1 << 0,
};
/*
* If this flag is unset, the lower 24 bits are an OUI, if set
* a Linux nl80211 vendor ID is used (no such IDs are allocated
* yet, so that's not valid so far)
*/
#define NL80211_VENDOR_ID_IS_LINUX 0x80000000
/**
* struct nl80211_vendor_cmd_info - vendor command data
* @vendor_id: If the %NL80211_VENDOR_ID_IS_LINUX flag is clear, then the
* value is a 24-bit OUI; if it is set then a separately allocated ID
* may be used, but no such IDs are allocated yet. New IDs should be
* added to this file when needed.
* @subcmd: sub-command ID for the command
*/
struct nl80211_vendor_cmd_info {
__u32 vendor_id;
__u32 subcmd;
};
#endif /* __LINUX_NL80211_H */
include/uapi/linux/nvme.h
+11
View File
@@ -350,6 +350,16 @@ struct nvme_delete_queue {
__u32 rsvd11[5];
};
struct nvme_abort_cmd {
__u8 opcode;
__u8 flags;
__u16 command_id;
__u32 rsvd1[9];
__le16 sqid;
__u16 cid;
__u32 rsvd11[5];
};
struct nvme_download_firmware {
__u8 opcode;
__u8 flags;
@@ -384,6 +394,7 @@ struct nvme_command {
struct nvme_download_firmware dlfw;
struct nvme_format_cmd format;
struct nvme_dsm_cmd dsm;
struct nvme_abort_cmd abort;
};
};
include/uapi/linux/openvswitch.h
+13 -1
View File
@@ -40,7 +40,15 @@ struct ovs_header {
#define OVS_DATAPATH_FAMILY "ovs_datapath"
#define OVS_DATAPATH_MCGROUP "ovs_datapath"
#define OVS_DATAPATH_VERSION 0x1
/* V2:
* - API users are expected to provide OVS_DP_ATTR_USER_FEATURES
* when creating the datapath.
*/
#define OVS_DATAPATH_VERSION 2
/* First OVS datapath version to support features */
#define OVS_DP_VER_FEATURES 2
enum ovs_datapath_cmd {
OVS_DP_CMD_UNSPEC,
@@ -75,6 +83,7 @@ enum ovs_datapath_attr {
OVS_DP_ATTR_UPCALL_PID, /* Netlink PID to receive upcalls */
OVS_DP_ATTR_STATS, /* struct ovs_dp_stats */
OVS_DP_ATTR_MEGAFLOW_STATS, /* struct ovs_dp_megaflow_stats */
OVS_DP_ATTR_USER_FEATURES, /* OVS_DP_F_* */
__OVS_DP_ATTR_MAX
};
@@ -106,6 +115,9 @@ struct ovs_vport_stats {
__u64 tx_dropped; /* no space available in linux */
};
/* Allow last Netlink attribute to be unaligned */
#define OVS_DP_F_UNALIGNED (1 << 0)
/* Fixed logical ports. */
#define OVSP_LOCAL ((__u32)0)
include/uapi/linux/pci_regs.h
+36 -6
View File
@@ -489,7 +489,12 @@
#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
#define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */
#define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */
#define PCI_EXP_LNKSTA_NLW_X4 0x0040 /* Current Link Width x4 */
#define PCI_EXP_LNKSTA_NLW_X8 0x0080 /* Current Link Width x8 */
#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
#define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */
#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
@@ -518,8 +523,16 @@
#define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */
#define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
#define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */
#define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 /* Attention Indicator on */
#define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */
#define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 /* Attention Indicator off */
#define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */
#define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 /* Power Indicator on */
#define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 /* Power Indicator blinking */
#define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 /* Power Indicator off */
#define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */
#define PCI_EXP_SLTCTL_PWR_ON 0x0000 /* Power On */
#define PCI_EXP_SLTCTL_PWR_OFF 0x0400 /* Power Off */
#define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */
#define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */
#define PCI_EXP_SLTSTA 26 /* Slot Status */
@@ -677,17 +690,34 @@
#define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */
/* Virtual Channel */
#define PCI_VC_PORT_REG1 4
#define PCI_VC_REG1_EVCC 0x7 /* extended VC count */
#define PCI_VC_PORT_REG2 8
#define PCI_VC_REG2_32_PHASE 0x2
#define PCI_VC_REG2_64_PHASE 0x4
#define PCI_VC_REG2_128_PHASE 0x8
#define PCI_VC_PORT_CAP1 4
#define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */
#define PCI_VC_CAP1_LPEVCC 0x00000070 /* low prio extended VC count */
#define PCI_VC_CAP1_ARB_SIZE 0x00000c00
#define PCI_VC_PORT_CAP2 8
#define PCI_VC_CAP2_32_PHASE 0x00000002
#define PCI_VC_CAP2_64_PHASE 0x00000004
#define PCI_VC_CAP2_128_PHASE 0x00000008
#define PCI_VC_CAP2_ARB_OFF 0xff000000
#define PCI_VC_PORT_CTRL 12
#define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001
#define PCI_VC_PORT_STATUS 14
#define PCI_VC_PORT_STATUS_TABLE 0x00000001
#define PCI_VC_RES_CAP 16
#define PCI_VC_RES_CAP_32_PHASE 0x00000002
#define PCI_VC_RES_CAP_64_PHASE 0x00000004
#define PCI_VC_RES_CAP_128_PHASE 0x00000008
#define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010
#define PCI_VC_RES_CAP_256_PHASE 0x00000020
#define PCI_VC_RES_CAP_ARB_OFF 0xff000000
#define PCI_VC_RES_CTRL 20
#define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000
#define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000
#define PCI_VC_RES_CTRL_ID 0x07000000
#define PCI_VC_RES_CTRL_ENABLE 0x80000000
#define PCI_VC_RES_STATUS 26
#define PCI_VC_RES_STATUS_TABLE 0x00000001
#define PCI_VC_RES_STATUS_NEGO 0x00000002
#define PCI_CAP_VC_BASE_SIZEOF 0x10
#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C
include/uapi/linux/perf_event.h
+3 -1
View File
@@ -679,6 +679,7 @@ enum perf_event_type {
*
* { u64 weight; } && PERF_SAMPLE_WEIGHT
* { u64 data_src; } && PERF_SAMPLE_DATA_SRC
* { u64 transaction; } && PERF_SAMPLE_TRANSACTION
* };
*/
PERF_RECORD_SAMPLE = 9,
@@ -724,6 +725,7 @@ enum perf_callchain_context {
#define PERF_FLAG_FD_NO_GROUP (1U << 0)
#define PERF_FLAG_FD_OUTPUT (1U << 1)
#define PERF_FLAG_PID_CGROUP (1U << 2) /* pid=cgroup id, per-cpu mode only */
#define PERF_FLAG_FD_CLOEXEC (1U << 3) /* O_CLOEXEC */
union perf_mem_data_src {
__u64 val;
@@ -786,7 +788,7 @@ union perf_mem_data_src {
#define PERF_MEM_TLB_SHIFT 26
#define PERF_MEM_S(a, s) \
(((u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
(((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
/*
* single taken branch record layout:
include/uapi/linux/pkt_sched.h
+53
View File
@@ -173,6 +173,8 @@ enum {
TCA_TBF_PTAB,
TCA_TBF_RATE64,
TCA_TBF_PRATE64,
TCA_TBF_BURST,
TCA_TBF_PBURST,
__TCA_TBF_MAX,
};
@@ -523,6 +525,7 @@ enum {
TCA_NETEM_LOSS,
TCA_NETEM_RATE,
TCA_NETEM_ECN,
TCA_NETEM_RATE64,
__TCA_NETEM_MAX,
};
@@ -790,4 +793,54 @@ struct tc_fq_qd_stats {
__u32 throttled_flows;
__u32 pad;
};
/* Heavy-Hitter Filter */
enum {
TCA_HHF_UNSPEC,
TCA_HHF_BACKLOG_LIMIT,
TCA_HHF_QUANTUM,
TCA_HHF_HH_FLOWS_LIMIT,
TCA_HHF_RESET_TIMEOUT,
TCA_HHF_ADMIT_BYTES,
TCA_HHF_EVICT_TIMEOUT,
TCA_HHF_NON_HH_WEIGHT,
__TCA_HHF_MAX
};
#define TCA_HHF_MAX (__TCA_HHF_MAX - 1)
struct tc_hhf_xstats {
__u32 drop_overlimit; /* number of times max qdisc packet limit
* was hit
*/
__u32 hh_overlimit; /* number of times max heavy-hitters was hit */
__u32 hh_tot_count; /* number of captured heavy-hitters so far */
__u32 hh_cur_count; /* number of current heavy-hitters */
};
/* PIE */
enum {
TCA_PIE_UNSPEC,
TCA_PIE_TARGET,
TCA_PIE_LIMIT,
TCA_PIE_TUPDATE,
TCA_PIE_ALPHA,
TCA_PIE_BETA,
TCA_PIE_ECN,
TCA_PIE_BYTEMODE,
__TCA_PIE_MAX
};
#define TCA_PIE_MAX (__TCA_PIE_MAX - 1)
struct tc_pie_xstats {
__u32 prob; /* current probability */
__u32 delay; /* current delay in ms */
__u32 avg_dq_rate; /* current average dq_rate in bits/pie_time */
__u32 packets_in; /* total number of packets enqueued */
__u32 dropped; /* packets dropped due to pie_action */
__u32 overlimit; /* dropped due to lack of space in queue */
__u32 maxq; /* maximum queue size */
__u32 ecn_mark; /* packets marked with ecn*/
};
#endif
include/uapi/linux/ppp-ioctl.h
+1
View File
@@ -12,6 +12,7 @@
#include <linux/types.h>
#include <linux/compiler.h>
#include <linux/ppp_defs.h>
/*
* Bit definitions for flags argument to PPPIOCGFLAGS/PPPIOCSFLAGS.
include/uapi/linux/raid/md_p.h
+5 -1
View File
@@ -292,6 +292,9 @@ struct mdp_superblock_1 {
* backwards anyway.
*/
#define MD_FEATURE_NEW_OFFSET 64 /* new_offset must be honoured */
#define MD_FEATURE_RECOVERY_BITMAP 128 /* recovery that is happening
* is guided by bitmap.
*/
#define MD_FEATURE_ALL (MD_FEATURE_BITMAP_OFFSET \
|MD_FEATURE_RECOVERY_OFFSET \
|MD_FEATURE_RESHAPE_ACTIVE \
@@ -299,6 +302,7 @@ struct mdp_superblock_1 {
|MD_FEATURE_REPLACEMENT \
|MD_FEATURE_RESHAPE_BACKWARDS \
|MD_FEATURE_NEW_OFFSET \
|MD_FEATURE_RECOVERY_BITMAP \
)
#endif
#endif
include/uapi/linux/resource.h
+16 -16
View File
@@ -23,25 +23,25 @@
struct rusage {
struct timeval ru_utime; /* user time used */
struct timeval ru_stime; /* system time used */
long ru_maxrss; /* maximum resident set size */
long ru_ixrss; /* integral shared memory size */
long ru_idrss; /* integral unshared data size */
long ru_isrss; /* integral unshared stack size */
long ru_minflt; /* page reclaims */
long ru_majflt; /* page faults */
long ru_nswap; /* swaps */
long ru_inblock; /* block input operations */
long ru_oublock; /* block output operations */
long ru_msgsnd; /* messages sent */
long ru_msgrcv; /* messages received */
long ru_nsignals; /* signals received */
long ru_nvcsw; /* voluntary context switches */
long ru_nivcsw; /* involuntary " */
__kernel_long_t ru_maxrss; /* maximum resident set size */
__kernel_long_t ru_ixrss; /* integral shared memory size */
__kernel_long_t ru_idrss; /* integral unshared data size */
__kernel_long_t ru_isrss; /* integral unshared stack size */
__kernel_long_t ru_minflt; /* page reclaims */
__kernel_long_t ru_majflt; /* page faults */
__kernel_long_t ru_nswap; /* swaps */
__kernel_long_t ru_inblock; /* block input operations */
__kernel_long_t ru_oublock; /* block output operations */
__kernel_long_t ru_msgsnd; /* messages sent */
__kernel_long_t ru_msgrcv; /* messages received */
__kernel_long_t ru_nsignals; /* signals received */
__kernel_long_t ru_nvcsw; /* voluntary context switches */
__kernel_long_t ru_nivcsw; /* involuntary " */
};
struct rlimit {
unsigned long rlim_cur;
unsigned long rlim_max;
__kernel_ulong_t rlim_cur;
__kernel_ulong_t rlim_max;
};
#define RLIM64_INFINITY (~0ULL)
include/uapi/linux/sched.h
+6
View File
@@ -39,8 +39,14 @@
#define SCHED_BATCH 3
/* SCHED_ISO: reserved but not implemented yet */
#define SCHED_IDLE 5
#define SCHED_DEADLINE 6
/* Can be ORed in to make sure the process is reverted back to SCHED_NORMAL on fork */
#define SCHED_RESET_ON_FORK 0x40000000
/*
* For the sched_{set,get}attr() calls
*/
#define SCHED_FLAG_RESET_ON_FORK 0x01
#endif /* _UAPI_LINUX_SCHED_H */
include/uapi/linux/sctp.h
+2 -3
View File
@@ -22,9 +22,8 @@
* See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU CC; see the file COPYING. If not, write to
* the Free Software Foundation, 59 Temple Place - Suite 330,
* Boston, MA 02111-1307, USA.
* along with GNU CC; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*
* Please send any bug reports or fixes you make to the
* email address(es):
include/uapi/linux/shm.h
+5 -5
View File
@@ -68,11 +68,11 @@ struct shminfo {
struct shm_info {
int used_ids;
unsigned long shm_tot; /* total allocated shm */
unsigned long shm_rss; /* total resident shm */
unsigned long shm_swp; /* total swapped shm */
unsigned long swap_attempts;
unsigned long swap_successes;
__kernel_ulong_t shm_tot; /* total allocated shm */
__kernel_ulong_t shm_rss; /* total resident shm */
__kernel_ulong_t shm_swp; /* total swapped shm */
__kernel_ulong_t swap_attempts;
__kernel_ulong_t swap_successes;
};
include/uapi/linux/snmp.h
+1
View File
@@ -258,6 +258,7 @@ enum
LINUX_MIB_TCPFASTOPENCOOKIEREQD, /* TCPFastOpenCookieReqd */
LINUX_MIB_TCPSPURIOUS_RTX_HOSTQUEUES, /* TCPSpuriousRtxHostQueues */
LINUX_MIB_BUSYPOLLRXPACKETS, /* BusyPollRxPackets */
LINUX_MIB_TCPAUTOCORKING, /* TCPAutoCorking */
__LINUX_MIB_MAX
};
include/uapi/linux/sockios.h
+2 -1
View File
@@ -125,7 +125,8 @@
#define SIOCBRDELIF 0x89a3 /* remove interface from bridge */
/* hardware time stamping: parameters in linux/net_tstamp.h */
#define SIOCSHWTSTAMP 0x89b0
#define SIOCSHWTSTAMP 0x89b0 /* set and get config */
#define SIOCGHWTSTAMP 0x89b1 /* get config */
/* Device private ioctl calls */
include/uapi/linux/tc_act/tc_ipt.h
+1
View File
@@ -4,6 +4,7 @@
#include <linux/pkt_cls.h>
#define TCA_ACT_IPT 6
#define TCA_ACT_XT 10
enum {
TCA_IPT_UNSPEC,
include/uapi/linux/tcp_metrics.h
+2
View File
@@ -35,6 +35,8 @@ enum {
TCP_METRICS_ATTR_FOPEN_SYN_DROPS, /* u16, count of drops */
TCP_METRICS_ATTR_FOPEN_SYN_DROP_TS, /* msecs age */
TCP_METRICS_ATTR_FOPEN_COOKIE, /* binary */
TCP_METRICS_ATTR_SADDR_IPV4, /* u32 */
TCP_METRICS_ATTR_SADDR_IPV6, /* binary */
__TCP_METRICS_ATTR_MAX,
};
include/uapi/linux/timex.h
+17 -17
View File
@@ -63,27 +63,27 @@
*/
struct timex {
unsigned int modes; /* mode selector */
long offset; /* time offset (usec) */
long freq; /* frequency offset (scaled ppm) */
long maxerror; /* maximum error (usec) */
long esterror; /* estimated error (usec) */
__kernel_long_t offset; /* time offset (usec) */
__kernel_long_t freq; /* frequency offset (scaled ppm) */
__kernel_long_t maxerror;/* maximum error (usec) */
__kernel_long_t esterror;/* estimated error (usec) */
int status; /* clock command/status */
long constant; /* pll time constant */
long precision; /* clock precision (usec) (read only) */
long tolerance; /* clock frequency tolerance (ppm)
* (read only)
*/
__kernel_long_t constant;/* pll time constant */
__kernel_long_t precision;/* clock precision (usec) (read only) */
__kernel_long_t tolerance;/* clock frequency tolerance (ppm)
* (read only)
*/
struct timeval time; /* (read only, except for ADJ_SETOFFSET) */
long tick; /* (modified) usecs between clock ticks */
__kernel_long_t tick; /* (modified) usecs between clock ticks */
long ppsfreq; /* pps frequency (scaled ppm) (ro) */
long jitter; /* pps jitter (us) (ro) */
__kernel_long_t ppsfreq;/* pps frequency (scaled ppm) (ro) */
__kernel_long_t jitter; /* pps jitter (us) (ro) */
int shift; /* interval duration (s) (shift) (ro) */
long stabil; /* pps stability (scaled ppm) (ro) */
long jitcnt; /* jitter limit exceeded (ro) */
long calcnt; /* calibration intervals (ro) */
long errcnt; /* calibration errors (ro) */
long stbcnt; /* stability limit exceeded (ro) */
__kernel_long_t stabil; /* pps stability (scaled ppm) (ro) */
__kernel_long_t jitcnt; /* jitter limit exceeded (ro) */
__kernel_long_t calcnt; /* calibration intervals (ro) */
__kernel_long_t errcnt; /* calibration errors (ro) */
__kernel_long_t stbcnt; /* stability limit exceeded (ro) */
int tai; /* TAI offset (ro) */
include/uapi/linux/v4l2-controls.h
+9
View File
@@ -164,6 +164,10 @@ enum v4l2_colorfx {
* this driver */
#define V4L2_CID_USER_TI_VPE_BASE (V4L2_CID_USER_BASE + 0x1050)
/* The base for the saa7134 driver controls.
* We reserve 16 controls for this driver. */
#define V4L2_CID_USER_SAA7134_BASE (V4L2_CID_USER_BASE + 0x1060)
/* MPEG-class control IDs */
/* The MPEG controls are applicable to all codec controls
* and the 'MPEG' part of the define is historical */
@@ -554,6 +558,11 @@ enum v4l2_vp8_golden_frame_sel {
V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_USE_PREV = 0,
V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_USE_REF_PERIOD = 1,
};
#define V4L2_CID_MPEG_VIDEO_VPX_MIN_QP (V4L2_CID_MPEG_BASE+507)
#define V4L2_CID_MPEG_VIDEO_VPX_MAX_QP (V4L2_CID_MPEG_BASE+508)
#define V4L2_CID_MPEG_VIDEO_VPX_I_FRAME_QP (V4L2_CID_MPEG_BASE+509)
#define V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP (V4L2_CID_MPEG_BASE+510)
#define V4L2_CID_MPEG_VIDEO_VPX_PROFILE (V4L2_CID_MPEG_BASE+511)
/* MPEG-class control IDs specific to the CX2341x driver as defined by V4L2 */
#define V4L2_CID_MPEG_CX2341X_BASE (V4L2_CTRL_CLASS_MPEG | 0x1000)
include/uapi/linux/v4l2-mediabus.h
+3
View File
@@ -110,6 +110,9 @@ enum v4l2_mbus_pixelcode {
/* S5C73M3 sensor specific interleaved UYVY and JPEG */
V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8 = 0x5001,
/* HSV - next is 0x6002 */
V4L2_MBUS_FMT_AHSV8888_1X32 = 0x6001,
};
/**
include/uapi/linux/videodev2.h
+2 -2
View File
@@ -207,8 +207,8 @@ enum v4l2_priority {
struct v4l2_rect {
__s32 left;
__s32 top;
__s32 width;
__s32 height;
__u32 width;
__u32 height;
};
struct v4l2_fract {
include/uapi/linux/vsp1.h
+34
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@@ -0,0 +1,34 @@
/*
* vsp1.h
*
* Renesas R-Car VSP1 - User-space API
*
* Copyright (C) 2013 Renesas Corporation
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __VSP1_USER_H__
#define __VSP1_USER_H__
#include <linux/types.h>
#include <linux/videodev2.h>
/*
* Private IOCTLs
*
* VIDIOC_VSP1_LUT_CONFIG - Configure the lookup table
*/
#define VIDIOC_VSP1_LUT_CONFIG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct vsp1_lut_config)
struct vsp1_lut_config {
u32 lut[256];
};
#endif /* __VSP1_USER_H__ */
include/uapi/linux/xattr.h
+3
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@@ -20,6 +20,9 @@
#define XATTR_MAC_OSX_PREFIX "osx."
#define XATTR_MAC_OSX_PREFIX_LEN (sizeof(XATTR_MAC_OSX_PREFIX) - 1)
#define XATTR_BTRFS_PREFIX "btrfs."
#define XATTR_BTRFS_PREFIX_LEN (sizeof(XATTR_BTRFS_PREFIX) - 1)
#define XATTR_SECURITY_PREFIX "security."
#define XATTR_SECURITY_PREFIX_LEN (sizeof(XATTR_SECURITY_PREFIX) - 1)
include/uapi/linux/zorro.h
+113
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@@ -0,0 +1,113 @@
/*
* linux/zorro.h -- Amiga AutoConfig (Zorro) Bus Definitions
*
* Copyright (C) 1995--2003 Geert Uytterhoeven
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#ifndef _UAPI_LINUX_ZORRO_H
#define _UAPI_LINUX_ZORRO_H
#include <linux/types.h>
/*
* Each Zorro board has a 32-bit ID of the form
*
* mmmmmmmmmmmmmmmmppppppppeeeeeeee
*
* with
*
* mmmmmmmmmmmmmmmm 16-bit Manufacturer ID (assigned by CBM (sigh))
* pppppppp 8-bit Product ID (assigned by manufacturer)
* eeeeeeee 8-bit Extended Product ID (currently only used
* for some GVP boards)
*/
#define ZORRO_MANUF(id) ((id) >> 16)
#define ZORRO_PROD(id) (((id) >> 8) & 0xff)
#define ZORRO_EPC(id) ((id) & 0xff)
#define ZORRO_ID(manuf, prod, epc) \
((ZORRO_MANUF_##manuf << 16) | ((prod) << 8) | (epc))
typedef __u32 zorro_id;
/* Include the ID list */
#include <linux/zorro_ids.h>
/*
* GVP identifies most of its products through the 'extended product code'
* (epc). The epc has to be ANDed with the GVP_PRODMASK before the
* identification.
*/
#define GVP_PRODMASK (0xf8)
#define GVP_SCSICLKMASK (0x01)
enum GVP_flags {
GVP_IO = 0x01,
GVP_ACCEL = 0x02,
GVP_SCSI = 0x04,
GVP_24BITDMA = 0x08,
GVP_25BITDMA = 0x10,
GVP_NOBANK = 0x20,
GVP_14MHZ = 0x40,
};
struct Node {
__be32 ln_Succ; /* Pointer to next (successor) */
__be32 ln_Pred; /* Pointer to previous (predecessor) */
__u8 ln_Type;
__s8 ln_Pri; /* Priority, for sorting */
__be32 ln_Name; /* ID string, null terminated */
} __packed;
struct ExpansionRom {
/* -First 16 bytes of the expansion ROM */
__u8 er_Type; /* Board type, size and flags */
__u8 er_Product; /* Product number, assigned by manufacturer */
__u8 er_Flags; /* Flags */
__u8 er_Reserved03; /* Must be zero ($ff inverted) */
__be16 er_Manufacturer; /* Unique ID, ASSIGNED BY COMMODORE-AMIGA! */
__be32 er_SerialNumber; /* Available for use by manufacturer */
__be16 er_InitDiagVec; /* Offset to optional "DiagArea" structure */
__u8 er_Reserved0c;
__u8 er_Reserved0d;
__u8 er_Reserved0e;
__u8 er_Reserved0f;
} __packed;
/* er_Type board type bits */
#define ERT_TYPEMASK 0xc0
#define ERT_ZORROII 0xc0
#define ERT_ZORROIII 0x80
/* other bits defined in er_Type */
#define ERTB_MEMLIST 5 /* Link RAM into free memory list */
#define ERTF_MEMLIST (1<<5)
struct ConfigDev {
struct Node cd_Node;
__u8 cd_Flags; /* (read/write) */
__u8 cd_Pad; /* reserved */
struct ExpansionRom cd_Rom; /* copy of board's expansion ROM */
__be32 cd_BoardAddr; /* where in memory the board was placed */
__be32 cd_BoardSize; /* size of board in bytes */
__be16 cd_SlotAddr; /* which slot number (PRIVATE) */
__be16 cd_SlotSize; /* number of slots (PRIVATE) */
__be32 cd_Driver; /* pointer to node of driver */
__be32 cd_NextCD; /* linked list of drivers to config */
__be32 cd_Unused[4]; /* for whatever the driver wants */
} __packed;
#define ZORRO_NUM_AUTO 16
#endif /* _UAPI_LINUX_ZORRO_H */
include/uapi/linux/zorro_ids.h
+552
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@@ -0,0 +1,552 @@
/*
* Zorro board IDs
*
* Please keep sorted.
*/
#define ZORRO_MANUF_PACIFIC_PERIPHERALS 0x00D3
#define ZORRO_PROD_PACIFIC_PERIPHERALS_SE_2000_A500 ZORRO_ID(PACIFIC_PERIPHERALS, 0x00, 0)
#define ZORRO_PROD_PACIFIC_PERIPHERALS_SCSI ZORRO_ID(PACIFIC_PERIPHERALS, 0x0A, 0)
#define ZORRO_MANUF_MACROSYSTEMS_USA_2 0x0100
#define ZORRO_PROD_MACROSYSTEMS_WARP_ENGINE ZORRO_ID(MACROSYSTEMS_USA_2, 0x13, 0)
#define ZORRO_MANUF_KUPKE_1 0x00DD
#define ZORRO_PROD_KUPKE_GOLEM_RAM_BOX_2MB ZORRO_ID(KUPKE_1, 0x00, 0)
#define ZORRO_MANUF_MEMPHIS 0x0100
#define ZORRO_PROD_MEMPHIS_STORMBRINGER ZORRO_ID(MEMPHIS, 0x00, 0)
#define ZORRO_MANUF_3_STATE 0x0200
#define ZORRO_PROD_3_STATE_MEGAMIX_2000 ZORRO_ID(3_STATE, 0x02, 0)
#define ZORRO_MANUF_COMMODORE_BRAUNSCHWEIG 0x0201
#define ZORRO_PROD_CBM_A2088_A2286 ZORRO_ID(COMMODORE_BRAUNSCHWEIG, 0x01, 0)
#define ZORRO_PROD_CBM_A2286 ZORRO_ID(COMMODORE_BRAUNSCHWEIG, 0x02, 0)
#define ZORRO_PROD_CBM_A4091_1 ZORRO_ID(COMMODORE_BRAUNSCHWEIG, 0x54, 0)
#define ZORRO_PROD_CBM_A2386SX_1 ZORRO_ID(COMMODORE_BRAUNSCHWEIG, 0x67, 0)
#define ZORRO_MANUF_COMMODORE_WEST_CHESTER_1 0x0202
#define ZORRO_PROD_CBM_A2090A ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x01, 0)
#define ZORRO_PROD_CBM_A590_A2091_1 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x02, 0)
#define ZORRO_PROD_CBM_A590_A2091_2 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x03, 0)
#define ZORRO_PROD_CBM_A2090B ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x04, 0)
#define ZORRO_PROD_CBM_A2060 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x09, 0)
#define ZORRO_PROD_CBM_A590_A2052_A2058_A2091 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x0A, 0)
#define ZORRO_PROD_CBM_A560_RAM ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x20, 0)
#define ZORRO_PROD_CBM_A2232_PROTOTYPE ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x45, 0)
#define ZORRO_PROD_CBM_A2232 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x46, 0)
#define ZORRO_PROD_CBM_A2620 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x50, 0)
#define ZORRO_PROD_CBM_A2630 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x51, 0)
#define ZORRO_PROD_CBM_A4091_2 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x54, 0)
#define ZORRO_PROD_CBM_A2065_1 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x5A, 0)
#define ZORRO_PROD_CBM_ROMULATOR ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x60, 0)
#define ZORRO_PROD_CBM_A3000_TEST_FIXTURE ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x61, 0)
#define ZORRO_PROD_CBM_A2386SX_2 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x67, 0)
#define ZORRO_PROD_CBM_A2065_2 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x70, 0)
#define ZORRO_MANUF_COMMODORE_WEST_CHESTER_2 0x0203
#define ZORRO_PROD_CBM_A2090A_CM ZORRO_ID(COMMODORE_WEST_CHESTER_2, 0x03, 0)
#define ZORRO_MANUF_PROGRESSIVE_PERIPHERALS_AND_SYSTEMS_2 0x02F4
#define ZORRO_PROD_PPS_EXP8000 ZORRO_ID(PROGRESSIVE_PERIPHERALS_AND_SYSTEMS_2, 0x02, 0)
#define ZORRO_MANUF_KOLFF_COMPUTER_SUPPLIES 0x02FF
#define ZORRO_PROD_KCS_POWER_PC_BOARD ZORRO_ID(KOLFF_COMPUTER_SUPPLIES, 0x00, 0)
#define ZORRO_MANUF_CARDCO_1 0x03EC
#define ZORRO_PROD_CARDCO_KRONOS_2000_1 ZORRO_ID(CARDCO_1, 0x04, 0)
#define ZORRO_PROD_CARDCO_A1000_1 ZORRO_ID(CARDCO_1, 0x0C, 0)
#define ZORRO_PROD_CARDCO_ESCORT ZORRO_ID(CARDCO_1, 0x0E, 0)
#define ZORRO_PROD_CARDCO_A2410 ZORRO_ID(CARDCO_1, 0xF5, 0)
#define ZORRO_MANUF_A_SQUARED 0x03ED
#define ZORRO_PROD_A_SQUARED_LIVE_2000 ZORRO_ID(A_SQUARED, 0x01, 0)
#define ZORRO_MANUF_COMSPEC_COMMUNICATIONS 0x03EE
#define ZORRO_PROD_COMSPEC_COMMUNICATIONS_AX2000 ZORRO_ID(COMSPEC_COMMUNICATIONS, 0x01, 0)
#define ZORRO_MANUF_ANAKIN_RESEARCH 0x03F1
#define ZORRO_PROD_ANAKIN_RESEARCH_EASYL ZORRO_ID(ANAKIN_RESEARCH, 0x01, 0)
#define ZORRO_MANUF_MICROBOTICS 0x03F2
#define ZORRO_PROD_MICROBOTICS_STARBOARD_II ZORRO_ID(MICROBOTICS, 0x00, 0)
#define ZORRO_PROD_MICROBOTICS_STARDRIVE ZORRO_ID(MICROBOTICS, 0x02, 0)
#define ZORRO_PROD_MICROBOTICS_8_UP_A ZORRO_ID(MICROBOTICS, 0x03, 0)
#define ZORRO_PROD_MICROBOTICS_8_UP_Z ZORRO_ID(MICROBOTICS, 0x04, 0)
#define ZORRO_PROD_MICROBOTICS_DELTA_RAM ZORRO_ID(MICROBOTICS, 0x20, 0)
#define ZORRO_PROD_MICROBOTICS_8_STAR_RAM ZORRO_ID(MICROBOTICS, 0x40, 0)
#define ZORRO_PROD_MICROBOTICS_8_STAR ZORRO_ID(MICROBOTICS, 0x41, 0)
#define ZORRO_PROD_MICROBOTICS_VXL_RAM_32 ZORRO_ID(MICROBOTICS, 0x44, 0)
#define ZORRO_PROD_MICROBOTICS_VXL_68030 ZORRO_ID(MICROBOTICS, 0x45, 0)
#define ZORRO_PROD_MICROBOTICS_DELTA ZORRO_ID(MICROBOTICS, 0x60, 0)
#define ZORRO_PROD_MICROBOTICS_MBX_1200_1200Z_RAM ZORRO_ID(MICROBOTICS, 0x81, 0)
#define ZORRO_PROD_MICROBOTICS_HARDFRAME_2000_1 ZORRO_ID(MICROBOTICS, 0x96, 0)
#define ZORRO_PROD_MICROBOTICS_HARDFRAME_2000_2 ZORRO_ID(MICROBOTICS, 0x9E, 0)
#define ZORRO_PROD_MICROBOTICS_MBX_1200_1200Z ZORRO_ID(MICROBOTICS, 0xC1, 0)
#define ZORRO_MANUF_ACCESS_ASSOCIATES_ALEGRA 0x03F4
#define ZORRO_MANUF_EXPANSION_TECHNOLOGIES 0x03F6
#define ZORRO_MANUF_ASDG 0x03FF
#define ZORRO_PROD_ASDG_MEMORY_1 ZORRO_ID(ASDG, 0x01, 0)
#define ZORRO_PROD_ASDG_MEMORY_2 ZORRO_ID(ASDG, 0x02, 0)
#define ZORRO_PROD_ASDG_EB920_LAN_ROVER ZORRO_ID(ASDG, 0xFE, 0)
#define ZORRO_PROD_ASDG_GPIB_DUALIEEE488_TWIN_X ZORRO_ID(ASDG, 0xFF, 0)
#define ZORRO_MANUF_IMTRONICS_1 0x0404
#define ZORRO_PROD_IMTRONICS_HURRICANE_2800_1 ZORRO_ID(IMTRONICS_1, 0x39, 0)
#define ZORRO_PROD_IMTRONICS_HURRICANE_2800_2 ZORRO_ID(IMTRONICS_1, 0x57, 0)
#define ZORRO_MANUF_CBM_UNIVERSITY_OF_LOWELL 0x0406
#define ZORRO_PROD_CBM_A2410 ZORRO_ID(CBM_UNIVERSITY_OF_LOWELL, 0x00, 0)
#define ZORRO_MANUF_AMERISTAR 0x041D
#define ZORRO_PROD_AMERISTAR_A2065 ZORRO_ID(AMERISTAR, 0x01, 0)
#define ZORRO_PROD_AMERISTAR_A560 ZORRO_ID(AMERISTAR, 0x09, 0)
#define ZORRO_PROD_AMERISTAR_A4066 ZORRO_ID(AMERISTAR, 0x0A, 0)
#define ZORRO_MANUF_SUPRA 0x0420
#define ZORRO_PROD_SUPRA_SUPRADRIVE_4x4 ZORRO_ID(SUPRA, 0x01, 0)
#define ZORRO_PROD_SUPRA_1000_RAM ZORRO_ID(SUPRA, 0x02, 0)
#define ZORRO_PROD_SUPRA_2000_DMA ZORRO_ID(SUPRA, 0x03, 0)
#define ZORRO_PROD_SUPRA_500 ZORRO_ID(SUPRA, 0x05, 0)
#define ZORRO_PROD_SUPRA_500_SCSI ZORRO_ID(SUPRA, 0x08, 0)
#define ZORRO_PROD_SUPRA_500XP_2000_RAM ZORRO_ID(SUPRA, 0x09, 0)
#define ZORRO_PROD_SUPRA_500RX_2000_RAM ZORRO_ID(SUPRA, 0x0A, 0)
#define ZORRO_PROD_SUPRA_2400ZI ZORRO_ID(SUPRA, 0x0B, 0)
#define ZORRO_PROD_SUPRA_500XP_SUPRADRIVE_WORDSYNC ZORRO_ID(SUPRA, 0x0C, 0)
#define ZORRO_PROD_SUPRA_SUPRADRIVE_WORDSYNC_II ZORRO_ID(SUPRA, 0x0D, 0)
#define ZORRO_PROD_SUPRA_2400ZIPLUS ZORRO_ID(SUPRA, 0x10, 0)
#define ZORRO_MANUF_COMPUTER_SYSTEMS_ASSOCIATES 0x0422
#define ZORRO_PROD_CSA_MAGNUM ZORRO_ID(COMPUTER_SYSTEMS_ASSOCIATES, 0x11, 0)
#define ZORRO_PROD_CSA_12_GAUGE ZORRO_ID(COMPUTER_SYSTEMS_ASSOCIATES, 0x15, 0)
#define ZORRO_MANUF_MARC_MICHAEL_GROTH 0x0439
#define ZORRO_MANUF_M_TECH 0x0502
#define ZORRO_PROD_MTEC_AT500_1 ZORRO_ID(M_TECH, 0x03, 0)
#define ZORRO_MANUF_GREAT_VALLEY_PRODUCTS_1 0x06E1
#define ZORRO_PROD_GVP_IMPACT_SERIES_I ZORRO_ID(GREAT_VALLEY_PRODUCTS_1, 0x08, 0)
#define ZORRO_MANUF_BYTEBOX 0x07DA
#define ZORRO_PROD_BYTEBOX_A500 ZORRO_ID(BYTEBOX, 0x00, 0)
#define ZORRO_MANUF_DKB_POWER_COMPUTING 0x07DC
#define ZORRO_PROD_DKB_POWER_COMPUTING_SECUREKEY ZORRO_ID(DKB_POWER_COMPUTING, 0x09, 0)
#define ZORRO_PROD_DKB_POWER_COMPUTING_DKM_3128 ZORRO_ID(DKB_POWER_COMPUTING, 0x0E, 0)
#define ZORRO_PROD_DKB_POWER_COMPUTING_RAPID_FIRE ZORRO_ID(DKB_POWER_COMPUTING, 0x0F, 0)
#define ZORRO_PROD_DKB_POWER_COMPUTING_DKM_1202 ZORRO_ID(DKB_POWER_COMPUTING, 0x10, 0)
#define ZORRO_PROD_DKB_POWER_COMPUTING_COBRA_VIPER_II_68EC030 ZORRO_ID(DKB_POWER_COMPUTING, 0x12, 0)
#define ZORRO_PROD_DKB_POWER_COMPUTING_WILDFIRE_060_1 ZORRO_ID(DKB_POWER_COMPUTING, 0x17, 0)
#define ZORRO_PROD_DKB_POWER_COMPUTING_WILDFIRE_060_2 ZORRO_ID(DKB_POWER_COMPUTING, 0xFF, 0)
#define ZORRO_MANUF_GREAT_VALLEY_PRODUCTS_2 0x07E1
#define ZORRO_PROD_GVP_IMPACT_SERIES_I_4K ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x01, 0)
#define ZORRO_PROD_GVP_IMPACT_SERIES_I_16K_2 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x02, 0)
#define ZORRO_PROD_GVP_IMPACT_SERIES_I_16K_3 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x03, 0)
#define ZORRO_PROD_GVP_IMPACT_3001_IDE_1 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x08, 0)
#define ZORRO_PROD_GVP_IMPACT_3001_RAM ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x09, 0)
#define ZORRO_PROD_GVP_IMPACT_SERIES_II_RAM_1 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0A, 0)
#define ZORRO_PROD_GVP_EPC_BASE ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0)
#define ZORRO_PROD_GVP_GFORCE_040_1 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0x20)
#define ZORRO_PROD_GVP_GFORCE_040_SCSI_1 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0x30)
#define ZORRO_PROD_GVP_A1291 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0x40)
#define ZORRO_PROD_GVP_COMBO_030_R4 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0x60)
#define ZORRO_PROD_GVP_COMBO_030_R4_SCSI ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0x70)
#define ZORRO_PROD_GVP_PHONEPAK ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0x78)
#define ZORRO_PROD_GVP_IO_EXTENDER ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0x98)
#define ZORRO_PROD_GVP_GFORCE_030 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0xa0)
#define ZORRO_PROD_GVP_GFORCE_030_SCSI ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0xb0)
#define ZORRO_PROD_GVP_A530 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0xc0)
#define ZORRO_PROD_GVP_A530_SCSI ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0xd0)
#define ZORRO_PROD_GVP_COMBO_030_R3 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0xe0)
#define ZORRO_PROD_GVP_COMBO_030_R3_SCSI ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0xf0)
#define ZORRO_PROD_GVP_SERIES_II ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0xf8)
#define ZORRO_PROD_GVP_IMPACT_3001_IDE_2 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0D, 0)
/*#define ZORRO_PROD_GVP_A2000_030 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0D, 0)*/
/*#define ZORRO_PROD_GVP_GFORCE_040_SCSI_2 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0D, 0)*/
#define ZORRO_PROD_GVP_GFORCE_040_060 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x16, 0)
#define ZORRO_PROD_GVP_IMPACT_VISION_24 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x20, 0)
#define ZORRO_PROD_GVP_GFORCE_040_2 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0xFF, 0)
#define ZORRO_MANUF_CALIFORNIA_ACCESS_SYNERGY 0x07E5
#define ZORRO_PROD_CALIFORNIA_ACCESS_SYNERGY_MALIBU ZORRO_ID(CALIFORNIA_ACCESS_SYNERGY, 0x01, 0)
#define ZORRO_MANUF_XETEC 0x07E6
#define ZORRO_PROD_XETEC_FASTCARD ZORRO_ID(XETEC, 0x01, 0)
#define ZORRO_PROD_XETEC_FASTCARD_RAM ZORRO_ID(XETEC, 0x02, 0)
#define ZORRO_PROD_XETEC_FASTCARD_PLUS ZORRO_ID(XETEC, 0x03, 0)
#define ZORRO_MANUF_PROGRESSIVE_PERIPHERALS_AND_SYSTEMS 0x07EA
#define ZORRO_PROD_PPS_MERCURY ZORRO_ID(PROGRESSIVE_PERIPHERALS_AND_SYSTEMS, 0x00, 0)
#define ZORRO_PROD_PPS_A3000_68040 ZORRO_ID(PROGRESSIVE_PERIPHERALS_AND_SYSTEMS, 0x01, 0)
#define ZORRO_PROD_PPS_A2000_68040 ZORRO_ID(PROGRESSIVE_PERIPHERALS_AND_SYSTEMS, 0x69, 0)
#define ZORRO_PROD_PPS_ZEUS ZORRO_ID(PROGRESSIVE_PERIPHERALS_AND_SYSTEMS, 0x96, 0)
#define ZORRO_PROD_PPS_A500_68040 ZORRO_ID(PROGRESSIVE_PERIPHERALS_AND_SYSTEMS, 0xBB, 0)
#define ZORRO_MANUF_XEBEC 0x07EC
#define ZORRO_MANUF_SPIRIT_TECHNOLOGY 0x07F2
#define ZORRO_PROD_SPIRIT_TECHNOLOGY_INSIDER_IN1000 ZORRO_ID(SPIRIT_TECHNOLOGY, 0x01, 0)
#define ZORRO_PROD_SPIRIT_TECHNOLOGY_INSIDER_IN500 ZORRO_ID(SPIRIT_TECHNOLOGY, 0x02, 0)
#define ZORRO_PROD_SPIRIT_TECHNOLOGY_SIN500 ZORRO_ID(SPIRIT_TECHNOLOGY, 0x03, 0)
#define ZORRO_PROD_SPIRIT_TECHNOLOGY_HDA_506 ZORRO_ID(SPIRIT_TECHNOLOGY, 0x04, 0)
#define ZORRO_PROD_SPIRIT_TECHNOLOGY_AX_S ZORRO_ID(SPIRIT_TECHNOLOGY, 0x05, 0)
#define ZORRO_PROD_SPIRIT_TECHNOLOGY_OCTABYTE ZORRO_ID(SPIRIT_TECHNOLOGY, 0x06, 0)
#define ZORRO_PROD_SPIRIT_TECHNOLOGY_INMATE ZORRO_ID(SPIRIT_TECHNOLOGY, 0x08, 0)
#define ZORRO_MANUF_SPIRIT_TECHNOLOGY_2 0x07F3
#define ZORRO_MANUF_BSC_ALFADATA_1 0x07FE
#define ZORRO_PROD_BSC_ALF_3_1 ZORRO_ID(BSC_ALFADATA_1, 0x03, 0)
#define ZORRO_MANUF_BSC_ALFADATA_2 0x0801
#define ZORRO_PROD_BSC_ALF_2_1 ZORRO_ID(BSC_ALFADATA_2, 0x01, 0)
#define ZORRO_PROD_BSC_ALF_2_2 ZORRO_ID(BSC_ALFADATA_2, 0x02, 0)
#define ZORRO_PROD_BSC_ALF_3_2 ZORRO_ID(BSC_ALFADATA_2, 0x03, 0)
#define ZORRO_MANUF_CARDCO_2 0x0802
#define ZORRO_PROD_CARDCO_KRONOS_2000_2 ZORRO_ID(CARDCO_2, 0x04, 0)
#define ZORRO_PROD_CARDCO_A1000_2 ZORRO_ID(CARDCO_2, 0x0C, 0)
#define ZORRO_MANUF_JOCHHEIM 0x0804
#define ZORRO_PROD_JOCHHEIM_RAM ZORRO_ID(JOCHHEIM, 0x01, 0)
#define ZORRO_MANUF_CHECKPOINT_TECHNOLOGIES 0x0807
#define ZORRO_PROD_CHECKPOINT_TECHNOLOGIES_SERIAL_SOLUTION ZORRO_ID(CHECKPOINT_TECHNOLOGIES, 0x00, 0)
#define ZORRO_MANUF_EDOTRONIK 0x0810
#define ZORRO_PROD_EDOTRONIK_IEEE_488 ZORRO_ID(EDOTRONIK, 0x01, 0)
#define ZORRO_PROD_EDOTRONIK_8032 ZORRO_ID(EDOTRONIK, 0x02, 0)
#define ZORRO_PROD_EDOTRONIK_MULTISERIAL ZORRO_ID(EDOTRONIK, 0x03, 0)
#define ZORRO_PROD_EDOTRONIK_VIDEODIGITIZER ZORRO_ID(EDOTRONIK, 0x04, 0)
#define ZORRO_PROD_EDOTRONIK_PARALLEL_IO ZORRO_ID(EDOTRONIK, 0x05, 0)
#define ZORRO_PROD_EDOTRONIK_PIC_PROTOYPING ZORRO_ID(EDOTRONIK, 0x06, 0)
#define ZORRO_PROD_EDOTRONIK_ADC ZORRO_ID(EDOTRONIK, 0x07, 0)
#define ZORRO_PROD_EDOTRONIK_VME ZORRO_ID(EDOTRONIK, 0x08, 0)
#define ZORRO_PROD_EDOTRONIK_DSP96000 ZORRO_ID(EDOTRONIK, 0x09, 0)
#define ZORRO_MANUF_NES_INC 0x0813
#define ZORRO_PROD_NES_INC_RAM ZORRO_ID(NES_INC, 0x00, 0)
#define ZORRO_MANUF_ICD 0x0817
#define ZORRO_PROD_ICD_ADVANTAGE_2000_SCSI ZORRO_ID(ICD, 0x01, 0)
#define ZORRO_PROD_ICD_ADVANTAGE_IDE ZORRO_ID(ICD, 0x03, 0)
#define ZORRO_PROD_ICD_ADVANTAGE_2080_RAM ZORRO_ID(ICD, 0x04, 0)
#define ZORRO_MANUF_KUPKE_2 0x0819
#define ZORRO_PROD_KUPKE_OMTI ZORRO_ID(KUPKE_2, 0x01, 0)
#define ZORRO_PROD_KUPKE_SCSI_II ZORRO_ID(KUPKE_2, 0x02, 0)
#define ZORRO_PROD_KUPKE_GOLEM_BOX ZORRO_ID(KUPKE_2, 0x03, 0)
#define ZORRO_PROD_KUPKE_030_882 ZORRO_ID(KUPKE_2, 0x04, 0)
#define ZORRO_PROD_KUPKE_SCSI_AT ZORRO_ID(KUPKE_2, 0x05, 0)
#define ZORRO_MANUF_GREAT_VALLEY_PRODUCTS_3 0x081D
#define ZORRO_PROD_GVP_A2000_RAM8 ZORRO_ID(GREAT_VALLEY_PRODUCTS_3, 0x09, 0)
#define ZORRO_PROD_GVP_IMPACT_SERIES_II_RAM_2 ZORRO_ID(GREAT_VALLEY_PRODUCTS_3, 0x0A, 0)
#define ZORRO_MANUF_INTERWORKS_NETWORK 0x081E
#define ZORRO_MANUF_HARDITAL_SYNTHESIS 0x0820
#define ZORRO_PROD_HARDITAL_SYNTHESIS_TQM_68030_68882 ZORRO_ID(HARDITAL_SYNTHESIS, 0x14, 0)
#define ZORRO_MANUF_APPLIED_ENGINEERING 0x0828
#define ZORRO_PROD_APPLIED_ENGINEERING_DL2000 ZORRO_ID(APPLIED_ENGINEERING, 0x10, 0)
#define ZORRO_PROD_APPLIED_ENGINEERING_RAM_WORKS ZORRO_ID(APPLIED_ENGINEERING, 0xE0, 0)
#define ZORRO_MANUF_BSC_ALFADATA_3 0x082C
#define ZORRO_PROD_BSC_OKTAGON_2008 ZORRO_ID(BSC_ALFADATA_3, 0x05, 0)
#define ZORRO_PROD_BSC_TANDEM_AT_2008_508 ZORRO_ID(BSC_ALFADATA_3, 0x06, 0)
#define ZORRO_PROD_BSC_ALFA_RAM_1200 ZORRO_ID(BSC_ALFADATA_3, 0x07, 0)
#define ZORRO_PROD_BSC_OKTAGON_2008_RAM ZORRO_ID(BSC_ALFADATA_3, 0x08, 0)
#define ZORRO_PROD_BSC_MULTIFACE_I ZORRO_ID(BSC_ALFADATA_3, 0x10, 0)
#define ZORRO_PROD_BSC_MULTIFACE_II ZORRO_ID(BSC_ALFADATA_3, 0x11, 0)
#define ZORRO_PROD_BSC_MULTIFACE_III ZORRO_ID(BSC_ALFADATA_3, 0x12, 0)
#define ZORRO_PROD_BSC_FRAMEMASTER_II ZORRO_ID(BSC_ALFADATA_3, 0x20, 0)
#define ZORRO_PROD_BSC_GRAFFITI_RAM ZORRO_ID(BSC_ALFADATA_3, 0x21, 0)
#define ZORRO_PROD_BSC_GRAFFITI_REG ZORRO_ID(BSC_ALFADATA_3, 0x22, 0)
#define ZORRO_PROD_BSC_ISDN_MASTERCARD ZORRO_ID(BSC_ALFADATA_3, 0x40, 0)
#define ZORRO_PROD_BSC_ISDN_MASTERCARD_II ZORRO_ID(BSC_ALFADATA_3, 0x41, 0)
#define ZORRO_MANUF_PHOENIX 0x0835
#define ZORRO_PROD_PHOENIX_ST506 ZORRO_ID(PHOENIX, 0x21, 0)
#define ZORRO_PROD_PHOENIX_SCSI ZORRO_ID(PHOENIX, 0x22, 0)
#define ZORRO_PROD_PHOENIX_RAM ZORRO_ID(PHOENIX, 0xBE, 0)
#define ZORRO_MANUF_ADVANCED_STORAGE_SYSTEMS 0x0836
#define ZORRO_PROD_ADVANCED_STORAGE_SYSTEMS_NEXUS ZORRO_ID(ADVANCED_STORAGE_SYSTEMS, 0x01, 0)
#define ZORRO_PROD_ADVANCED_STORAGE_SYSTEMS_NEXUS_RAM ZORRO_ID(ADVANCED_STORAGE_SYSTEMS, 0x08, 0)
#define ZORRO_MANUF_IMPULSE 0x0838
#define ZORRO_PROD_IMPULSE_FIRECRACKER_24 ZORRO_ID(IMPULSE, 0x00, 0)
#define ZORRO_MANUF_IVS 0x0840
#define ZORRO_PROD_IVS_GRANDSLAM_PIC_2 ZORRO_ID(IVS, 0x02, 0)
#define ZORRO_PROD_IVS_GRANDSLAM_PIC_1 ZORRO_ID(IVS, 0x04, 0)
#define ZORRO_PROD_IVS_OVERDRIVE ZORRO_ID(IVS, 0x10, 0)
#define ZORRO_PROD_IVS_TRUMPCARD_CLASSIC ZORRO_ID(IVS, 0x30, 0)
#define ZORRO_PROD_IVS_TRUMPCARD_PRO_GRANDSLAM ZORRO_ID(IVS, 0x34, 0)
#define ZORRO_PROD_IVS_META_4 ZORRO_ID(IVS, 0x40, 0)
#define ZORRO_PROD_IVS_WAVETOOLS ZORRO_ID(IVS, 0xBF, 0)
#define ZORRO_PROD_IVS_VECTOR_1 ZORRO_ID(IVS, 0xF3, 0)
#define ZORRO_PROD_IVS_VECTOR_2 ZORRO_ID(IVS, 0xF4, 0)
#define ZORRO_MANUF_VECTOR_1 0x0841
#define ZORRO_PROD_VECTOR_CONNECTION_1 ZORRO_ID(VECTOR_1, 0xE3, 0)
#define ZORRO_MANUF_XPERT_PRODEV 0x0845
#define ZORRO_PROD_XPERT_PRODEV_VISIONA_RAM ZORRO_ID(XPERT_PRODEV, 0x01, 0)
#define ZORRO_PROD_XPERT_PRODEV_VISIONA_REG ZORRO_ID(XPERT_PRODEV, 0x02, 0)
#define ZORRO_PROD_XPERT_PRODEV_MERLIN_RAM ZORRO_ID(XPERT_PRODEV, 0x03, 0)
#define ZORRO_PROD_XPERT_PRODEV_MERLIN_REG_1 ZORRO_ID(XPERT_PRODEV, 0x04, 0)
#define ZORRO_PROD_XPERT_PRODEV_MERLIN_REG_2 ZORRO_ID(XPERT_PRODEV, 0xC9, 0)
#define ZORRO_MANUF_HYDRA_SYSTEMS 0x0849
#define ZORRO_PROD_HYDRA_SYSTEMS_AMIGANET ZORRO_ID(HYDRA_SYSTEMS, 0x01, 0)
#define ZORRO_MANUF_SUNRIZE_INDUSTRIES 0x084F
#define ZORRO_PROD_SUNRIZE_INDUSTRIES_AD1012 ZORRO_ID(SUNRIZE_INDUSTRIES, 0x01, 0)
#define ZORRO_PROD_SUNRIZE_INDUSTRIES_AD516 ZORRO_ID(SUNRIZE_INDUSTRIES, 0x02, 0)
#define ZORRO_PROD_SUNRIZE_INDUSTRIES_DD512 ZORRO_ID(SUNRIZE_INDUSTRIES, 0x03, 0)
#define ZORRO_MANUF_TRICERATOPS 0x0850
#define ZORRO_PROD_TRICERATOPS_MULTI_IO ZORRO_ID(TRICERATOPS, 0x01, 0)
#define ZORRO_MANUF_APPLIED_MAGIC 0x0851
#define ZORRO_PROD_APPLIED_MAGIC_DMI_RESOLVER ZORRO_ID(APPLIED_MAGIC, 0x01, 0)
#define ZORRO_PROD_APPLIED_MAGIC_DIGITAL_BROADCASTER ZORRO_ID(APPLIED_MAGIC, 0x06, 0)
#define ZORRO_MANUF_GFX_BASE 0x085E
#define ZORRO_PROD_GFX_BASE_GDA_1_VRAM ZORRO_ID(GFX_BASE, 0x00, 0)
#define ZORRO_PROD_GFX_BASE_GDA_1 ZORRO_ID(GFX_BASE, 0x01, 0)
#define ZORRO_MANUF_ROCTEC 0x0860
#define ZORRO_PROD_ROCTEC_RH_800C ZORRO_ID(ROCTEC, 0x01, 0)
#define ZORRO_PROD_ROCTEC_RH_800C_RAM ZORRO_ID(ROCTEC, 0x01, 0)
#define ZORRO_MANUF_KATO 0x0861
#define ZORRO_PROD_KATO_MELODY ZORRO_ID(KATO, 0x80, 0)
/* ID clash!! */
#define ZORRO_MANUF_HELFRICH_1 0x0861
#define ZORRO_PROD_HELFRICH_RAINBOW_II ZORRO_ID(HELFRICH_1, 0x20, 0)
#define ZORRO_PROD_HELFRICH_RAINBOW_III ZORRO_ID(HELFRICH_1, 0x21, 0)
#define ZORRO_MANUF_ATLANTIS 0x0862
#define ZORRO_MANUF_PROTAR 0x0864
#define ZORRO_MANUF_ACS 0x0865
#define ZORRO_MANUF_SOFTWARE_RESULTS_ENTERPRISES 0x0866
#define ZORRO_PROD_SOFTWARE_RESULTS_ENTERPRISES_GOLDEN_GATE_2_BUS_PLUS ZORRO_ID(SOFTWARE_RESULTS_ENTERPRISES, 0x01, 0)
#define ZORRO_MANUF_MASOBOSHI 0x086D
#define ZORRO_PROD_MASOBOSHI_MASTER_CARD_SC201 ZORRO_ID(MASOBOSHI, 0x03, 0)
#define ZORRO_PROD_MASOBOSHI_MASTER_CARD_MC702 ZORRO_ID(MASOBOSHI, 0x04, 0)
#define ZORRO_PROD_MASOBOSHI_MVD_819 ZORRO_ID(MASOBOSHI, 0x07, 0)
#define ZORRO_MANUF_MAINHATTAN_DATA 0x086F
#define ZORRO_PROD_MAINHATTAN_DATA_IDE ZORRO_ID(MAINHATTAN_DATA, 0x01, 0)
#define ZORRO_MANUF_VILLAGE_TRONIC 0x0877
#define ZORRO_PROD_VILLAGE_TRONIC_DOMINO_RAM ZORRO_ID(VILLAGE_TRONIC, 0x01, 0)
#define ZORRO_PROD_VILLAGE_TRONIC_DOMINO_REG ZORRO_ID(VILLAGE_TRONIC, 0x02, 0)
#define ZORRO_PROD_VILLAGE_TRONIC_DOMINO_16M_PROTOTYPE ZORRO_ID(VILLAGE_TRONIC, 0x03, 0)
#define ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM ZORRO_ID(VILLAGE_TRONIC, 0x0B, 0)
#define ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG ZORRO_ID(VILLAGE_TRONIC, 0x0C, 0)
#define ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_SEGMENTED_MODE ZORRO_ID(VILLAGE_TRONIC, 0x0D, 0)
#define ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM1 ZORRO_ID(VILLAGE_TRONIC, 0x15, 0)
#define ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM2 ZORRO_ID(VILLAGE_TRONIC, 0x16, 0)
#define ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_REG ZORRO_ID(VILLAGE_TRONIC, 0x17, 0)
#define ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3 ZORRO_ID(VILLAGE_TRONIC, 0x18, 0)
#define ZORRO_PROD_VILLAGE_TRONIC_ARIADNE ZORRO_ID(VILLAGE_TRONIC, 0xC9, 0)
#define ZORRO_PROD_VILLAGE_TRONIC_ARIADNE2 ZORRO_ID(VILLAGE_TRONIC, 0xCA, 0)
#define ZORRO_MANUF_UTILITIES_UNLIMITED 0x087B
#define ZORRO_PROD_UTILITIES_UNLIMITED_EMPLANT_DELUXE ZORRO_ID(UTILITIES_UNLIMITED, 0x15, 0)
#define ZORRO_PROD_UTILITIES_UNLIMITED_EMPLANT_DELUXE2 ZORRO_ID(UTILITIES_UNLIMITED, 0x20, 0)
#define ZORRO_MANUF_AMITRIX 0x0880
#define ZORRO_PROD_AMITRIX_MULTI_IO ZORRO_ID(AMITRIX, 0x01, 0)
#define ZORRO_PROD_AMITRIX_CD_RAM ZORRO_ID(AMITRIX, 0x02, 0)
#define ZORRO_MANUF_ARMAX 0x0885
#define ZORRO_PROD_ARMAX_OMNIBUS ZORRO_ID(ARMAX, 0x00, 0)
#define ZORRO_MANUF_ZEUS 0x088D
#define ZORRO_PROD_ZEUS_SPIDER ZORRO_ID(ZEUS, 0x04, 0)
#define ZORRO_MANUF_NEWTEK 0x088F
#define ZORRO_PROD_NEWTEK_VIDEOTOASTER ZORRO_ID(NEWTEK, 0x00, 0)
#define ZORRO_MANUF_M_TECH_GERMANY 0x0890
#define ZORRO_PROD_MTEC_AT500_2 ZORRO_ID(M_TECH_GERMANY, 0x01, 0)
#define ZORRO_PROD_MTEC_68030 ZORRO_ID(M_TECH_GERMANY, 0x03, 0)
#define ZORRO_PROD_MTEC_68020I ZORRO_ID(M_TECH_GERMANY, 0x06, 0)
#define ZORRO_PROD_MTEC_A1200_T68030_RTC ZORRO_ID(M_TECH_GERMANY, 0x20, 0)
#define ZORRO_PROD_MTEC_VIPER_MK_V_E_MATRIX_530 ZORRO_ID(M_TECH_GERMANY, 0x21, 0)
#define ZORRO_PROD_MTEC_8_MB_RAM ZORRO_ID(M_TECH_GERMANY, 0x22, 0)
#define ZORRO_PROD_MTEC_VIPER_MK_V_E_MATRIX_530_SCSI_IDE ZORRO_ID(M_TECH_GERMANY, 0x24, 0)
#define ZORRO_MANUF_GREAT_VALLEY_PRODUCTS_4 0x0891
#define ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM ZORRO_ID(GREAT_VALLEY_PRODUCTS_4, 0x01, 0)
#define ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG ZORRO_ID(GREAT_VALLEY_PRODUCTS_4, 0x02, 0)
#define ZORRO_MANUF_APOLLO_1 0x0892
#define ZORRO_PROD_APOLLO_A1200 ZORRO_ID(APOLLO_1, 0x01, 0)
#define ZORRO_MANUF_HELFRICH_2 0x0893
#define ZORRO_PROD_HELFRICH_PICCOLO_RAM ZORRO_ID(HELFRICH_2, 0x05, 0)
#define ZORRO_PROD_HELFRICH_PICCOLO_REG ZORRO_ID(HELFRICH_2, 0x06, 0)
#define ZORRO_PROD_HELFRICH_PEGGY_PLUS_MPEG ZORRO_ID(HELFRICH_2, 0x07, 0)
#define ZORRO_PROD_HELFRICH_VIDEOCRUNCHER ZORRO_ID(HELFRICH_2, 0x08, 0)
#define ZORRO_PROD_HELFRICH_SD64_RAM ZORRO_ID(HELFRICH_2, 0x0A, 0)
#define ZORRO_PROD_HELFRICH_SD64_REG ZORRO_ID(HELFRICH_2, 0x0B, 0)
#define ZORRO_MANUF_MACROSYSTEMS_USA 0x089B
#define ZORRO_PROD_MACROSYSTEMS_WARP_ENGINE_40xx ZORRO_ID(MACROSYSTEMS_USA, 0x13, 0)
#define ZORRO_MANUF_ELBOX_COMPUTER 0x089E
#define ZORRO_PROD_ELBOX_COMPUTER_1200_4 ZORRO_ID(ELBOX_COMPUTER, 0x06, 0)
#define ZORRO_MANUF_HARMS_PROFESSIONAL 0x0A00
#define ZORRO_PROD_HARMS_PROFESSIONAL_030_PLUS ZORRO_ID(HARMS_PROFESSIONAL, 0x10, 0)
#define ZORRO_PROD_HARMS_PROFESSIONAL_3500 ZORRO_ID(HARMS_PROFESSIONAL, 0xD0, 0)
#define ZORRO_MANUF_MICRONIK 0x0A50
#define ZORRO_PROD_MICRONIK_RCA_120 ZORRO_ID(MICRONIK, 0x0A, 0)
#define ZORRO_MANUF_MICRONIK2 0x0F0F
#define ZORRO_PROD_MICRONIK2_Z3I ZORRO_ID(MICRONIK2, 0x01, 0)
#define ZORRO_MANUF_MEGAMICRO 0x1000
#define ZORRO_PROD_MEGAMICRO_SCRAM_500 ZORRO_ID(MEGAMICRO, 0x03, 0)
#define ZORRO_PROD_MEGAMICRO_SCRAM_500_RAM ZORRO_ID(MEGAMICRO, 0x04, 0)
#define ZORRO_MANUF_IMTRONICS_2 0x1028
#define ZORRO_PROD_IMTRONICS_HURRICANE_2800_3 ZORRO_ID(IMTRONICS_2, 0x39, 0)
#define ZORRO_PROD_IMTRONICS_HURRICANE_2800_4 ZORRO_ID(IMTRONICS_2, 0x57, 0)
/* unofficial ID */
#define ZORRO_MANUF_INDIVIDUAL_COMPUTERS 0x1212
#define ZORRO_PROD_INDIVIDUAL_COMPUTERS_BUDDHA ZORRO_ID(INDIVIDUAL_COMPUTERS, 0x00, 0)
#define ZORRO_PROD_INDIVIDUAL_COMPUTERS_X_SURF ZORRO_ID(INDIVIDUAL_COMPUTERS, 0x17, 0)
#define ZORRO_PROD_INDIVIDUAL_COMPUTERS_CATWEASEL ZORRO_ID(INDIVIDUAL_COMPUTERS, 0x2A, 0)
#define ZORRO_MANUF_KUPKE_3 0x1248
#define ZORRO_PROD_KUPKE_GOLEM_HD_3000 ZORRO_ID(KUPKE_3, 0x01, 0)
#define ZORRO_MANUF_ITH 0x1388
#define ZORRO_PROD_ITH_ISDN_MASTER_II ZORRO_ID(ITH, 0x01, 0)
#define ZORRO_MANUF_VMC 0x1389
#define ZORRO_PROD_VMC_ISDN_BLASTER_Z2 ZORRO_ID(VMC, 0x01, 0)
#define ZORRO_PROD_VMC_HYPERCOM_4 ZORRO_ID(VMC, 0x02, 0)
#define ZORRO_MANUF_INFORMATION 0x157C
#define ZORRO_PROD_INFORMATION_ISDN_ENGINE_I ZORRO_ID(INFORMATION, 0x64, 0)
#define ZORRO_MANUF_VORTEX 0x2017
#define ZORRO_PROD_VORTEX_GOLDEN_GATE_80386SX ZORRO_ID(VORTEX, 0x07, 0)
#define ZORRO_PROD_VORTEX_GOLDEN_GATE_RAM ZORRO_ID(VORTEX, 0x08, 0)
#define ZORRO_PROD_VORTEX_GOLDEN_GATE_80486 ZORRO_ID(VORTEX, 0x09, 0)
#define ZORRO_MANUF_EXPANSION_SYSTEMS 0x2062
#define ZORRO_PROD_EXPANSION_SYSTEMS_DATAFLYER_4000SX ZORRO_ID(EXPANSION_SYSTEMS, 0x01, 0)
#define ZORRO_PROD_EXPANSION_SYSTEMS_DATAFLYER_4000SX_RAM ZORRO_ID(EXPANSION_SYSTEMS, 0x02, 0)
#define ZORRO_MANUF_READYSOFT 0x2100
#define ZORRO_PROD_READYSOFT_AMAX_II_IV ZORRO_ID(READYSOFT, 0x01, 0)
#define ZORRO_MANUF_PHASE5 0x2140
#define ZORRO_PROD_PHASE5_BLIZZARD_RAM ZORRO_ID(PHASE5, 0x01, 0)
#define ZORRO_PROD_PHASE5_BLIZZARD ZORRO_ID(PHASE5, 0x02, 0)
#define ZORRO_PROD_PHASE5_BLIZZARD_1220_IV ZORRO_ID(PHASE5, 0x06, 0)
#define ZORRO_PROD_PHASE5_FASTLANE_Z3_RAM ZORRO_ID(PHASE5, 0x0A, 0)
#define ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060 ZORRO_ID(PHASE5, 0x0B, 0)
#define ZORRO_PROD_PHASE5_BLIZZARD_1220_CYBERSTORM ZORRO_ID(PHASE5, 0x0C, 0)
#define ZORRO_PROD_PHASE5_BLIZZARD_1230 ZORRO_ID(PHASE5, 0x0D, 0)
#define ZORRO_PROD_PHASE5_BLIZZARD_1230_IV_1260 ZORRO_ID(PHASE5, 0x11, 0)
#define ZORRO_PROD_PHASE5_BLIZZARD_2060 ZORRO_ID(PHASE5, 0x18, 0)
#define ZORRO_PROD_PHASE5_CYBERSTORM_MK_II ZORRO_ID(PHASE5, 0x19, 0)
#define ZORRO_PROD_PHASE5_CYBERVISION64 ZORRO_ID(PHASE5, 0x22, 0)
#define ZORRO_PROD_PHASE5_CYBERVISION64_3D_PROTOTYPE ZORRO_ID(PHASE5, 0x32, 0)
#define ZORRO_PROD_PHASE5_CYBERVISION64_3D ZORRO_ID(PHASE5, 0x43, 0)
#define ZORRO_PROD_PHASE5_CYBERSTORM_MK_III ZORRO_ID(PHASE5, 0x64, 0)
#define ZORRO_PROD_PHASE5_BLIZZARD_603E_PLUS ZORRO_ID(PHASE5, 0x6e, 0)
#define ZORRO_MANUF_DPS 0x2169
#define ZORRO_PROD_DPS_PERSONAL_ANIMATION_RECORDER ZORRO_ID(DPS, 0x01, 0)
#define ZORRO_MANUF_APOLLO_2 0x2200
#define ZORRO_PROD_APOLLO_A620_68020_1 ZORRO_ID(APOLLO_2, 0x00, 0)
#define ZORRO_PROD_APOLLO_A620_68020_2 ZORRO_ID(APOLLO_2, 0x01, 0)
#define ZORRO_MANUF_APOLLO_3 0x2222
#define ZORRO_PROD_APOLLO_AT_APOLLO ZORRO_ID(APOLLO_3, 0x22, 0)
#define ZORRO_PROD_APOLLO_1230_1240_1260_2030_4040_4060 ZORRO_ID(APOLLO_3, 0x23, 0)
#define ZORRO_MANUF_PETSOFF_LP 0x38A5
#define ZORRO_PROD_PETSOFF_LP_DELFINA ZORRO_ID(PETSOFF_LP, 0x00, 0)
#define ZORRO_PROD_PETSOFF_LP_DELFINA_LITE ZORRO_ID(PETSOFF_LP, 0x01, 0)
#define ZORRO_MANUF_UWE_GERLACH 0x3FF7
#define ZORRO_PROD_UWE_GERLACH_RAM_ROM ZORRO_ID(UWE_GERLACH, 0xd4, 0)
#define ZORRO_MANUF_ACT 0x4231
#define ZORRO_PROD_ACT_PRELUDE ZORRO_ID(ACT, 0x01, 0)
#define ZORRO_MANUF_MACROSYSTEMS_GERMANY 0x4754
#define ZORRO_PROD_MACROSYSTEMS_MAESTRO ZORRO_ID(MACROSYSTEMS_GERMANY, 0x03, 0)
#define ZORRO_PROD_MACROSYSTEMS_VLAB ZORRO_ID(MACROSYSTEMS_GERMANY, 0x04, 0)
#define ZORRO_PROD_MACROSYSTEMS_MAESTRO_PRO ZORRO_ID(MACROSYSTEMS_GERMANY, 0x05, 0)
#define ZORRO_PROD_MACROSYSTEMS_RETINA ZORRO_ID(MACROSYSTEMS_GERMANY, 0x06, 0)
#define ZORRO_PROD_MACROSYSTEMS_MULTI_EVOLUTION ZORRO_ID(MACROSYSTEMS_GERMANY, 0x08, 0)
#define ZORRO_PROD_MACROSYSTEMS_TOCCATA ZORRO_ID(MACROSYSTEMS_GERMANY, 0x0C, 0)
#define ZORRO_PROD_MACROSYSTEMS_RETINA_Z3 ZORRO_ID(MACROSYSTEMS_GERMANY, 0x10, 0)
#define ZORRO_PROD_MACROSYSTEMS_VLAB_MOTION ZORRO_ID(MACROSYSTEMS_GERMANY, 0x12, 0)
#define ZORRO_PROD_MACROSYSTEMS_ALTAIS ZORRO_ID(MACROSYSTEMS_GERMANY, 0x13, 0)
#define ZORRO_PROD_MACROSYSTEMS_FALCON_040 ZORRO_ID(MACROSYSTEMS_GERMANY, 0xFD, 0)
#define ZORRO_MANUF_COMBITEC 0x6766
#define ZORRO_MANUF_SKI_PERIPHERALS 0x8000
#define ZORRO_PROD_SKI_PERIPHERALS_MAST_FIREBALL ZORRO_ID(SKI_PERIPHERALS, 0x08, 0)
#define ZORRO_PROD_SKI_PERIPHERALS_SCSI_DUAL_SERIAL ZORRO_ID(SKI_PERIPHERALS, 0x80, 0)
#define ZORRO_MANUF_REIS_WARE_2 0xA9AD
#define ZORRO_PROD_REIS_WARE_SCAN_KING ZORRO_ID(REIS_WARE_2, 0x11, 0)
#define ZORRO_MANUF_CAMERON 0xAA01
#define ZORRO_PROD_CAMERON_PERSONAL_A4 ZORRO_ID(CAMERON, 0x10, 0)
#define ZORRO_MANUF_REIS_WARE 0xAA11
#define ZORRO_PROD_REIS_WARE_HANDYSCANNER ZORRO_ID(REIS_WARE, 0x11, 0)
#define ZORRO_MANUF_PHOENIX_2 0xB5A8
#define ZORRO_PROD_PHOENIX_ST506_2 ZORRO_ID(PHOENIX_2, 0x21, 0)
#define ZORRO_PROD_PHOENIX_SCSI_2 ZORRO_ID(PHOENIX_2, 0x22, 0)
#define ZORRO_PROD_PHOENIX_RAM_2 ZORRO_ID(PHOENIX_2, 0xBE, 0)
#define ZORRO_MANUF_COMBITEC_2 0xC008
#define ZORRO_PROD_COMBITEC_HD ZORRO_ID(COMBITEC_2, 0x2A, 0)
#define ZORRO_PROD_COMBITEC_SRAM ZORRO_ID(COMBITEC_2, 0x2B, 0)
/*
* Test and illegal Manufacturer IDs.
*/
#define ZORRO_MANUF_HACKER 0x07DB
#define ZORRO_PROD_GENERAL_PROTOTYPE ZORRO_ID(HACKER, 0x00, 0)
#define ZORRO_PROD_HACKER_SCSI ZORRO_ID(HACKER, 0x01, 0)
#define ZORRO_PROD_RESOURCE_MANAGEMENT_FORCE_QUICKNET_QN2000 ZORRO_ID(HACKER, 0x02, 0)
#define ZORRO_PROD_VECTOR_CONNECTION_2 ZORRO_ID(HACKER, 0xE0, 0)
#define ZORRO_PROD_VECTOR_CONNECTION_3 ZORRO_ID(HACKER, 0xE1, 0)
#define ZORRO_PROD_VECTOR_CONNECTION_4 ZORRO_ID(HACKER, 0xE2, 0)
#define ZORRO_PROD_VECTOR_CONNECTION_5 ZORRO_ID(HACKER, 0xE3, 0)
include/uapi/sound/compress_params.h
+7 -3
View File
@@ -57,6 +57,7 @@
#define MAX_NUM_CODECS 32
#define MAX_NUM_CODEC_DESCRIPTORS 32
#define MAX_NUM_BITRATES 32
#define MAX_NUM_SAMPLE_RATES 32
/* Codecs are listed linearly to allow for extensibility */
#define SND_AUDIOCODEC_PCM ((__u32) 0x00000001)
@@ -324,7 +325,8 @@ union snd_codec_options {
/** struct snd_codec_desc - description of codec capabilities
* @max_ch: Maximum number of audio channels
* @sample_rates: Sampling rates in Hz, use SNDRV_PCM_RATE_xxx for this
* @sample_rates: Sampling rates in Hz, use values like 48000 for this
* @num_sample_rates: Number of valid values in sample_rates array
* @bit_rate: Indexed array containing supported bit rates
* @num_bitrates: Number of valid values in bit_rate array
* @rate_control: value is specified by SND_RATECONTROLMODE defines.
@@ -346,7 +348,8 @@ union snd_codec_options {
struct snd_codec_desc {
__u32 max_ch;
__u32 sample_rates;
__u32 sample_rates[MAX_NUM_SAMPLE_RATES];
__u32 num_sample_rates;
__u32 bit_rate[MAX_NUM_BITRATES];
__u32 num_bitrates;
__u32 rate_control;
@@ -364,7 +367,8 @@ struct snd_codec_desc {
* @ch_out: Number of output channels. In case of contradiction between
* this field and the channelMode field, the channelMode field
* overrides.
* @sample_rate: Audio sample rate of input data
* @sample_rate: Audio sample rate of input data in Hz, use values like 48000
* for this.
* @bit_rate: Bitrate of encoded data. May be ignored by decoders
* @rate_control: Encoding rate control. See SND_RATECONTROLMODE defines.
* Encoders may rely on profiles for quality levels.
include/uapi/xen/Kbuild
+2
View File
@@ -1,3 +1,5 @@
# UAPI Header export list
header-y += evtchn.h
header-y += gntalloc.h
header-y += gntdev.h
header-y += privcmd.h
include/uapi/xen/gntalloc.h
+82
View File
@@ -0,0 +1,82 @@
/******************************************************************************
* gntalloc.h
*
* Interface to /dev/xen/gntalloc.
*
* Author: Daniel De Graaf <dgdegra@tycho.nsa.gov>
*
* This file is in the public domain.
*/
#ifndef __LINUX_PUBLIC_GNTALLOC_H__
#define __LINUX_PUBLIC_GNTALLOC_H__
/*
* Allocates a new page and creates a new grant reference.
*/
#define IOCTL_GNTALLOC_ALLOC_GREF \
_IOC(_IOC_NONE, 'G', 5, sizeof(struct ioctl_gntalloc_alloc_gref))
struct ioctl_gntalloc_alloc_gref {
/* IN parameters */
/* The ID of the domain to be given access to the grants. */
uint16_t domid;
/* Flags for this mapping */
uint16_t flags;
/* Number of pages to map */
uint32_t count;
/* OUT parameters */
/* The offset to be used on a subsequent call to mmap(). */
uint64_t index;
/* The grant references of the newly created grant, one per page */
/* Variable size, depending on count */
uint32_t gref_ids[1];
};
#define GNTALLOC_FLAG_WRITABLE 1
/*
* Deallocates the grant reference, allowing the associated page to be freed if
* no other domains are using it.
*/
#define IOCTL_GNTALLOC_DEALLOC_GREF \
_IOC(_IOC_NONE, 'G', 6, sizeof(struct ioctl_gntalloc_dealloc_gref))
struct ioctl_gntalloc_dealloc_gref {
/* IN parameters */
/* The offset returned in the map operation */
uint64_t index;
/* Number of references to unmap */
uint32_t count;
};
/*
* Sets up an unmap notification within the page, so that the other side can do
* cleanup if this side crashes. Required to implement cross-domain robust
* mutexes or close notification on communication channels.
*
* Each mapped page only supports one notification; multiple calls referring to
* the same page overwrite the previous notification. You must clear the
* notification prior to the IOCTL_GNTALLOC_DEALLOC_GREF if you do not want it
* to occur.
*/
#define IOCTL_GNTALLOC_SET_UNMAP_NOTIFY \
_IOC(_IOC_NONE, 'G', 7, sizeof(struct ioctl_gntalloc_unmap_notify))
struct ioctl_gntalloc_unmap_notify {
/* IN parameters */
/* Offset in the file descriptor for a byte within the page (same as
* used in mmap). If using UNMAP_NOTIFY_CLEAR_BYTE, this is the byte to
* be cleared. Otherwise, it can be any byte in the page whose
* notification we are adjusting.
*/
uint64_t index;
/* Action(s) to take on unmap */
uint32_t action;
/* Event channel to notify */
uint32_t event_channel_port;
};
/* Clear (set to zero) the byte specified by index */
#define UNMAP_NOTIFY_CLEAR_BYTE 0x1
/* Send an interrupt on the indicated event channel */
#define UNMAP_NOTIFY_SEND_EVENT 0x2
#endif /* __LINUX_PUBLIC_GNTALLOC_H__ */
include/uapi/xen/gntdev.h
+150
View File
@@ -0,0 +1,150 @@
/******************************************************************************
* gntdev.h
*
* Interface to /dev/xen/gntdev.
*
* Copyright (c) 2007, D G Murray
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation; or, when distributed
* separately from the Linux kernel or incorporated into other
* software packages, subject to the following license:
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this source file (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify,
* merge, publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#ifndef __LINUX_PUBLIC_GNTDEV_H__
#define __LINUX_PUBLIC_GNTDEV_H__
struct ioctl_gntdev_grant_ref {
/* The domain ID of the grant to be mapped. */
uint32_t domid;
/* The grant reference of the grant to be mapped. */
uint32_t ref;
};
/*
* Inserts the grant references into the mapping table of an instance
* of gntdev. N.B. This does not perform the mapping, which is deferred
* until mmap() is called with @index as the offset.
*/
#define IOCTL_GNTDEV_MAP_GRANT_REF \
_IOC(_IOC_NONE, 'G', 0, sizeof(struct ioctl_gntdev_map_grant_ref))
struct ioctl_gntdev_map_grant_ref {
/* IN parameters */
/* The number of grants to be mapped. */
uint32_t count;
uint32_t pad;
/* OUT parameters */
/* The offset to be used on a subsequent call to mmap(). */
uint64_t index;
/* Variable IN parameter. */
/* Array of grant references, of size @count. */
struct ioctl_gntdev_grant_ref refs[1];
};
/*
* Removes the grant references from the mapping table of an instance of
* of gntdev. N.B. munmap() must be called on the relevant virtual address(es)
* before this ioctl is called, or an error will result.
*/
#define IOCTL_GNTDEV_UNMAP_GRANT_REF \
_IOC(_IOC_NONE, 'G', 1, sizeof(struct ioctl_gntdev_unmap_grant_ref))
struct ioctl_gntdev_unmap_grant_ref {
/* IN parameters */
/* The offset was returned by the corresponding map operation. */
uint64_t index;
/* The number of pages to be unmapped. */
uint32_t count;
uint32_t pad;
};
/*
* Returns the offset in the driver's address space that corresponds
* to @vaddr. This can be used to perform a munmap(), followed by an
* UNMAP_GRANT_REF ioctl, where no state about the offset is retained by
* the caller. The number of pages that were allocated at the same time as
* @vaddr is returned in @count.
*
* N.B. Where more than one page has been mapped into a contiguous range, the
* supplied @vaddr must correspond to the start of the range; otherwise
* an error will result. It is only possible to munmap() the entire
* contiguously-allocated range at once, and not any subrange thereof.
*/
#define IOCTL_GNTDEV_GET_OFFSET_FOR_VADDR \
_IOC(_IOC_NONE, 'G', 2, sizeof(struct ioctl_gntdev_get_offset_for_vaddr))
struct ioctl_gntdev_get_offset_for_vaddr {
/* IN parameters */
/* The virtual address of the first mapped page in a range. */
uint64_t vaddr;
/* OUT parameters */
/* The offset that was used in the initial mmap() operation. */
uint64_t offset;
/* The number of pages mapped in the VM area that begins at @vaddr. */
uint32_t count;
uint32_t pad;
};
/*
* Sets the maximum number of grants that may mapped at once by this gntdev
* instance.
*
* N.B. This must be called before any other ioctl is performed on the device.
*/
#define IOCTL_GNTDEV_SET_MAX_GRANTS \
_IOC(_IOC_NONE, 'G', 3, sizeof(struct ioctl_gntdev_set_max_grants))
struct ioctl_gntdev_set_max_grants {
/* IN parameter */
/* The maximum number of grants that may be mapped at once. */
uint32_t count;
};
/*
* Sets up an unmap notification within the page, so that the other side can do
* cleanup if this side crashes. Required to implement cross-domain robust
* mutexes or close notification on communication channels.
*
* Each mapped page only supports one notification; multiple calls referring to
* the same page overwrite the previous notification. You must clear the
* notification prior to the IOCTL_GNTALLOC_DEALLOC_GREF if you do not want it
* to occur.
*/
#define IOCTL_GNTDEV_SET_UNMAP_NOTIFY \
_IOC(_IOC_NONE, 'G', 7, sizeof(struct ioctl_gntdev_unmap_notify))
struct ioctl_gntdev_unmap_notify {
/* IN parameters */
/* Offset in the file descriptor for a byte within the page (same as
* used in mmap). If using UNMAP_NOTIFY_CLEAR_BYTE, this is the byte to
* be cleared. Otherwise, it can be any byte in the page whose
* notification we are adjusting.
*/
uint64_t index;
/* Action(s) to take on unmap */
uint32_t action;
/* Event channel to notify */
uint32_t event_channel_port;
};
/* Clear (set to zero) the byte specified by index */
#define UNMAP_NOTIFY_CLEAR_BYTE 0x1
/* Send an interrupt on the indicated event channel */
#define UNMAP_NOTIFY_SEND_EVENT 0x2
#endif /* __LINUX_PUBLIC_GNTDEV_H__ */