mirror of
https://github.com/clearlinux/kvmtool.git
synced 2026-06-16 02:15:47 +00:00
Marc Zyngier
4123ca555b
The recent introduction of bi-endianness on arm/arm64 had the odd effect of breaking virtio-pci support on these platforms, as the device endian field defaults to being VIRTIO_ENDIAN_HOST, which is the wrong thing to have on a bi-endian capable architecture. The fix is to check for the endianness on the ioport path the same way we do it for mmio, which implies passing the vcpu all the way down. Patch is a bit ugly, but aligns MMIO and ioport nicely. Tested on arm64 and x86. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Pekka Enberg <penberg@kernel.org>
119 lines
3.1 KiB
C
119 lines
3.1 KiB
C
#include "kvm/ioport.h"
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#include <stdlib.h>
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#include <stdio.h>
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static bool debug_io_out(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size)
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{
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return 0;
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}
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static struct ioport_operations debug_ops = {
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.io_out = debug_io_out,
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};
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static bool seabios_debug_io_out(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size)
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{
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char ch;
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ch = ioport__read8(data);
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putchar(ch);
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return true;
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}
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static struct ioport_operations seabios_debug_ops = {
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.io_out = seabios_debug_io_out,
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};
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static bool dummy_io_in(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size)
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{
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return true;
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}
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static bool dummy_io_out(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size)
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{
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return true;
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}
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static struct ioport_operations dummy_read_write_ioport_ops = {
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.io_in = dummy_io_in,
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.io_out = dummy_io_out,
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};
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static struct ioport_operations dummy_write_only_ioport_ops = {
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.io_out = dummy_io_out,
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};
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/*
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* The "fast A20 gate"
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*/
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static bool ps2_control_a_io_in(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size)
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{
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/*
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* A20 is always enabled.
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*/
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ioport__write8(data, 0x02);
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return true;
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}
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static struct ioport_operations ps2_control_a_ops = {
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.io_in = ps2_control_a_io_in,
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.io_out = dummy_io_out,
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};
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void ioport__map_irq(u8 *irq)
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{
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}
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void ioport__setup_arch(struct kvm *kvm)
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{
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/* Legacy ioport setup */
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/* 0000 - 001F - DMA1 controller */
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ioport__register(kvm, 0x0000, &dummy_read_write_ioport_ops, 32, NULL);
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/* 0x0020 - 0x003F - 8259A PIC 1 */
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ioport__register(kvm, 0x0020, &dummy_read_write_ioport_ops, 2, NULL);
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/* PORT 0040-005F - PIT - PROGRAMMABLE INTERVAL TIMER (8253, 8254) */
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ioport__register(kvm, 0x0040, &dummy_read_write_ioport_ops, 4, NULL);
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/* 0092 - PS/2 system control port A */
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ioport__register(kvm, 0x0092, &ps2_control_a_ops, 1, NULL);
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/* 0x00A0 - 0x00AF - 8259A PIC 2 */
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ioport__register(kvm, 0x00A0, &dummy_read_write_ioport_ops, 2, NULL);
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/* 00C0 - 001F - DMA2 controller */
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ioport__register(kvm, 0x00C0, &dummy_read_write_ioport_ops, 32, NULL);
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/* PORT 00E0-00EF are 'motherboard specific' so we use them for our
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internal debugging purposes. */
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ioport__register(kvm, IOPORT_DBG, &debug_ops, 1, NULL);
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/* PORT 00ED - DUMMY PORT FOR DELAY??? */
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ioport__register(kvm, 0x00ED, &dummy_write_only_ioport_ops, 1, NULL);
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/* 0x00F0 - 0x00FF - Math co-processor */
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ioport__register(kvm, 0x00F0, &dummy_write_only_ioport_ops, 2, NULL);
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/* PORT 0278-027A - PARALLEL PRINTER PORT (usually LPT1, sometimes LPT2) */
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ioport__register(kvm, 0x0278, &dummy_read_write_ioport_ops, 3, NULL);
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/* PORT 0378-037A - PARALLEL PRINTER PORT (usually LPT2, sometimes LPT3) */
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ioport__register(kvm, 0x0378, &dummy_read_write_ioport_ops, 3, NULL);
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/* PORT 03D4-03D5 - COLOR VIDEO - CRT CONTROL REGISTERS */
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ioport__register(kvm, 0x03D4, &dummy_read_write_ioport_ops, 1, NULL);
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ioport__register(kvm, 0x03D5, &dummy_write_only_ioport_ops, 1, NULL);
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ioport__register(kvm, 0x402, &seabios_debug_ops, 1, NULL);
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/* 0510 - QEMU BIOS configuration register */
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ioport__register(kvm, 0x510, &dummy_read_write_ioport_ops, 2, NULL);
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}
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