mirror of
https://github.com/clearlinux/kvmtool.git
synced 2026-06-15 18:05:49 +00:00
Andre Przywara
045fc040c8
We had GIC specific defines for the IRQ type identifiers in kvmtool. But in fact the specification of being a level or edge interrupt is quite generic, with the GIC binding using the generic Linux defines. So lets replace the GIC specific #defines in favour of the more general names copied from Linux' include/linux/irq.h. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
118 lines
3.2 KiB
C
118 lines
3.2 KiB
C
#include "kvm/devices.h"
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#include "kvm/fdt.h"
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#include "kvm/of_pci.h"
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#include "kvm/pci.h"
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#include "kvm/util.h"
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#include "arm-common/pci.h"
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/*
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* An entry in the interrupt-map table looks like:
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* <pci unit address> <pci interrupt pin> <gic phandle> <gic interrupt>
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*/
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struct of_gic_irq {
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u32 type, num, flags;
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} __attribute__((packed));
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struct of_interrupt_map_entry {
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struct of_pci_irq_mask pci_irq_mask;
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u32 gic_phandle;
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struct of_gic_irq gic_irq;
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} __attribute__((packed));
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void pci__generate_fdt_nodes(void *fdt, u32 gic_phandle)
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{
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struct device_header *dev_hdr;
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struct of_interrupt_map_entry irq_map[OF_PCI_IRQ_MAP_MAX];
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unsigned nentries = 0;
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/* Bus range */
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u32 bus_range[] = { cpu_to_fdt32(0), cpu_to_fdt32(1), };
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/* Configuration Space */
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u64 cfg_reg_prop[] = { cpu_to_fdt64(KVM_PCI_CFG_AREA),
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cpu_to_fdt64(ARM_PCI_CFG_SIZE), };
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/* Describe the memory ranges */
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struct of_pci_ranges_entry ranges[] = {
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{
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.pci_addr = {
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.hi = cpu_to_fdt32(of_pci_b_ss(OF_PCI_SS_IO)),
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.mid = 0,
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.lo = 0,
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},
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.cpu_addr = cpu_to_fdt64(KVM_IOPORT_AREA),
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.length = cpu_to_fdt64(ARM_IOPORT_SIZE),
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},
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{
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.pci_addr = {
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.hi = cpu_to_fdt32(of_pci_b_ss(OF_PCI_SS_M32)),
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.mid = cpu_to_fdt32(KVM_PCI_MMIO_AREA >> 32),
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.lo = cpu_to_fdt32(KVM_PCI_MMIO_AREA),
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},
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.cpu_addr = cpu_to_fdt64(KVM_PCI_MMIO_AREA),
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.length = cpu_to_fdt64(ARM_PCI_MMIO_SIZE),
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},
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};
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/* Boilerplate PCI properties */
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_FDT(fdt_begin_node(fdt, "pci"));
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_FDT(fdt_property_string(fdt, "device_type", "pci"));
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_FDT(fdt_property_cell(fdt, "#address-cells", 0x3));
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_FDT(fdt_property_cell(fdt, "#size-cells", 0x2));
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_FDT(fdt_property_cell(fdt, "#interrupt-cells", 0x1));
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_FDT(fdt_property_string(fdt, "compatible", "pci-host-cam-generic"));
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_FDT(fdt_property(fdt, "bus-range", bus_range, sizeof(bus_range)));
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_FDT(fdt_property(fdt, "reg", &cfg_reg_prop, sizeof(cfg_reg_prop)));
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_FDT(fdt_property(fdt, "ranges", ranges, sizeof(ranges)));
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/* Generate the interrupt map ... */
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dev_hdr = device__first_dev(DEVICE_BUS_PCI);
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while (dev_hdr && nentries < ARRAY_SIZE(irq_map)) {
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struct of_interrupt_map_entry *entry = &irq_map[nentries];
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struct pci_device_header *pci_hdr = dev_hdr->data;
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u8 dev_num = dev_hdr->dev_num;
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u8 pin = pci_hdr->irq_pin;
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u8 irq = pci_hdr->irq_line;
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*entry = (struct of_interrupt_map_entry) {
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.pci_irq_mask = {
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.pci_addr = {
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.hi = cpu_to_fdt32(of_pci_b_ddddd(dev_num)),
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.mid = 0,
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.lo = 0,
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},
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.pci_pin = cpu_to_fdt32(pin),
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},
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.gic_phandle = cpu_to_fdt32(gic_phandle),
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.gic_irq = {
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.type = cpu_to_fdt32(GIC_FDT_IRQ_TYPE_SPI),
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.num = cpu_to_fdt32(irq - GIC_SPI_IRQ_BASE),
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.flags = cpu_to_fdt32(IRQ_TYPE_EDGE_RISING),
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},
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};
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nentries++;
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dev_hdr = device__next_dev(dev_hdr);
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}
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_FDT(fdt_property(fdt, "interrupt-map", irq_map,
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sizeof(struct of_interrupt_map_entry) * nentries));
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/* ... and the corresponding mask. */
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if (nentries) {
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struct of_pci_irq_mask irq_mask = {
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.pci_addr = {
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.hi = cpu_to_fdt32(of_pci_b_ddddd(-1)),
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.mid = 0,
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.lo = 0,
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},
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.pci_pin = cpu_to_fdt32(7),
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};
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_FDT(fdt_property(fdt, "interrupt-map-mask", &irq_mask,
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sizeof(irq_mask)));
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}
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_FDT(fdt_end_node(fdt));
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}
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