ecf5e527ca
Add the driver for PowerVR Rogue graphics hardware. Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
152 lines
5.8 KiB
C
152 lines
5.8 KiB
C
/*************************************************************************/ /*!
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@File cache_km.h
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@Title CPU cache management header
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#ifndef CACHE_KM_H
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#define CACHE_KM_H
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#if defined(__linux__)
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#include <linux/version.h>
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#else
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#define KERNEL_VERSION
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#endif
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#include "pvrsrv_error.h"
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#include "os_cpu_cache.h"
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#include "img_types.h"
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#include "cache_ops.h"
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#include "device.h"
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#include "pmr.h"
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typedef IMG_UINT32 PVRSRV_CACHE_OP_ADDR_TYPE; /*!< Represents CPU address type required for CPU d-cache maintenance */
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#define PVRSRV_CACHE_OP_ADDR_TYPE_VIRTUAL 0x1 /*!< Operation requires CPU virtual address only */
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#define PVRSRV_CACHE_OP_ADDR_TYPE_PHYSICAL 0x2 /*!< Operation requires CPU physical address only */
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#define PVRSRV_CACHE_OP_ADDR_TYPE_BOTH 0x3 /*!< Operation requires both CPU virtual & physical addresses */
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#include "connection_server.h"
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/*
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* CacheOpInit() & CacheOpDeInit()
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*
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* This must be called to initialise the KM cache maintenance framework.
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* This is called early during the driver/module (un)loading phase.
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*/
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PVRSRV_ERROR CacheOpInit(void);
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void CacheOpDeInit(void);
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/*
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* CacheOpInit2() & CacheOpDeInit2()
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*
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* This must be called to initialise the UM cache maintenance framework.
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* This is called when the driver is loaded/unloaded from the kernel.
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*/
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PVRSRV_ERROR CacheOpInit2(void);
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void CacheOpDeInit2(void);
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/*
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* CacheOpExec()
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*
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* This is the primary CPU data-cache maintenance interface and it is
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* always guaranteed to be synchronous; the arguments supplied must be
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* pre-validated for performance reasons else the d-cache maintenance
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* operation might cause the underlying OS kernel to fault.
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*/
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PVRSRV_ERROR CacheOpExec(PPVRSRV_DEVICE_NODE psDevNode,
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void *pvVirtStart,
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void *pvVirtEnd,
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IMG_CPU_PHYADDR sCPUPhysStart,
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IMG_CPU_PHYADDR sCPUPhysEnd,
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PVRSRV_CACHE_OP uiCacheOp);
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/*
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* CacheOpValExec()
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*
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* Same as CacheOpExec(), except arguments are _Validated_ before being
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* presented to the underlying OS kernel for CPU data-cache maintenance.
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* The uiAddress is the start CPU virtual address for the to-be d-cache
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* maintained PMR, it can be NULL in which case a remap will be performed
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* internally, if required for cache maintenance. This is primarily used
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* as the services client bridge call handler for synchronous user-mode
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* cache maintenance requests.
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*/
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PVRSRV_ERROR CacheOpValExec(PMR *psPMR,
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IMG_UINT64 uiAddress,
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IMG_DEVMEM_OFFSET_T uiOffset,
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IMG_DEVMEM_SIZE_T uiSize,
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PVRSRV_CACHE_OP uiCacheOp);
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/*
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* CacheOpQueue()
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*
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* This is the secondary cache maintenance interface and it is not
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* guaranteed to be synchronous in that requests could be deferred
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* and executed asynchronously. This interface is primarily meant
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* as services client bridge call handler. Both uiInfoPgGFSeqNum
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* and ui32[Current,Next]FenceSeqNum implements an internal client
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* server queueing protocol so making use of this interface outside
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* of services client is not recommended and should not be done.
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*/
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PVRSRV_ERROR CacheOpQueue(CONNECTION_DATA *psConnection,
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PPVRSRV_DEVICE_NODE psDevNode,
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IMG_UINT32 ui32OpCount,
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PMR **ppsPMR,
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IMG_UINT64 *puiAddress,
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IMG_DEVMEM_OFFSET_T *puiOffset,
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IMG_DEVMEM_SIZE_T *puiSize,
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PVRSRV_CACHE_OP *puiCacheOp,
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IMG_UINT32 ui32OpTimeline);
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/*
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* CacheOpLog()
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*
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* This is used for logging client cache maintenance operations that
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* was executed in user-space.
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*/
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PVRSRV_ERROR CacheOpLog(PMR *psPMR,
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IMG_UINT64 uiAddress,
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IMG_DEVMEM_OFFSET_T uiOffset,
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IMG_DEVMEM_SIZE_T uiSize,
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IMG_UINT64 ui64StartTime,
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IMG_UINT64 ui64EndTime,
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PVRSRV_CACHE_OP uiCacheOp);
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#endif /* CACHE_KM_H */
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