636 lines
16 KiB
C
636 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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* Copyright 2015 Regents of the University of California
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* Copyright 2017 SiFive
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*
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* Copied from arch/tile/kernel/ptrace.c
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*/
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#include <asm/vector.h>
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#include <asm/ptrace.h>
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#include <asm/syscall.h>
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#include <asm/thread_info.h>
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#include <asm/switch_to.h>
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#include <linux/audit.h>
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#include <linux/compat.h>
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#include <linux/ptrace.h>
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#include <linux/elf.h>
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#include <linux/regset.h>
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#include <linux/sched.h>
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#include <linux/sched/task_stack.h>
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#include <linux/hw_breakpoint.h>
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enum riscv_regset {
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REGSET_X,
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#ifdef CONFIG_FPU
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REGSET_F,
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#endif
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#ifdef CONFIG_RISCV_ISA_V
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REGSET_V,
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#endif
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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REGSET_HW_BREAK,
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REGSET_HW_WATCH,
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#endif
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};
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static int riscv_gpr_get(struct task_struct *target,
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const struct user_regset *regset,
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struct membuf to)
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{
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return membuf_write(&to, task_pt_regs(target),
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sizeof(struct user_regs_struct));
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}
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static int riscv_gpr_set(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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const void *kbuf, const void __user *ubuf)
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{
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struct pt_regs *regs;
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regs = task_pt_regs(target);
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return user_regset_copyin(&pos, &count, &kbuf, &ubuf, regs, 0, -1);
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}
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#ifdef CONFIG_FPU
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static int riscv_fpr_get(struct task_struct *target,
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const struct user_regset *regset,
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struct membuf to)
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{
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struct __riscv_d_ext_state *fstate = &target->thread.fstate;
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if (target == current)
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fstate_save(current, task_pt_regs(current));
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membuf_write(&to, fstate, offsetof(struct __riscv_d_ext_state, fcsr));
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membuf_store(&to, fstate->fcsr);
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return membuf_zero(&to, 4); // explicitly pad
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}
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static int riscv_fpr_set(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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const void *kbuf, const void __user *ubuf)
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{
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int ret;
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struct __riscv_d_ext_state *fstate = &target->thread.fstate;
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, fstate, 0,
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offsetof(struct __riscv_d_ext_state, fcsr));
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if (!ret) {
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, fstate, 0,
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offsetof(struct __riscv_d_ext_state, fcsr) +
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sizeof(fstate->fcsr));
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}
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return ret;
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}
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#endif
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#ifdef CONFIG_RISCV_ISA_V
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static int riscv_vr_get(struct task_struct *target,
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const struct user_regset *regset,
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struct membuf to)
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{
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struct __riscv_v_ext_state *vstate = &target->thread.vstate;
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struct __riscv_v_regset_state ptrace_vstate;
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if (!riscv_v_vstate_query(task_pt_regs(target))) {
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if (riscv_v_thread_zalloc(target))
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return -EINVAL;
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riscv_v_vstate_on(task_pt_regs(target));
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if (target == current)
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riscv_v_vstate_restore(current, task_pt_regs(current));
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}
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/*
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* Ensure the vector registers have been saved to the memory before
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* copying them to membuf.
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*/
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if (target == current)
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riscv_v_vstate_save(current, task_pt_regs(current));
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ptrace_vstate.vstart = vstate->vstart;
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ptrace_vstate.vl = vstate->vl;
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ptrace_vstate.vtype = vstate->vtype;
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ptrace_vstate.vcsr = vstate->vcsr;
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ptrace_vstate.vlenb = vstate->vlenb;
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/* Copy vector header from vstate. */
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membuf_write(&to, &ptrace_vstate, sizeof(struct __riscv_v_regset_state));
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/* Copy all the vector registers from vstate. */
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return membuf_write(&to, vstate->datap, riscv_v_vsize);
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}
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static int riscv_vr_set(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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const void *kbuf, const void __user *ubuf)
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{
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int ret;
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struct __riscv_v_ext_state *vstate = &target->thread.vstate;
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struct __riscv_v_regset_state ptrace_vstate;
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if (!riscv_v_vstate_query(task_pt_regs(target))) {
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if (riscv_v_thread_zalloc(target))
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return -EINVAL;
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riscv_v_vstate_on(task_pt_regs(target));
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if (target == current)
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riscv_v_vstate_restore(current, task_pt_regs(current));
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}
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/* Copy rest of the vstate except datap */
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ptrace_vstate, 0,
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sizeof(struct __riscv_v_regset_state));
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if (unlikely(ret))
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return ret;
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if (vstate->vlenb != ptrace_vstate.vlenb)
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return -EINVAL;
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vstate->vstart = ptrace_vstate.vstart;
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vstate->vl = ptrace_vstate.vl;
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vstate->vtype = ptrace_vstate.vtype;
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vstate->vcsr = ptrace_vstate.vcsr;
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/* Copy all the vector registers. */
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pos = 0;
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate->datap,
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0, riscv_v_vsize);
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return ret;
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}
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#endif
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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static void ptrace_hbptriggered(struct perf_event *bp,
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struct perf_sample_data *data,
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struct pt_regs *regs)
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{
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struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp);
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force_sig_fault(SIGTRAP, TRAP_HWBKPT, (void __user *)bkpt->addr);
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}
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static int hw_break_get(struct task_struct *target,
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const struct user_regset *regset,
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struct membuf to)
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{
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/* send total number of h/w debug triggers */
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struct user_hwdebug_state hw_state;
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hw_state.dbg_slots = hw_breakpoint_slots(regset->core_note_type);
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membuf_write(&to, &hw_state, sizeof(hw_state));
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return 0;
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}
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static inline int hw_break_empty(u64 addr, u64 type, u64 len)
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{
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/* TODO: for now adjusted to current riscv-gdb behavior */
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return (!addr && !len);
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}
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static int hw_break_cache_trigger(struct task_struct *target, u32 note_type,
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u64 addr, u64 type, u64 len, u32 idx)
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{
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struct arch_hw_breakpoint *bp;
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u64 bp_type;
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u64 bp_len;
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// pr_info("%s:[%d] note_type=%d addr=%llx type=%lld len=%lld\n", __func__, idx, note_type, addr, type, len);
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if (!hw_break_empty(addr, type, len)) {
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/* bp len: gdb to kernel */
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switch (len) {
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case 2:
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bp_len = HW_BREAKPOINT_LEN_2;
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break;
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case 4:
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bp_len = HW_BREAKPOINT_LEN_4;
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break;
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case 8:
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bp_len = HW_BREAKPOINT_LEN_8;
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break;
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default:
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pr_warn("%s: unsupported len: %llu\n", __func__, len);
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return -EINVAL;
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}
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/* bp type: gdb to kernel */
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switch (type) {
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case 0:
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bp_type = HW_BREAKPOINT_X;
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break;
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case 1:
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bp_type = HW_BREAKPOINT_R;
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break;
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case 2:
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bp_type = HW_BREAKPOINT_W;
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break;
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case 3:
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bp_type = HW_BREAKPOINT_RW;
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break;
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default:
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pr_warn("%s: unsupported type: %llu\n", __func__, type);
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return -EINVAL;
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}
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}
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if (note_type == NT_RISCV_HW_BREAK)
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bp = &(target->thread.hbp_break[idx]);
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if (note_type == NT_RISCV_HW_WATCH)
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bp = &(target->thread.hbp_watch[idx]);
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bp->addr = addr;
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bp->type = bp_type;
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bp->len = bp_len;
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return 0;
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}
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static int hw_break_register_trigger(struct task_struct *target, u32 note_type,
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u64 addr, u64 type, u64 len, u32 idx)
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{
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struct perf_event *bp = ERR_PTR(-EINVAL);
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struct perf_event_attr attr;
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// pr_info("%s:[%d] note_type=%d addr=%llx type=%lld len=%lld\n", __func__, idx, note_type, addr, type, len);
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bp = target->thread.ptrace_bps[idx];
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if (bp) {
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attr = bp->attr;
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if (hw_break_empty(addr, type, len)) {
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attr.disabled = 1;
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} else {
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attr.bp_addr = addr;
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attr.bp_type = type;
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attr.bp_len = len;
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attr.disabled = 0;
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}
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return modify_user_hw_breakpoint(bp, &attr);
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}
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ptrace_breakpoint_init(&attr);
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attr.bp_addr = addr;
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attr.bp_type = type;
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attr.bp_len = len;
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bp = register_user_hw_breakpoint(&attr, ptrace_hbptriggered,
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NULL, target);
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if (IS_ERR(bp)) {
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pr_err("%s failed! ret=%ld\n", __func__, PTR_ERR(bp));
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return PTR_ERR(bp);
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}
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target->thread.ptrace_bps[idx] = bp;
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return 0;
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}
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static int hw_break_setup_trigger(struct task_struct *target)
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{
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u32 i, idx = 0;
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flush_ptrace_hw_breakpoint(target);
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for (i = 0; i < HW_BP_NUM_MAX; i++) {
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if (target->thread.hbp_break[i].addr) {
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hw_break_register_trigger(target, NT_RISCV_HW_BREAK, target->thread.hbp_break[i].addr, target->thread.hbp_break[i].type, target->thread.hbp_break[i].len, idx);
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idx++;
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}
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}
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for (i = 0; i < HW_BP_NUM_MAX; i++) {
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if (target->thread.hbp_watch[i].addr) {
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hw_break_register_trigger(target, NT_RISCV_HW_WATCH, target->thread.hbp_watch[i].addr, target->thread.hbp_watch[i].type, target->thread.hbp_watch[i].len, idx);
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idx++;
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}
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}
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return idx;
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}
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static int hw_break_set(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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const void *kbuf, const void __user *ubuf)
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{
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int ret, idx = 0, offset, limit, note_type;
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u64 addr;
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u64 type;
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u64 size;
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#define PTRACE_HBP_ADDR_SZ sizeof(u64)
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#define PTRACE_HBP_TYPE_SZ sizeof(u64)
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#define PTRACE_HBP_SIZE_SZ sizeof(u64)
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note_type = regset->core_note_type; // NT_RISCV_HW_BREAK(0x904) | NT_RISCV_HW_WATCH(0x905)
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/* Resource info and pad */
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offset = offsetof(struct user_hwdebug_state, dbg_regs);
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user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 0, offset);
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// pr_info("%s: core_note_type=%d count=%d offset=%d regset.n=%d regset.size=%d\n", __func__, regset->core_note_type, count, offset, regset->n, regset->size);
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/* trigger settings */
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limit = regset->n * regset->size;
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while (count && offset < limit) {
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if (count <= PTRACE_HBP_ADDR_SZ)
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return -EINVAL;
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &addr,
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offset, offset + PTRACE_HBP_ADDR_SZ);
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if (ret)
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return ret;
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offset += PTRACE_HBP_ADDR_SZ;
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &type,
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offset, offset + PTRACE_HBP_TYPE_SZ);
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if (ret)
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return ret;
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offset += PTRACE_HBP_TYPE_SZ;
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &size,
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offset, offset + PTRACE_HBP_SIZE_SZ);
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if (ret)
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return ret;
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offset += PTRACE_HBP_SIZE_SZ;
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ret = hw_break_cache_trigger(target, note_type, addr, type, size, idx);
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if (ret)
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return ret;
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idx++;
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}
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// pr_info("%s: count=%d offset=%d\n", __func__, count, offset);
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hw_break_setup_trigger(target);
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return 0;
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}
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#endif
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static const struct user_regset riscv_user_regset[] = {
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[REGSET_X] = {
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.core_note_type = NT_PRSTATUS,
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.n = ELF_NGREG,
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.size = sizeof(elf_greg_t),
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.align = sizeof(elf_greg_t),
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.regset_get = riscv_gpr_get,
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.set = riscv_gpr_set,
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},
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#ifdef CONFIG_FPU
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[REGSET_F] = {
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.core_note_type = NT_PRFPREG,
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.n = ELF_NFPREG,
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.size = sizeof(elf_fpreg_t),
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.align = sizeof(elf_fpreg_t),
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.regset_get = riscv_fpr_get,
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.set = riscv_fpr_set,
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},
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#endif
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#ifdef CONFIG_RISCV_ISA_V
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[REGSET_V] = {
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.core_note_type = NT_RISCV_VECTOR,
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.align = 16,
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.n = ((32 * RISCV_MAX_VLENB) +
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sizeof(struct __riscv_v_regset_state)) / sizeof(__u32),
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.size = sizeof(__u32),
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.regset_get = riscv_vr_get,
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.set = riscv_vr_set,
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},
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#endif
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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[REGSET_HW_BREAK] = {
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.core_note_type = NT_RISCV_HW_BREAK,
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.n = sizeof(struct user_hwdebug_state) / sizeof(u32),
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.size = sizeof(u32),
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.align = sizeof(u32),
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.regset_get = hw_break_get,
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.set = hw_break_set,
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},
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[REGSET_HW_WATCH] = {
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.core_note_type = NT_RISCV_HW_WATCH,
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.n = sizeof(struct user_hwdebug_state) / sizeof(u32),
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.size = sizeof(u32),
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.align = sizeof(u32),
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.regset_get = hw_break_get,
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.set = hw_break_set,
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},
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#endif
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};
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static const struct user_regset_view riscv_user_native_view = {
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.name = "riscv",
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.e_machine = EM_RISCV,
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.regsets = riscv_user_regset,
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.n = ARRAY_SIZE(riscv_user_regset),
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};
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struct pt_regs_offset {
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const char *name;
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int offset;
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};
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#define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
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#define REG_OFFSET_END {.name = NULL, .offset = 0}
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static const struct pt_regs_offset regoffset_table[] = {
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REG_OFFSET_NAME(epc),
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REG_OFFSET_NAME(ra),
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REG_OFFSET_NAME(sp),
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REG_OFFSET_NAME(gp),
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REG_OFFSET_NAME(tp),
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REG_OFFSET_NAME(t0),
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REG_OFFSET_NAME(t1),
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REG_OFFSET_NAME(t2),
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REG_OFFSET_NAME(s0),
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REG_OFFSET_NAME(s1),
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REG_OFFSET_NAME(a0),
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REG_OFFSET_NAME(a1),
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REG_OFFSET_NAME(a2),
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REG_OFFSET_NAME(a3),
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REG_OFFSET_NAME(a4),
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REG_OFFSET_NAME(a5),
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REG_OFFSET_NAME(a6),
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REG_OFFSET_NAME(a7),
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REG_OFFSET_NAME(s2),
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REG_OFFSET_NAME(s3),
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REG_OFFSET_NAME(s4),
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REG_OFFSET_NAME(s5),
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REG_OFFSET_NAME(s6),
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REG_OFFSET_NAME(s7),
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REG_OFFSET_NAME(s8),
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REG_OFFSET_NAME(s9),
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REG_OFFSET_NAME(s10),
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REG_OFFSET_NAME(s11),
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REG_OFFSET_NAME(t3),
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REG_OFFSET_NAME(t4),
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REG_OFFSET_NAME(t5),
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REG_OFFSET_NAME(t6),
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REG_OFFSET_NAME(status),
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REG_OFFSET_NAME(badaddr),
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REG_OFFSET_NAME(cause),
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REG_OFFSET_NAME(orig_a0),
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REG_OFFSET_END,
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};
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/**
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* regs_query_register_offset() - query register offset from its name
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* @name: the name of a register
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*
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* regs_query_register_offset() returns the offset of a register in struct
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* pt_regs from its name. If the name is invalid, this returns -EINVAL;
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*/
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int regs_query_register_offset(const char *name)
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{
|
|
const struct pt_regs_offset *roff;
|
|
|
|
for (roff = regoffset_table; roff->name != NULL; roff++)
|
|
if (!strcmp(roff->name, name))
|
|
return roff->offset;
|
|
return -EINVAL;
|
|
}
|
|
|
|
/**
|
|
* regs_within_kernel_stack() - check the address in the stack
|
|
* @regs: pt_regs which contains kernel stack pointer.
|
|
* @addr: address which is checked.
|
|
*
|
|
* regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
|
|
* If @addr is within the kernel stack, it returns true. If not, returns false.
|
|
*/
|
|
static bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr)
|
|
{
|
|
return (addr & ~(THREAD_SIZE - 1)) ==
|
|
(kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1));
|
|
}
|
|
|
|
/**
|
|
* regs_get_kernel_stack_nth() - get Nth entry of the stack
|
|
* @regs: pt_regs which contains kernel stack pointer.
|
|
* @n: stack entry number.
|
|
*
|
|
* regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
|
|
* is specified by @regs. If the @n th entry is NOT in the kernel stack,
|
|
* this returns 0.
|
|
*/
|
|
unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n)
|
|
{
|
|
unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
|
|
|
|
addr += n;
|
|
if (regs_within_kernel_stack(regs, (unsigned long)addr))
|
|
return *addr;
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
void ptrace_disable(struct task_struct *child)
|
|
{
|
|
}
|
|
|
|
long arch_ptrace(struct task_struct *child, long request,
|
|
unsigned long addr, unsigned long data)
|
|
{
|
|
long ret = -EIO;
|
|
|
|
switch (request) {
|
|
default:
|
|
ret = ptrace_request(child, request, addr, data);
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
#if IS_ENABLED(CONFIG_COMPAT) || IS_ENABLED(CONFIG_ARCH_RV64ILP32)
|
|
static int compat_riscv_gpr_get(struct task_struct *target,
|
|
const struct user_regset *regset,
|
|
struct membuf to)
|
|
{
|
|
struct compat_user_regs_struct cregs;
|
|
|
|
regs_to_cregs(&cregs, task_pt_regs(target));
|
|
|
|
return membuf_write(&to, &cregs,
|
|
sizeof(struct compat_user_regs_struct));
|
|
}
|
|
|
|
static int compat_riscv_gpr_set(struct task_struct *target,
|
|
const struct user_regset *regset,
|
|
unsigned int pos, unsigned int count,
|
|
const void *kbuf, const void __user *ubuf)
|
|
{
|
|
int ret;
|
|
struct compat_user_regs_struct cregs;
|
|
|
|
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &cregs, 0, -1);
|
|
|
|
cregs_to_regs(&cregs, task_pt_regs(target));
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct user_regset compat_riscv_user_regset[] = {
|
|
[REGSET_X] = {
|
|
.core_note_type = NT_PRSTATUS,
|
|
.n = ELF_NGREG,
|
|
.size = sizeof(compat_elf_greg_t),
|
|
.align = sizeof(compat_elf_greg_t),
|
|
.regset_get = compat_riscv_gpr_get,
|
|
.set = compat_riscv_gpr_set,
|
|
},
|
|
#ifdef CONFIG_FPU
|
|
[REGSET_F] = {
|
|
.core_note_type = NT_PRFPREG,
|
|
.n = ELF_NFPREG,
|
|
.size = sizeof(elf_fpreg_t),
|
|
.align = sizeof(elf_fpreg_t),
|
|
.regset_get = riscv_fpr_get,
|
|
.set = riscv_fpr_set,
|
|
},
|
|
#endif
|
|
};
|
|
|
|
static const struct user_regset_view compat_riscv_user_native_view = {
|
|
.name = "riscv",
|
|
.e_machine = EM_RISCV,
|
|
.regsets = compat_riscv_user_regset,
|
|
.n = ARRAY_SIZE(compat_riscv_user_regset),
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
|
|
compat_ulong_t caddr, compat_ulong_t cdata)
|
|
{
|
|
long ret = -EIO;
|
|
|
|
switch (request) {
|
|
default:
|
|
ret = compat_ptrace_request(child, request, caddr, cdata);
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
#endif /* CONFIG_COMPAT */
|
|
|
|
const struct user_regset_view *task_user_regset_view(struct task_struct *task)
|
|
{
|
|
#if IS_ENABLED(CONFIG_COMPAT) || IS_ENABLED(CONFIG_ARCH_RV64ILP32)
|
|
if (test_tsk_thread_flag(task, TIF_32BIT) &&
|
|
!test_tsk_thread_flag(task, TIF_64ILP32))
|
|
return &compat_riscv_user_native_view;
|
|
else
|
|
#endif
|
|
return &riscv_user_native_view;
|
|
}
|