OERV-BSP/kernel-zhihe-a210
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cb381faa1ea3b70af4ca18ce6073ab368fb14dd5
kernel-zhihe-a210/arch/riscv/boot/dts/zhihe/a210-soc-peri.dtsi
hongyi 218862ffdd Release develop 260205
2026-02-05 10:48:51 +08:00

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#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/a210-clock.h>
#include <dt-bindings/iommu/zh-iommu.h>
#include <dt-bindings/ata/ahci.h>
/ {
display-subsystem {
compatible = "verisilicon,display-subsystem";
ports = <&dpu_disp0>, <&dpu_disp1>, <&auxdisp_out>;
};
dpu-encoders {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
dpu_enc0: dpu-encoder@0 {
/* default encoder is DSI. */
compatible = "verisilicon,dsi-encoder";
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/* input */
port@0 {
reg = <0>;
dsi_enc_in: endpoint {
remote-endpoint = <&auxdisp_to_dsi>;
};
};
/* output */
port@1 {
reg = <1>;
dsi_enc_out: endpoint {
// remote-endpoint = <&dsi0_in>;
};
};
};
};
};
reg_vref_1v8: regulator-adc-verf {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
vdec_opp_table: opp_table_vdec {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <750000 750000 800000>;
};
opp01 {
opp-hz = /bits/ 64 <786432000>;
opp-microvolt = <800000 750000 800000>;
};
};
venc_opp_table: opp_table_venc {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <528000000>;
opp-microvolt = <750000 750000 800000>;
};
opp01 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <800000 750000 800000>;
};
};
g2d_opp_table: opp_table_g2d {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <600000000>;
aclk-hz = /bits/ 64 <528000000>;
opp-microvolt = <750000 750000 800000>;
};
opp01 {
opp-hz = /bits/ 64 <786432000>;
aclk-hz = /bits/ 64 <880000000>;
opp-microvolt = <800000 750000 800000>;
};
};
soc {
teesys_syscon: teesys-reg@0027400000 {
compatible = "syscon";
reg = <0x00 0x27400000 0x0 0x1000>;
};
nvmem_controller: efuse@0027410000 {
compatible = "zhihe,a210-fm-efuse", "syscon";
reg = <0x00 0x27410000 0x0 0x10000>;
zhihe,teesys = <&teesys_syscon>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&clk_peri TEE_EFUSE_CLKEN>;
clock-names = "pclk";
gmac0_mac_address: gmac0-mac-address {
reg = <0xb0 6>;
};
gmac1_mac_address: gmac1-mac-address {
reg = <0xb8 6>;
};
};
dsi0: dw-mipi-dsi0@6700000{
compatible = "simple-bus", "syscon";
reg = <0x00 0x6700000 0x0 0x10000>;
power-domains = <&power_vo>;
dphy_0: dsi0-dphy {
compatible = "zhihe,a210-mipi-dphy";
regmap = <&dsi0>;
vosys-regmap = <&vosys_reg>;
clocks = <&osc_24m>,
<&clk_vo VO_MIPI_CFGCLK_EN>,
<&clk_vo VO_MIPI_PCLK_EN>,
<&clk_vo VO_MIPI_PIXCLK>,
<&osc_24m>;
clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk";
#phy-cells = <0>;
};
dsi_host0: dsi0-host {
compatible = "verisilicon,dw-mipi-dsi";
regmap = <&dsi0>;
interrupt-parent = <&intc>;
interrupts = <213>;
clocks = <&clk_vo VO_MIPI_CFGCLK_EN>,
<&clk_vo VO_MIPI_PCLK_EN>,
<&clk_vo VO_MIPI_PIXCLK>;
clock-names = "cfgclk", "pclk", "pixclk";
phys = <&dphy_0>;
phy-names = "dphy";
#address-cells = <1>;
#size-cells = <0>;
};
};
vosys_reg: vosys@6e06000{
compatible = "thead,light-vo-subsys", "syscon";
reg = <0x00 0x06e06000 0x0 0x1000>;
};
peri1_sys: syscon@02010000{
compatible = "syscon";
reg = <0x00 0x02010000 0x0 0x1000>;
};
hdmi_tx: dw-hdmi-tx@6600000 {
compatible = "thead,light-hdmi-tx";
reg = <0x00 0x6600000 0x0 0x40000>;
interrupt-parent = <&intc>;
interrupts = <216>;
clocks = <&clk_vo VO_HDMI_PCLK_EN>,
<&clk_vo VO_HDMI_SFRCLK_EN>,
<&clk_vo VO_CEC_CLK_EN>,
<&clk_vo VO_HDMI_PIXCLK>;
clock-names = "iahb", "isfr", "cec", "pixclk";
power-domains = <&power_vo>;
reg-io-width = <4>;
phy_version = <301>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
hdmi_tx_in0: endpoint@0 {
reg = <0>;
remote-endpoint = <&disp1_out>;
};
};
/* i2s input */
port@1 {
reg = <1>;
hdmi_i2s_rx: endpoint {
remote-endpoint = <&hdmi_i2s_tx>;
};
};
};
};
dp0: dp-tx@8010000 {
compatible = "zhihe,dw-dp";
reg = <0x0 0x8010000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <179>;
clocks = <&clk_usb DPTX_I2S_CLK_EN>,
<&clk_usb DPTX_IPI_CLK_EN>,
<&clk_usb DPTX_AUX_CLK_EN>,
<&clk_usb DPTX_GTC_CLK_EN>,
<&clk_usb DPTX_PCLK_EN>;
clock-names = "i2s", "ipi", "aux", "gtc", "pclk";
power-domains = <&power_vo>;
#sound-dai-cells = <1>;
phys = <&usbdp_phy0_dp>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dp_tx_in: endpoint {
remote-endpoint = <&disp0_out>;
};
};
};
};
dpu: dc8200@6400000{
compatible = "verisilicon,dc8200";
reg = <0x00 0x6400000 0x0 0x100>, <0x00 0x6400800 0x0 0x2000>, <0x00 0x6430010 0x0 0x60>;
interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <218>;
clocks = <&clk_vo VO_DPUC_CLK_EN>,
<&clk_vo VO_DPU_ACLK_EN>,
<&clk_vo VO_DPU_HCLK_EN>,
<&clk_vo VO_CH0_PIXCLK_EN>,
<&clk_vo VO_CH1_PIXCLK_EN>,
<&clk DPU0_PLL_FOUTPOSTDIV>,
<&clk DPU1_PLL_FOUTPOSTDIV>,
<&clk_vo VO_MIPI_PIXCLK>,
<&clk_vo VO_HDMI_PIXCLK>,
<&clk_vo VO_DPTX_PIXCLK>;
clock-names = "core_clk", "axi_clk", "cfg_clk",
"pixclk0", "pixclk1", "dpu0_pll_foutpostdiv", "dpu1_pll_foutpostdiv",
"mipi_pixclk", "hdmi_pixclk", "dptx_pixclk";
power-domains = <&power_vo>;
vosys-regmap = <&vosys_reg>;
zhihe-a210;
dpu_disp0: port@0 {
reg = <0>;
disp0_out: endpoint {
remote-endpoint = <&dp_tx_in>;
};
};
dpu_disp1: port@1 {
reg = <1>;
disp1_out: endpoint {
remote-endpoint = <&hdmi_tx_in0>;
};
};
};
auxdisp: auxdisp@6740000 {
compatible = "zhihe,auxdisp";
reg = <0x00 0x6740000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <228>;
clocks = <&clk_vo VO_AUXDISP_ACLK_EN>,
<&clk_vo VO_AUXDISP_PCLK_EN>,
<&clk_vo VO_CH2_PIXCLK_EN>,
<&clk_vo VO_HDMI_PIXCLK>,
<&clk_vo VO_MIPI_PIXCLK>,
<&clk_vo VO_DPTX_PIXCLK>;
clock-names = "aclk", "pclk", "pixclk", "hdmi_pixclk", "mipi_pixclk", "dptx_pixclk";
#address-cells = <1>;
#size-cells = <0>;
auxdisp_out: port@0 {
reg = <0>;
auxdisp_to_dsi: endpoint@0 {
remote-endpoint = <&dsi_enc_in>;
};
};
};
gpu_opp_table: gpu-opp-table {
compatible = "operating-points-v2";
opp-528000000 {
opp-hz = /bits/ 64 <528000000>;
opp-microvolt = <750000>;
};
opp-792000000 {
opp-hz = /bits/ 64 <792000000>;
opp-microvolt = <800000>;
};
};
gpu: gpu@6c00000{
compatible = "img,gpu";
reg = <0x00 0x6c00000 0x0 0x100000>;
interrupt-parent = <&intc>;
interrupts = <72>;
interrupt-names = "gpuirq";
power-domains = <&power_gpu>;
vosys-regmap = <&vosys_reg>;
dma-mask = <0xf 0xffffffff>;
clocks = <&clk_gpu SW_PWR_WRAP_GPU_CORE_CLK_EN>;
clock-names = "gpu_core_clk ";
operating-points-v2 = <&gpu_opp_table>;
};
watchdog0: watchdog@00305000 {
compatible = "snps,dw-wdt";
reg = <0x00 0x00305000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <331>;
clocks = <&clk_peri PERI0_WDT0_PCLK_EN>;
power-domains = <&power_top>;
clock-names = "tclk";
resets = <&rst PERI0_WDT0_PRST>;
};
aon_wdt0: aon_wdt@0 {
compatible = "zhihe,aon_wdt";
};
can0: flexcan@2000000 {
compatible = "fsl,zha210-flexcan";
reg = <0x00 0x2000000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <261>;
clocks = <&clk_peri PERI1_CAN0_HIRES_CLK_EN>,
<&clk_peri PERI1_CAN0_PCLK_EN>;
clock-names = "ipg", "per";
power-domains = <&power_top>;
/* fsl,stop-mode = <&gpr 0x34 29 0x10 18>; */
};
can1: flexcan@2004000 {
compatible = "fsl,zha210-flexcan";
reg = <0x00 0x2004000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <262>;
clocks = <&clk_peri PERI1_CAN1_HIRES_CLK_EN>,
<&clk_peri PERI1_CAN1_PCLK_EN>;
clock-names = "ipg", "per";
power-domains = <&power_top>;
/* fsl,stop-mode = <&gpr 0x34 29 0x10 18>; */
};
can2: flexcan@8420000 {
compatible = "fsl,zha210-flexcan";
reg = <0x00 0x8420000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <263>;
clocks = <&clk_peri PERI2_CAN2_HIRES_CLK_EN>,
<&clk_peri PERI2_CAN2_PCLK_EN>;
clock-names = "ipg", "per";
power-domains = <&power_peri2>;
/* fsl,stop-mode = <&gpr 0x34 29 0x10 18>; */
};
rtc: rtc@30840000 {
compatible = "snps,dw-apb-rtc";
reg = <0x00 0x30840000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <18>;
clocks = <&osc_32k>;
clock-names = "osc_32k";
wakeup-source;
prescaler = <0x8000>;
};
dmac0: dmac@0000520000 {
compatible = "zhihe,a210-axi-dma";
reg = <0x00 0x00520000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <264>;
clocks = <&clk_peri PERI3_DMAC_ACLK_EN>, <&clk_peri PERI3_DMAC_HCLK_EN>;
clock-names = "core-clk", "cfgr-clk";
power-domains = <&power_peri3>;
//iommus = <&iommu DEVID_DIE0_DMAC_AP>;
#dma-cells = <1>;
dma-channels = <16>;
snps,block-size = <65536 65536 65536 65536 65536 65536 65536 65536
65536 65536 65536 65536 65536 65536 65536 65536>;
snps,priority = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>;
snps,dma-masters = <1>;
snps,data-width = <4>;
snps,axi-max-burst-len = <4>;
};
dmac1: tee_dmac@27540000 {
compatible = "zhihe,a210-axi-dma";
reg = <0x00 0x27540000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <259>;
clocks = <&clk_peri TEE_DMAC_CLKEN>, <&clk_peri TEE_DMAC_CLKEN>;
clock-names = "core-clk", "cfgr-clk";
#dma-cells = <1>;
dma-channels = <4>;
snps,block-size = <65536 65536 65536 65536>;
snps,priority = <0 0 0 0>;
snps,dma-masters = <1>;
snps,data-width = <4>;
snps,axi-max-burst-len = <16>;
//iommus = <&iommu DEVID_DIE0_TEE_DMAC>;
};
uart0: serial@02014000 {
compatible = "snps,dw-apb-uart";
reg = <0x00 0x02014000 0x0 0x400>;
interrupt-parent = <&intc>;
interrupts = <321>;
clocks = <&clk_peri PERI1_UART0_PCLK_EN>, <&clk_peri PERI1_UART0_SCLK_EN>;
clock-names = "apb_pclk", "baudclk";
power-domains = <&power_top>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart1: serial@02015000 {
compatible = "snps,dw-apb-uart";
reg = <0x00 0x02015000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <322>;
clocks = <&clk_peri PERI1_UART1_PCLK_EN>, <&clk_peri PERI1_UART1_SCLK_EN>;
clock-names = "apb_pclk", "baudclk";
power-domains = <&power_top>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart2: serial@02016000 {
compatible = "snps,dw-apb-uart";
reg = <0x00 0x02016000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <323>;
clocks = <&clk_peri PERI1_UART2_PCLK_EN>, <&clk_peri PERI1_UART2_SCLK_EN>;
clock-names = "apb_pclk", "baudclk";
power-domains = <&power_top>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart3: serial@02017000 {
compatible = "snps,dw-apb-uart";
reg = <0x00 0x02017000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <324>;
clocks = <&clk_peri PERI1_UART3_PCLK_EN>, <&clk_peri PERI1_UART3_SCLK_EN>;
clock-names = "apb_pclk", "baudclk";
power-domains = <&power_top>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart4: serial@08401000 {
compatible = "snps,dw-apb-uart";
reg = <0x00 0x08401000 0x0 0x400>;
interrupt-parent = <&intc>;
interrupts = <325>;
clocks = <&clk_peri PERI2_UART4_PCLK_EN>, <&clk_peri PERI2_UART4_SCLK_EN>;
clock-names = "apb_pclk", "baudclk";
power-domains = <&power_peri2>;
reg-shift = <2>;
reg-io-width = <4>;
current-speed = <115200>; /* OpenSBI */
};
uart5: serial@08402000 {
compatible = "snps,dw-apb-uart";
reg = <0x00 0x08402000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <326>;
clocks = <&clk_peri PERI2_UART5_PCLK_EN>, <&clk_peri PERI2_UART5_SCLK_EN>;
clock-names = "apb_pclk", "baudclk";
power-domains = <&power_peri2>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart6: serial@08403000 {
compatible = "snps,dw-apb-uart";
reg = <0x00 0x08403000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <327>;
clocks = <&clk_peri PERI2_UART6_PCLK_EN>, <&clk_peri PERI2_UART6_SCLK_EN>;
clock-names = "apb_pclk", "baudclk";
power-domains = <&power_peri2>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart7: serial@08404000 {
compatible = "snps,dw-apb-uart";
reg = <0x00 0x08404000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <328>;
clocks = <&clk_peri PERI2_UART7_PCLK_EN>, <&clk_peri PERI2_UART7_SCLK_EN>;
clock-names = "apb_pclk", "baudclk";
power-domains = <&power_peri2>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart8: serial@08405000 {
compatible = "snps,dw-apb-uart";
reg = <0x00 0x08405000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <329>;
clocks = <&clk_peri PERI2_UART8_PCLK_EN>, <&clk_peri PERI2_UART8_SCLK_EN>;
clock-names = "apb_pclk", "baudclk";
power-domains = <&power_peri2>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart9: serial@08406000 {
compatible = "snps,dw-apb-uart";
reg = <0x00 0x08406000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <330>;
clocks = <&clk_peri PERI2_UART9_PCLK_EN>, <&clk_peri PERI2_UART9_SCLK_EN>;
clock-names = "apb_pclk", "baudclk";
power-domains = <&power_peri2>;
reg-shift = <2>;
reg-io-width = <4>;
};
adc: adc@5a0000 {
compatible = "zhihe,a210-adc";
reg = <0x00 0x5a0000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <260>;
clocks = <&clk_peri PERI3_ADC_PCLK_EN>;
power-domains = <&power_peri3>;
clock-names = "adc";
};
spi0: spi@02023000 {
compatible = "snps,dw-apb-ssi";
reg = <0x00 0x02023000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <310>;
clocks = <&clk_peri PERI1_SPI0_SSI_CLK_EN>;
clock-names = "sclk";
power-domains = <&power_top>;
dmas = <&dmac0 9>, <&dmac0 8>;
dma-names = "tx", "rx";
dma-tx-addr-incr;
dma-rx-addr-incr;
reg-map-size = <144>;
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@08413000 {
compatible = "snps,dw-apb-ssi";
reg = <0x00 0x08413000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <311>;
clocks = <&clk_peri PERI2_SPI1_SSI_CLK_EN>;
clock-names = "sclk";
power-domains = <&power_peri2>;
dmas = <&dmac0 62>, <&dmac0 61>;
dma-names = "tx", "rx";
dma-tx-addr-incr;
dma-rx-addr-incr;
reg-map-size = <144>;
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
qspi0: spi@01000000 {
compatible = "snps,dw-apb-ssi-quad";
reg = <0x00 0x01000000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <308>;
clocks = <&clk_peri PERI1_QSPI0_SSI_CLK_EN>;
clock-names = "sclk";
power-domains = <&power_top>;
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
qspi1: spi@08428000 {
compatible = "snps,dw-apb-ssi-quad";
reg = <0x00 0x08428000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <309>;
clocks = <&clk_peri PERI2_QSPI1_SSI_CLK_EN>;
clock-names = "sclk";
power-domains = <&power_peri2>;
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
emmc: sdhci@00500000 {
compatible = "zhihe,a210-dwcmshc";
reg = <0x0 0x00500000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <265>;
interrupt-names = "sdhciirq";
clocks = <&clk_peri PERI3_EMMC_SDIO_REF_CLK_CG_EN>,
<&clk_peri PERI3_EMMC_HCLK_EN>;
clock-names = "core", "bus";
power-domains = <&power_peri3>;
//iommus = <&iommu DEVID_DIE0_EMMC>;
clk-delay-mmc-hs200 = <50>;
clk-delay-mmc-hs400 = <24>;
};
sdhci0: sd@00510000 {
compatible = "zhihe,a210-dwcmshc";
reg = <0x00 0x00510000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <337>;
interrupt-names = "sdhci0irq";
clocks = <&clk_peri PERI3_EMMC_SDIO_REF_CLK_CG_EN>,
<&clk_peri PERI3_EMMC_HCLK_EN>;
clock-names = "core", "bus";
power-domains = <&power_peri3>;
//iommus = <&iommu DEVID_DIE0_SD>;
clk-delay-default = <46>;
clk-delay-uhs-sdr104 = <46>;
};
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <7>;
snps,rd_osr_lmt = <7>;
snps,blen = <16 8 4 0 0 0 0>;
};
gmac0_sys: syscon@0210F000 {
compatible = "syscon";
reg = <0x00 0x0210f000 0x0 0x20>;
};
gmac1_sys: syscon@0211F000 {
compatible = "syscon";
reg = <0x00 0x0211f000 0x0 0x20>;
};
gmac0: ethernet@0002100000{
compatible = "zhihe,a210-dwmac", "snps,dwmac-5.40a";
reg = <0x00 0x02100000 0x0 0x10000>;
reg-names = "gmac";
interrupt-parent = <&intc>;
interrupts = <277>;
interrupt-names = "macirq";
clocks = <&clk_peri PERI1_GMAC0_ACLK_EN>,
<&clk_peri PERI1_GMAC0_HCLK_EN>;
clock-names = "gmac_aclk", "gmac_hclk";
power-domains = <&power_top>;
snps,pbl = <32>;
snps,fixed-burst;
snps,axi-config = <&stmmac_axi_setup>;
snps,tso;
zhihe,gmacsys = <&gmac0_sys>;
// iommus = <&iommu DEVID_DIE0_GMAC_0>;
mdio0: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
gmac1: ethernet@02110000 {
compatible = "zhihe,a210-dwmac", "snps,dwmac-5.40a";
reg = <0x00 0x02110000 0x0 0x10000>;
reg-names = "gmac";
interrupt-parent = <&intc>;
interrupts = <288>;
interrupt-names = "macirq";
clocks = <&clk_peri PERI1_GMAC1_ACLK_EN>,
<&clk_peri PERI1_GMAC1_HCLK_EN>;
clock-names = "gmac_aclk", "gmac_hclk";
power-domains = <&power_top>;
snps,pbl = <32>;
snps,fixed-burst;
snps,axi-config = <&stmmac_axi_setup>;
snps,tso;
zhihe,gmacsys = <&gmac1_sys>;
// iommus = <&iommu DEVID_DIE0_GMAC_1>;
mdio1: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
aon_padctrl: aon-padctrl@30848000 {
compatible = "zhihe,a210-group0-pinctrl";
reg = <0x00 0x30848000 0x0 0x2000>;
clocks = <&aon_110m>;
clock-names = "pclk";
};
gpio@30841000 {
compatible = "snps,dw-apb-gpio";
reg = <0x00 0x30841000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&aon_110m>, <&osc_32k>;
clock-names = "bus", "db";
ao_gpio0: ao_gpio0-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
gpio-ranges = <&aon_padctrl 0 8 15>, <&aon_padctrl 21 23 11>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <17>;
};
};
gpio@30897000 {
compatible = "snps,dw-apb-gpio";
reg = <0x00 0x30897000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&aon_110m>, <&osc_32k>;
clock-names = "bus", "db";
ao_gpio1: ao_gpio1-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <10>;
gpio-ranges = <&aon_padctrl 0 34 10>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <10>;
};
};
peri1_padctrl: peri1-padctrl@02026000 {
compatible = "zhihe,a210-group1-pinctrl";
reg = <0x00 0x02026000 0x0 0x1000>;
clocks = <&clk_peri PERI1_PAD_CTRL_PCLK_EN>;
clock-names = "pclk";
};
peri2_padctrl: peri2-padctrl@08411000 {
compatible = "zhihe,a210-group2-pinctrl";
reg = <0x00 0x08411000 0x0 0x1000>;
clocks = <&clk_peri PERI2_PAD_CTRL_PCLK_EN>;
clock-names = "pclk";
};
peri3_padctrl: peri3-padctrl@00542000 {
compatible = "zhihe,a210-group3-pinctrl";
reg = <0x00 0x00542000 0x0 0x1000>;
clocks = <&clk_peri PERI3_PAD_CTRL_PCLK_EN>;
clock-names = "pclk";
};
gpio@02012000 {
compatible = "snps,dw-apb-gpio";
reg = <0x00 0x02012000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk_peri PERI1_GPIO0_PCLK_EN>,
<&clk_peri PERI1_GPIO0_DBCLK_EN>;
clock-names = "bus", "db";
power-domains = <&power_top>;
gpio0: gpio0-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
gpio-ranges = <&peri1_padctrl 0 0 32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <289>;
};
};
gpio@02013000 {
compatible = "snps,dw-apb-gpio";
reg = <0x00 0x02013000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk_peri PERI1_GPIO1_PCLK_EN>,
<&clk_peri PERI1_GPIO1_DBCLK_EN>;
clock-names = "bus", "db";
power-domains = <&power_top>;
gpio1: gpio1-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <18>;
gpio-ranges = <&peri1_padctrl 0 32 18>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <290>;
};
};
gpio@08410000 {
compatible = "snps,dw-apb-gpio";
reg = <0x00 0x08410000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk_peri PERI2_GPIO2_PCLK_EN>,
<&clk_peri PERI2_GPIO2_DBCLK_EN>;
clock-names = "bus", "db";
power-domains = <&power_peri2>;
gpio2: gpio2-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
gpio-ranges = <&peri2_padctrl 0 0 32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <291>;
};
};
gpio@08412000 {
compatible = "snps,dw-apb-gpio";
reg = <0x00 0x08412000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk_peri PERI2_GPIO3_PCLK_EN>,
<&clk_peri PERI2_GPIO3_DBCLK_EN>;
clock-names = "bus", "db";
power-domains = <&power_peri2>;
gpio3: gpio3-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <11>;
gpio-ranges = <&peri2_padctrl 0 32 11>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <292>;
};
};
gpio@00550000 {
compatible = "snps,dw-apb-gpio";
reg = <0x00 0x00550000 0x0 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk_peri PERI3_GPIO4_PCLK_EN>,
<&clk_peri PERI3_GPIO4_DBCLK_EN>;
clock-names = "bus", "db";
power-domains = <&power_peri3>;
gpio4: gpio4-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <6>;
gpio-ranges = <&peri3_padctrl 0 0 6>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <52>;
};
};
pwm0: pwm@0202A000 {
compatible = "zhihe,a210-pwm";
reg = <0x00 0x0202A000 0x0 0x1000>;
#pwm-cells = <2>;
clocks = <&clk_peri PERI1_PWM0_CCLK_EN>;
clock-names = "cclk";
power-domains = <&power_top>;
interrupts = <305>;
interrupt-parent = <&intc>;
};
pwm1: pwm@0841A000 {
compatible = "zhihe,a210-pwm";
reg = <0x00 0x0841A000 0x0 0x1000>;
#pwm-cells = <2>;
clocks = <&clk_peri PERI2_PWM1_CCLK_EN>;
clock-names = "cclk";
power-domains = <&power_peri2>;
interrupts = <306>;
interrupt-parent = <&intc>;
};
pwm2: pwm@0841B000 {
compatible = "zhihe,a210-pwm";
reg = <0x00 0x0841B000 0x0 0x1000>;
#pwm-cells = <2>;
clocks = <&clk_peri PERI2_PWM2_CCLK_EN>;
clock-names = "cclk";
power-domains = <&power_peri2>;
interrupts = <307>;
interrupt-parent = <&intc>;
};
timer0: timer0@00303000 {
compatible = "snps,dw-apb-timer";
reg = <0x00 0x00303000 0x0 0x14>;
clocks = <&clk_peri PERI0_TIMER0_PCLK_EN>, <&clk_peri PERI0_TIMER0_CCLK_EN>;
clock-names = "pclk", "timer";
resets = <&rst PERI0_TIMER0_RST>;
interrupts = <313>;
interrupt-parent = <&intc>;
};
timer1: timer1@00303014 {
compatible = "snps,dw-apb-timer";
reg = <0x00 0x00303014 0x0 0x14>;
clocks = <&clk_peri PERI0_TIMER0_PCLK_EN>, <&clk_peri PERI0_TIMER0_CCLK_EN>;
clock-names = "pclk", "timer";
resets = <&rst PERI0_TIMER0_RST>;
interrupts = <314>;
interrupt-parent = <&intc>;
};
timer2: timer2@00303028 {
compatible = "snps,dw-apb-timer";
reg = <0x00 0x00303028 0x0 0x14>;
clocks = <&clk_peri PERI0_TIMER0_PCLK_EN>, <&clk_peri PERI0_TIMER0_CCLK_EN>;
clock-names = "pclk", "timer";
resets = <&rst PERI0_TIMER0_RST>;
interrupts = <315>;
interrupt-parent = <&intc>;
};
timer3: timer3@0030303c {
compatible = "snps,dw-apb-timer";
reg = <0x00 0x0030303c 0x0 0x14>;
clocks = <&clk_peri PERI0_TIMER0_PCLK_EN>, <&clk_peri PERI0_TIMER0_CCLK_EN>;
clock-names = "pclk", "timer";
resets = <&rst PERI0_TIMER0_RST>;
interrupts = <316>;
interrupt-parent = <&intc>;
};
timer4: timer4@00304000 {
compatible = "snps,dw-apb-timer";
reg = <0x00 0x00304000 0x0 0x14>;
clocks = <&clk_peri PERI0_TIMER1_PCLK_EN>, <&clk_peri PERI0_TIMER1_CCLK_EN>;
clock-names = "pclk", "timer";
resets = <&rst PERI0_TIMER1_RST>;
interrupts = <317>;
interrupt-parent = <&intc>;
};
timer5: timer5@00304014 {
compatible = "snps,dw-apb-timer";
reg = <0x00 0x00304014 0x0 0x14>;
clocks = <&clk_peri PERI0_TIMER1_PCLK_EN>, <&clk_peri PERI0_TIMER1_CCLK_EN>;
clock-names = "pclk", "timer";
resets = <&rst PERI0_TIMER1_RST>;
interrupts = <318>;
interrupt-parent = <&intc>;
};
timer6: timer6@00304028 {
compatible = "snps,dw-apb-timer";
reg = <0x00 0x00304028 0x0 0x14>;
clocks = <&clk_peri PERI0_TIMER1_PCLK_EN>, <&clk_peri PERI0_TIMER1_CCLK_EN>;
clock-names = "pclk", "timer";
resets = <&rst PERI0_TIMER1_RST>;
interrupts = <319>;
interrupt-parent = <&intc>;
};
timer7: timer7@0030403c {
compatible = "snps,dw-apb-timer";
reg = <0x00 0x0030403c 0x0 0x14>;
clocks = <&clk_peri PERI0_TIMER1_PCLK_EN>, <&clk_peri PERI0_TIMER1_CCLK_EN>;
clock-names = "pclk", "timer";
resets = <&rst PERI0_TIMER1_RST>;
interrupts = <320>;
interrupt-parent = <&intc>;
};
i2c0: i2c@02020000 {
compatible = "snps,designware-i2c";
reg = <0x00 0x02020000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <293>;
clocks = <&clk_peri PERI1_I2C0_IC_CLK_EN>, <&clk_peri PERI1_I2C0_PCLK_EN>;
clock-names = "ref", "pclk";
power-domains = <&power_top>;
dma-mode;
dmas = <&dmac0 21>, <&dmac0 20>;
dma-names = "tx", "rx";
dma-burst-len = <1>, <1>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@02021000 {
compatible = "snps,designware-i2c";
reg = <0x00 0x02021000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <294>;
clocks = <&clk_peri PERI1_I2C1_IC_CLK_EN>, <&clk_peri PERI1_I2C1_PCLK_EN>;
clock-names = "ref", "pclk";
power-domains = <&power_top>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c2: i2c@02022000{
compatible = "snps,designware-i2c";
reg = <0x00 0x02022000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <295>;
clocks = <&clk_peri PERI1_I2C2_IC_CLK_EN>, <&clk_peri PERI1_I2C2_PCLK_EN>;
clock-names = "ref", "pclk";
power-domains = <&power_top>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c3: i2c@08415000{
compatible = "snps,designware-i2c";
reg = <0x00 0x08415000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <296>;
clocks = <&clk_peri PERI2_I2C3_IC_CLK_EN>, <&clk_peri PERI2_I2C3_PCLK_EN>;
clock-names = "ref", "pclk";
power-domains = <&power_peri2>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c4: i2c@08416000{
compatible = "snps,designware-i2c";
reg = <0x00 0x08416000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <297>;
clocks = <&clk_peri PERI2_I2C4_IC_CLK_EN>, <&clk_peri PERI2_I2C4_PCLK_EN>;
clock-names = "ref", "pclk";
power-domains = <&power_peri2>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c5: i2c@08417000{
compatible = "snps,designware-i2c";
reg = <0x00 0x08417000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <298>;
clocks = <&clk_peri PERI2_I2C5_IC_CLK_EN>, <&clk_peri PERI2_I2C5_PCLK_EN>;
clock-names = "ref", "pclk";
power-domains = <&power_peri2>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c6: i2c@08418000{
compatible = "snps,designware-i2c";
reg = <0x00 0x08418000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <299>;
clocks = <&clk_peri PERI2_I2C6_IC_CLK_EN>, <&clk_peri PERI2_I2C6_PCLK_EN>;
clock-names = "ref", "pclk";
power-domains = <&power_peri2>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c7: i2c@08419000{
compatible = "snps,designware-i2c";
reg = <0x00 0x08419000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <300>;
clocks = <&clk_peri PERI2_I2C7_IC_CLK_EN>, <&clk_peri PERI2_I2C7_PCLK_EN>;
clock-names = "ref", "pclk";
power-domains = <&power_peri2>;
#address-cells = <1>;
#size-cells = <0>;
};
aoi2c1: i2c@30891000{
compatible = "snps,designware-i2c";
reg = <0x00 0x30891000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <20>;
clocks = <&aon_110m>;
clock-names = "ref", "pclk";
//power-domains = <&power_peri2>;
#address-cells = <1>;
#size-cells = <0>;
};
vdec: vdec@0006800000 {
compatible = "zhihe,vpu-vc9000d";
address-cells = <2>;
size-cells = <2>;
reg = <0x00 0x06800000 0x0 0xFFFFF
0x00 0x06b40000 0x0 0x10000 >;
interrupt-parent = <&intc>;
interrupts = <229>, <231>;
power-domains = <&power_vdec>;
clocks = <&clk_vp VP_VDEC_CCLK_EN>, <&clk_vp VP_VDEC_ACLK_EN>, <&clk_vp VP_VDEC_PCLK_EN>;
clock-names = "vdec_cclk", "vp_aclk", "vdec_pclk";
operating-points-v2 = <&vdec_opp_table>;
aclk-freq-low = <528000000>;
aclk-freq-high = <880000000>;
cclk-threshold = <600000000>;
//iommus = <&iommu DEVID_DIE0_VDEC>;
//iommu-group = <IOMMU_GROUP_VIDEO>;
};
venc: venc@0006900000 {
compatible = "zhihe,vpu-vc9000e";
address-cells = <2>;
size-cells = <2>;
reg = <0x00 0x06900000 0x0 0xFFFFF
0x00 0x06b50000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <230>, <350>;
power-domains = <&power_venc>;
clocks = <&clk_vp VP_VENC_CCLK_EN>, <&clk_vp VP_VENC_ACLK_EN>, <&clk_vp VP_VENC_PCLK_EN>;
clock-names = "venc_cclk", "vp_aclk", "venc_pclk";
operating-points-v2 = <&venc_opp_table>;
aclk-freq-low = <528000000>;
aclk-freq-high = <880000000>;
cclk-threshold = <528000000>;
//iommus = <&iommu DEVID_DIE0_VENC>;
//iommu-group = <IOMMU_GROUP_VIDEO>;
};
vidmem: vidmem@ffecc08000 {
compatible = "zhihe,vidmem";
//iommus = <&iommu DEVID_VIDEO_MEMORY_DUMMY>;
//iommu-group = <IOMMU_GROUP_VIDEO>;
};
audio_i2s0: audio_i2s0@0002029000 {
compatible = "zhihe,i2s0";
reg = <0x0 0x02029000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <301>;
clocks = <&clk_peri PERI1_I2S0_SRC_CLK_EN>, <&clk_peri PERI1_I2S0_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_top>;
#sound-dai-cells = <1>;
dmas = <&dmac0 3>, <&dmac0 2>;
dma-names = "tx", "rx";
snd-soc-zhihe-a210;
};
audio_i2s1: audio_i2s1@000840a000 {
compatible = "zhihe,i2s1";
reg = <0x0 0x0840a000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <302>;
clocks = <&clk_peri PERI2_I2S1_SRC_CLK_EN>, <&clk_peri PERI2_I2S1_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri2>;
#sound-dai-cells = <1>;
dmas = <&dmac0 38>, <&dmac0 37>;
dma-names = "tx", "rx";
snd-soc-zhihe-a210;
};
audio_i2s2: audio_i2s2@000840b000 {
compatible = "zhihe,i2s2";
reg = <0x0 0x0840b000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <303>;
clocks = <&clk_peri PERI2_I2S2_SRC_CLK_EN>, <&clk_peri PERI2_I2S2_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri2>;
#sound-dai-cells = <1>;
dmas = <&dmac0 36>, <&dmac0 35>;
dma-names = "tx", "rx";
snd-soc-zhihe-a210;
};
audio_i2s_8ch_sd0: audio_i2s_8ch_sd0@000840c000 {
compatible = "zhihe,i2s3-8ch-sd0";
reg = <0x0 0x0840c000 0x0 0x1000>,
<0x0 0x00240000 0x0 0x4>;
interrupt-parent = <&intc>;
interrupts = <304>;
clocks = <&clk_peri PERI2_I2S3_SRC_CLK_EN>, <&clk_peri PERI2_I2S3_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri2>;
multi-channels = <8>;
#sound-dai-cells = <1>;
dmas = <&dmac0 28>, <&dmac0 27>;
dma-names = "tx", "rx";
snd-soc-zhihe-a210;
ports {
#address-cells = <1>;
#size-cells = <0>;
/* i2s transmit to hdmi */
port@0 {
reg = <0>;
hdmi_i2s_tx: endpoint {
remote-endpoint = <&hdmi_i2s_rx>;
};
};
};
};
audio_i2s_8ch_sd1: audio_i2s_8ch_sd1@000840c000 {
compatible = "zhihe,i2s3-8ch-sd1";
reg = <0x0 0x0840c000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <304>;
clocks = <&clk_peri PERI2_I2S3_SRC_CLK_EN>, <&clk_peri PERI2_I2S3_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri2>;
multi-channels = <8>;
#sound-dai-cells = <1>;
dmas = <&dmac0 30>, <&dmac0 29>;
dma-names = "tx", "rx";
snd-soc-zhihe-a210;
};
audio_i2s_8ch_sd2: audio_i2s_8ch_sd2@000840c000 {
compatible = "zhihe,i2s3-8ch-sd2";
reg = <0x0 0x0840c000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <304>;
clocks = <&clk_peri PERI2_I2S3_SRC_CLK_EN>, <&clk_peri PERI2_I2S3_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri2>;
multi-channels = <8>;
#sound-dai-cells = <1>;
dmas = <&dmac0 32>, <&dmac0 31>;
dma-names = "tx", "rx";
snd-soc-zhihe-a210;
};
audio_i2s_8ch_sd3: audio_i2s_8ch_sd3@000840c000 {
compatible = "zhihe,i2s3-8ch-sd3";
reg = <0x0 0x0840c000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <304>;
clocks = <&clk_peri PERI2_I2S3_SRC_CLK_EN>, <&clk_peri PERI2_I2S3_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri2>;
multi-channels = <8>;
#sound-dai-cells = <1>;
dmas = <&dmac0 34>, <&dmac0 33>;
dma-names = "tx", "rx";
snd-soc-zhihe-a210;
};
audio_tdm_slot0: audio_tdm_slot0@200c000 {
compatible = "zhihe,tdm-0";
reg = <0x0 0x200c000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <312>;
clocks = <&clk_peri PERI1_TDM0_SCLK_EN>, <&clk_peri PERI1_TDM0_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
dmas = <&dmac0 4>;
dma-names = "rx";
};
audio_tdm_slot1: audio_tdm_slot1@200c000 {
compatible = "zhihe,tdm-1";
reg = <0x0 0x200c000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <312>;
clocks = <&clk_peri PERI1_TDM0_SCLK_EN>, <&clk_peri PERI1_TDM0_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
dmas = <&dmac0 5>;
dma-names = "rx";
};
audio_tdm_slot2: audio_tdm_slot2@200c000 {
compatible = "zhihe,tdm-2";
reg = <0x0 0x200c000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <312>;
clocks = <&clk_peri PERI1_TDM0_SCLK_EN>, <&clk_peri PERI1_TDM0_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
dmas = <&dmac0 0>;
dma-names = "rx";
};
audio_tdm_slot3: audio_tdm_slot3@200c000 {
compatible = "zhihe,tdm-3";
reg = <0x0 0x200c000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <312>;
clocks = <&clk_peri PERI1_TDM0_SCLK_EN>, <&clk_peri PERI1_TDM0_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
dmas = <&dmac0 1>;
dma-names = "rx";
};
audio_tdm_slot4: audio_tdm_slot4@200c000 {
compatible = "zhihe,tdm-4";
reg = <0x0 0x200c000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <312>;
clocks = <&clk_peri PERI1_TDM0_SCLK_EN>, <&clk_peri PERI1_TDM0_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
dmas = <&dmac0 10>;
dma-names = "rx";
};
audio_tdm_slot5: audio_tdm_slot5@200c000 {
compatible = "zhihe,tdm-5";
reg = <0x0 0x200c000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <312>;
clocks = <&clk_peri PERI1_TDM0_SCLK_EN>, <&clk_peri PERI1_TDM0_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
dmas = <&dmac0 11>;
dma-names = "rx";
};
audio_tdm_slot6: audio_tdm_slot6@200c000 {
compatible = "zhihe,tdm-6";
reg = <0x0 0x200c000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <312>;
clocks = <&clk_peri PERI1_TDM0_SCLK_EN>, <&clk_peri PERI1_TDM0_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
dmas = <&dmac0 12>;
dma-names = "rx";
};
audio_tdm_slot7: audio_tdm_slot7@200c000 {
compatible = "zhihe,tdm-7";
reg = <0x0 0x200c000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <312>;
clocks = <&clk_peri PERI1_TDM0_SCLK_EN>, <&clk_peri PERI1_TDM0_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
dmas = <&dmac0 13>;
dma-names = "rx";
};
usb31_c10phy: phy@8040000 {
compatible = "zhihe,a210-c10phy";
reg = <0x00 0x08040000 0x0 0x3C000>,
<0x00 0x0807C000 0x0 0x2000>,
<0x00 0x0807E000 0x0 0x100>,
<0x00 0x08014000 0x0 0x200>;
reg-names = "phy_ctrl", "tca", "sysreg", "dptx_sys";
resets = <&rst USB_C10PHY_PHY_RST>;
reset-names = "phy-rst";
#phy-cells = <0>;
power-domains = <&power_usb>;
usbdp_phy0_dp: dp-port {
#phy-cells = <0>;
status = "okay";
};
usbdp_phy0_u3: u3-port {
#phy-cells = <0>;
status = "okay";
};
};
usb20phy0: phy@08300000 {
compatible = "zhihe,a210-usb2-phy0";
reg = <0x00 0x8300000 0x0 0x1000>;
reg-names = "usb20-blk-sysreg";
resets = <&rst USB_USB20_BLK_USB0_PHY_PON_RESET>;
reset-names = "phy-rst";
#phy-cells = <0>;
power-domains = <&power_usb>;
zhihe,init-seq = /bits/ 32 <0x000 0x40b67b5b>;
};
usb20phy1: phy@08301000 {
compatible = "zhihe,a210-usb2-phy1";
reg = <0x00 0x8301000 0x0 0x1000>;
reg-names = "usb20-blk-sysreg";
resets = <&rst USB_USB20_BLK_USB1_PHY_PON_RESET>;
reset-names = "phy-rst";
#phy-cells = <0>;
power-domains = <&power_usb>;
zhihe,init-seq = /bits/ 32 <0x000 0x40b67b5b>;
};
usb31_syscon: syscon@8000000 {
compatible = "syscon";
reg = <0x00 0x08000000 0x0 0x1000>;
};
usb20phy2: usb2-phy {
compatible = "zhihe,a210-usb2-phy2";
syscon = <&usb31_syscon>;
resets = <&rst USB_USB31_PHY_RST>;
reset-names = "phy-rst";
#phy-cells = <0>;
zhihe,init-seq = /bits/ 32 <0x0a0 0x1000>;
};
usb31: usb3@8001000 {
compatible = "zhihe,usb31";
syscon = <&usb31_syscon>;
clocks = <&clk_usb USB31_REF_CLK_EN>,
<&clk_usb USB31_SLV_AFENCE_ACLK_EN>,
<&clk_usb USB_SS_PERI2_CFG_ACLK_EN>;
clock-names = "ref-clk", "slv-aclk", "cfg-aclk";
resets = <&rst USB_USB31_SLV_AFENCE_ARST>;
reset-names = "usb31-arst";
#address-cells = <2>;
#size-cells = <2>;
ranges;
usb3: dwc3@8100000 {
compatible = "snps,dwc3";
reg = <0x00 0x8100000 0x0 0x100000>;
interrupt-parent = <&intc>;
interrupts = <183>;
clocks = <&clk_usb USB31_PCLK_EN>,
<&clk_usb USB31_BUS_CLK_EN>,
<&clk_usb USB31_SUSPEND_CLK_EN>;
clock-names = "pclk", "bus_clk", "suspend_clk";
reg-shift = <2>;
reg-io-width = <4>;
dr_mode = "host";
power-domains = <&power_usb>;
phys = <&usb20phy2>, <&usbdp_phy0_u3>;
phy-names = "usb2-phy", "usb3-phy";
//iommus = <&iommu DEVID_DIE0_USB3_0>;
snps,usb3_lpm_capable;
snps,usb_sofitpsync;
};
};
usb2_0: usb2@8200000 {
compatible = "zhihe,a210-usb", "snps,dwc2";
reg = <0x00 0x8200000 0x0 0x40000>;
interrupt-parent = <&intc>;
interrupts = <181>;
clocks = <&clk_usb USB20_BUS_CLK>;
clock-names = "otg";
resets = <&rst USB_USB20_BLK_USB2_WRAP0_HRST>;
reset-names = "dwc2";
phys = <&usb20phy0>;
phy-names = "usb2-phy";
dr_mode = "host";
maximum-speed = "high-speed";
reg-shift = <2>;
reg-io-width = <4>;
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <275>;
g-tx-fifo-size = <256 128 128 64 64 32>;
power-domains = <&power_usb>;
// iommus = <&iommu DEVID_DIE0_USB2_0>;
snps,need-phy-for-wake;
};
usb2_1: usb2@8240000 {
compatible = "zhihe,a210-usb", "snps,dwc2";
reg = <0x00 0x8240000 0x0 0x40000>;
interrupt-parent = <&intc>;
interrupts = <182>;
clocks = <&clk_usb USB20_BUS_CLK>;
clock-names = "otg";
resets = <&rst USB_USB20_BLK_USB2_WRAP1_HRST>;
reset-names = "dwc2";
phys = <&usb20phy1>;
phy-names = "usb2-phy";
dr_mode = "host";
maximum-speed = "high-speed";
reg-shift = <2>;
reg-io-width = <4>;
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <275>;
g-tx-fifo-size = <256 128 128 64 64 32>;
power-domains = <&power_usb>;
// iommus = <&iommu DEVID_DIE0_USB2_1>;
snps,need-phy-for-wake;
};
audio_pdm0: audio_pdm0@0002008000 {
compatible = "zhihe,pdm";
reg = <0x0 0x02008000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <339>;
clocks = <&clk_peri PERI1_PDM0_MCLK_EN>, <&clk_peri PERI1_PDM0_PCLK_EN>;
clock-names = "mclk", "pclk";
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
zhihe,mode = "pdm-master";
zhihe,sel = "audio_pdm0";
dmas = <&dmac0 6>;
dma-names = "rx";
};
audio_pdm1: audio_pdm1@0002008000 {
compatible = "zhihe,pdm";
reg = <0x0 0x02008000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <339>;
clocks = <&clk_peri PERI1_PDM0_MCLK_EN>, <&clk_peri PERI1_PDM0_PCLK_EN>;
clock-names = "mclk", "pclk";
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
zhihe,mode = "pdm-master";
zhihe,sel = "audio_pdm1";
dmas = <&dmac0 7>;
dma-names = "rx";
};
audio_pdm2: audio_pdm2@0002008000 {
compatible = "zhihe,pdm";
reg = <0x0 0x02008000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <339>;
clocks = <&clk_peri PERI1_PDM0_MCLK_EN>, <&clk_peri PERI1_PDM0_PCLK_EN>;
clock-names = "mclk", "pclk";
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
zhihe,mode = "pdm-master";
zhihe,sel = "audio_pdm2";
dmas = <&dmac0 12>;
dma-names = "rx";
};
audio_pdm3: audio_pdm3@0002008000 {
compatible = "zhihe,pdm";
reg = <0x0 0x02008000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <339>;
clocks = <&clk_peri PERI1_PDM0_MCLK_EN>, <&clk_peri PERI1_PDM0_PCLK_EN>;
clock-names = "mclk", "pclk";
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
zhihe,mode = "pdm-master";
zhihe,sel = "audio_pdm3";
dmas = <&dmac0 13>;
dma-names = "rx";
};
audio_pdm4: audio_pdm4@0002008000 {
compatible = "zhihe,pdm";
reg = <0x0 0x02008000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <339>;
clocks = <&clk_peri PERI1_PDM0_MCLK_EN>, <&clk_peri PERI1_PDM0_PCLK_EN>;
clock-names = "mclk", "pclk";
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
zhihe,mode = "pdm-master";
zhihe,sel = "audio_pdm4";
dmas = <&dmac0 10>;
dma-names = "rx";
};
audio_pdm5: audio_pdm5@0002008000 {
compatible = "zhihe,pdm";
reg = <0x0 0x02008000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <339>;
clocks = <&clk_peri PERI1_PDM0_MCLK_EN>, <&clk_peri PERI1_PDM0_PCLK_EN>;
clock-names = "mclk", "pclk";
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
zhihe,mode = "pdm-master";
zhihe,sel = "audio_pdm5";
dmas = <&dmac0 11>;
dma-names = "rx";
};
audio_pdm6: audio_pdm6@0002008000 {
compatible = "zhihe,pdm";
reg = <0x0 0x02008000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <339>;
clocks = <&clk_peri PERI1_PDM0_MCLK_EN>, <&clk_peri PERI1_PDM0_PCLK_EN>;
clock-names = "mclk", "pclk";
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
zhihe,mode = "pdm-master";
zhihe,sel = "audio_pdm6";
dmas = <&dmac0 0>;
dma-names = "rx";
};
audio_pdm7: audio_pdm7@0002008000 {
compatible = "zhihe,pdm";
reg = <0x0 0x02008000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <339>;
clocks = <&clk_peri PERI1_PDM0_MCLK_EN>, <&clk_peri PERI1_PDM0_PCLK_EN>;
clock-names = "mclk", "pclk";
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
zhihe,mode = "pdm-master";
zhihe,sel = "audio_pdm7";
dmas = <&dmac0 1>;
dma-names = "rx";
};
e16phy: e16phy@a1800000 {
compatible = "zhihe,a210-e16phy";
reg = <0x00 0xa180000 0x0 0x001000>;
#phy-cells = <0>;
clocks = <&clk_pcie E16PHY_PCLK_EN>;
clock-names = "e16phy_clk";
resets = <&rst PCIE_E16PHY_APBS_PRST>,<&rst PCIE_E16PHY_PHY_RST>;
reset-names = "apb", "phy";
/* PCIE_DMx4 */
init-seq-pcie_dmx4 = /bits/ 32 <0x000 0x00110000>,
<0x004 0x00000000>,
<0x008 0x00000000>,
<0x108 0x00000011>,
<0x048 0x00010001>;
/* PCIE_DMx2,PCIE_RPx1 */
init-seq-pcie_dmx2_rpx1 = /bits/ 32 <0x000 0x00110100>,
<0x004 0x00000000>,
<0x008 0x00000000>,
<0x108 0x00000011>,
<0x048 0x00010001>;
/* PCIE_DMx2,SATA_x2 */
init-seq-pcie_dmx2_satax2 = /bits/ 32 <0x000 0x00110001>,
<0x004 0x00001100>,
<0x008 0x00002200>,
<0x108 0x00000011>,
<0x048 0x00010001>;
/* PCIE_DMx1,PCIE_RPx1,SATA_x2 */
init-seq-pcie_dmx1_rpx1_satax2 = /bits/ 32 <0x000 0x00110101>,
<0x004 0x00001100>,
<0x008 0x00002200>,
<0x108 0x00000011>,
<0x048 0x00010001>;
init-seq-select = "pcie_dmx4";
};
dm3x4: pcie@b000000 {
compatible = "zhihe,a210-pcie";
reg = <0x00 0x0b000000 0x0 0x800000>,
<0x18 0x00000000 0x0 0x200000>,
<0x00 0x0A004000 0x0 0x001000>;
reg-names = "dbi","config","pcie_sysreg";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0x18 0x00200000 0x18 0x00200000 0x0 0x600000>,
<0x82000000 0x00 0x40100000 0x00 0x40100000 0x0 0x800000>,
<0xc3000000 0x18 0x00300000 0x18 0x00300000 0x0 0x800000>;
interrupts = <139>,<140>,<141>,<142>,<143>;
interrupt-names = "msi","inta","intb","intc","intd";
interrupt-parent = <&intc>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &intc 140>,
<0x0 0x0 0x0 0x2 &intc 141>,
<0x0 0x0 0x0 0x3 &intc 142>,
<0x0 0x0 0x0 0x4 &intc 143>;
clocks = <&clk_pcie PCIE_DM_GEN3X4_AUX_CLK_EN>,
<&clk_pcie PCIE_DM_GEN3X4_SLV_ACLK_EN>,
<&clk_pcie PCIE_DM_GEN3X4_MST_ACLK_EN>,
<&clk_pcie PCIE_DM_GEN3X4_PCLK_EN>;
clock-names = "gen3x4_aux_clk","gen3x4_slv_clk","gen3x4_mst_clk","gen3x4_pclk";
power-domains = <&power_pcie0>;
//iommus = <&iommu DEVID_DIE0_PCIE_0>;
phys = <&e16phy>;
phy-names = "pcie-phy";
num-lanes = <4>;
max-link-speed = <3>;
};
rp3x1: pcie@b800000 {
compatible = "zhihe,a210-pcie";
reg = <0x00 0x0b800000 0x0 0x800000>,
<0x1E 0x00000000 0x0 0x20000>,
<0x00 0x0A005000 0x0 0x001000>;
reg-names = "dbi","config","pcie_sysreg";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0x1E 0x00200000 0x1E 0x00200000 0x0 0x600000>,
<0x82000000 0x00 0x50100000 0x00 0x50100000 0x0 0x800000>,
<0xc3000000 0x1E 0x00300000 0x1E 0x00300000 0x0 0x800000>;
interrupts = <158>,<159>,<160>,<161>,<162>;
interrupt-names = "msi","inta","intb","intc","intd";
interrupt-parent = <&intc>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &intc 159>,
<0x0 0x0 0x0 0x2 &intc 160>,
<0x0 0x0 0x0 0x3 &intc 161>,
<0x0 0x0 0x0 0x4 &intc 162>;
clocks = <&clk_pcie PCIE_RP_GEN3X1_AUX_CLK_EN>,
<&clk_pcie PCIE_RP_GEN3X1_SLV_ACLK_EN>,
<&clk_pcie PCIE_RP_GEN3X1_MST_ACLK_EN>,
<&clk_pcie PCIE_RP_GEN3X1_PCLK_EN>;
clock-names = "gen3x1_aux_clk","gen3x1_slv_clk","gen3x1_mst_clk","gen3x1_pclk";
power-domains = <&power_pcie1>;
//iommus = <&iommu DEVID_DIE0_PCIE_1>;
phys = <&e16phy>;
phy-names = "pcie-phy";
num-lanes = <1>;
max-link-speed = <3>;
};
mbox_920: mbox@0000310000 {
compatible = "zhihe,mailbox";
reg = <0x00 0x00321000 0x0 0x1000>,
<0x00 0x00320000 0x0 0x1000>,
<0x00 0x00311000 0x0 0x1000>;
reg-names = "interrupt_addr",
"local_addr0",
"remote_icu0";
resets = <&rst PERI0_MBOX0_PRST>, <&rst PERI0_MBOX1_PRST>;
interrupt-parent = <&intc>;
interrupts = <336 IRQ_TYPE_LEVEL_HIGH>;
icu_cpu_id = <0>;
#mbox-cells = <2>;
version = <1>;
};
aon: aon_subsys@308f8000 {
compatible = "zhihe,aon";
reg = <0x00 0x308f8000 0x0 0x10000>,
<0x00 0x30842018 0x0 0x4>,
<0x00 0x30846144 0x0 0x4>;
reg-names = "aon_base_addr",
"aon_reset_reg",
"aon_sync_reg";
firmware-name = "a210-aon.bin";
mboxes = <&mbox_920 1 0>; //parent / channel / type
mbox-names = "aon0";
#mbox-cells = <2>;
version = <1>;
};
sata: sata@000a200000 {
compatible = "snps,dwc-ahci";
reg = <0x0 0xa200000 0x0 0x100000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <170>;
clocks = <&clk_pcie SATA_PMALIVE_CLK_EN>,
<&clk_pcie SATA_RXOOB0_CLK_EN>,
<&clk_pcie SATA_RXOOB1_CLK_EN>,
<&clk_pcie SATA_GEN3X2_ACLK_EN>;
clock-names = "pmalive", "rxoob0", "rxoob1", "aclk";
resets = <&rst PCIE_SATA_ARESET>,
<&rst PCIE_SATA_RST_PMALIVE>, <&rst PCIE_SATA_RST_ASIC0>, <&rst PCIE_SATA_RST_ASIC1>,
<&rst PCIE_SATA_RST_RXOOB0>, <&rst PCIE_SATA_RST_RXOOB1>;
power-domains = <&power_sata>;
//iommus = <&iommu DEVID_DIE0_SATA_0>;
ports-implemented = <3>;
sata0: sata-port@0 {
reg = <0>;
hba-port-cap = <HBA_PORT_FBSCP>;
snps,tx-ts-max = <16>;
snps,rx-ts-max = <16>;
phys = <&e16phy>;
phy-names = "sata-phy";
};
sata1: sata-port@1 {
reg = <1>;
hba-port-cap = <HBA_PORT_FBSCP>;
snps,tx-ts-max = <16>;
snps,rx-ts-max = <16>;
phys = <&e16phy>;
phy-names = "sata-phy";
};
};
iommu: iommu@0 {
compatible = "zhihe,iommu";
reg = <0x0 0x06372000 0x0 0x400>,
<0x0 0x06B12000 0x0 0x400>,
<0x0 0x07102000 0x0 0x400>,
<0x0 0x06712000 0x0 0x400>,
<0x0 0x02032000 0x0 0x400>,
<0x0 0x0a012000 0x0 0x400>,
<0x0 0x08022000 0x0 0x400>;
reg-names = "vi", "vp", "npu", "vo", "peri1", "pcie", "usb";
clocks = <&clk SW_IOMMU_PTW_330_ACLK_EN>, <&clk_vi VI_PTW_ACLK_EN>,
<&clk_vi VI_DFMU_ACLK_EN>, <&clk_vi VI_DFMU_PCLK_EN>,
<&clk_vp VP_PTW_ACLK_EN>, <&clk_vp VP_DFMU_ACLK_EN>,
<&clk_vp VP_DFMU_PCLK_EN>, <&clk_vo VO_PTW_ACLK_EN>,
<&clk_vo VO_DFMU_PCLK_EN>, <&clk_vo VO_DFMU_ACLK_EN>,
<&clk_peri PERI1_DFMU_PTW_ACLK_EN>, <&clk_peri PERI1_DFMU_PCLK_EN>,
<&clk_peri PERI1_DFMU_ACLK_EN>;
interrupt-parent = <&intc>;
interrupts = <204>, <235>, <66>, <223>, <344>, <174>, <187>;
power-domains = <&power_vi_isp>, <&power_venc>, <&power_vdec>, <&power_npu_ip>,
<&power_vo>, <&power_pcie0>, <&power_pcie1>, <&power_usb>,
<&power_top>;
#iommu-cells = <1>;
};
dfmu_mt_vi: mt@0x06370000 {
compatible = "zhihe,memtester";
reg = <0x0 0x06370000 0x0 0x400>;
iommus = <&iommu DEVID_DIE0_VI_DFMU>;
};
dfmu_mt_vp: mt@0x06B10000 {
compatible = "zhihe,memtester";
reg = <0x0 0x06B10000 0x0 0x400>;
iommus = <&iommu DEVID_DIE0_VP_DFMU>;
};
dfmu_mt_npu: mt@0x07100000 {
compatible = "zhihe,memtester";
reg = <0x0 0x07100000 0x0 0x400>;
iommus = <&iommu DEVID_DIE0_NPU_DFMU>;
};
dfmu_mt_vo: mt@0x06710000 {
compatible = "zhihe,memtester";
reg = <0x0 0x06710000 0x0 0x400>;
iommus = <&iommu DEVID_DIE0_VO_DFMU>;
};
dfmu_mt_peri1: mt@0x02030000 {
compatible = "zhihe,memtester";
reg = <0x0 0x02030000 0x0 0x400>;
iommus = <&iommu DEVID_DIE0_PERI1_DFMU>;
};
dfmu_mt_pcie: mt@0x0a010000 {
compatible = "zhihe,memtester";
reg = <0x0 0x0a010000 0x0 0x400>;
iommus = <&iommu DEVID_DIE0_PCIE_DFMU>;
};
dfmu_mt_usb: mt@0x08020000 {
compatible = "zhihe,memtester";
reg = <0x0 0x08020000 0x0 0x400>;
iommus = <&iommu DEVID_DIE0_USB_DFMU>;
};
npu0: vipcore@0x07000000 {
compatible = "verisilicon,vipcore0";
reg = <0x00 0x7000000 0x00 0x10000>;
interrupt-parent = <&intc>;
interrupts = <71>;
clocks = <&clk_npu SW_NPU_IP_ACLK_EN>, <&clk_npu SW_NPU_IP_CCLK_EN>,
<&clk_npu SW_NPU_IP_HCLK_EN>;
clock-names = "npu_aclk", "npu_cclk", "top_cfg_aclk";
power-domains = <&power_npu_ip>;
};
g2d: gc620@0006a00000 {
compatible = "xuantie,th1520-gc620", "thead,c910-gc620";
reg = <0x00 0x06a00000 0x0 0x40000>;
interrupt-parent = <&intc>;
interrupts = <240>;
interrupt-names = "irq_2d";
clocks = <&clk_vp VP_G2D_CCLK_EN>,
<&clk_vp VP_G2D_ACLK_EN>,
<&clk_vp VP_G2D_PCLK_EN>;
clock-names = "cclk", "aclk", "pclk";
operating-points-v2 = <&g2d_opp_table>;
power-domains = <&power_vp_wrapper>;
//iommus = <&iommu DEVID_DIE0_G2D>;
//iommu-group = <IOMMU_GROUP_VIDEO>;
};
eip_28: eip-28@0027500000 {
compatible = "xlnx,sunrise-fpga-1.0", "safexcel-eip-28";
reg = <0x00 0x27500000 0x0 0x40000>;
interrupt-parent = <&intc>;
interrupts = <243>,<246>,<249>,<251>;
clocks = <&clk_peri TEE_EIP120SI_CLKEN>,
<&clk_peri TEE_EIP120SII_CLKEN>,
<&clk_peri TEE_EIP120SIII_CLKEN>,
<&clk_peri TEE_EIP150B_CLKEN>;
clock-names = "120si_clk","120sii_clk","120siii_clk","hclk";
//iommus = <&iommu DEVID_DIE0_TEE_EIP120SI>,
// <&iommu DEVID_DIE0_TEE_EIP120SII>,
// <&iommu DEVID_DIE0_TEE_EIP120SIII>;
};
mipi0_csi0: csi@0006300000 {
compatible = "zhihe,bm-csi";
//default 2lane mode: host addr; current phy ctrl addr(csi1->aphy, csi0 bphy); mipi_ctrl addr
reg = < 0x00 0x06300000 0x0 0x10000
0x00 0x063a0024 0x0 0x4
0x00 0x063a0028 0x0 0x4>;
interrupt-parent = <&intc>;
interrupts = <192>;
clocks = <&clk_vi VI_MIPI0_CSI0_PIXCLK_EN>,
<&clk_vi VI_MIPI0B_CFGCLK_EN>,
<&clk_vi VI_MIPI0CSI0_PCLK_EN>,
<&clk_vi VI_MIPI0CSI0_FPCLK_EN>;
power-domains = <&power_vi_isp>;
clock-names = "pixclk", "cfg_clk", "pclk", "fpclk";
phy_name = "CSI_BPHY";
};
mipi0_csi1: csi@0006310000 {
compatible = "zhihe,bm-csi";
//default 2lane mode: host addr; current phy ctrl addr(csi1->aphy, csi0 bphy); mipi_ctrl addr
reg = < 0x00 0x06310000 0x0 0x10000
0x00 0x063a0020 0x0 0x4
0x00 0x063a0028 0x0 0x4>;
interrupt-parent = <&intc>;
interrupts = <193>;
clocks = <&clk_vi VI_MIPI0_CSI1_PIXCLK_EN>,
<&clk_vi VI_MIPI0A_CFGCLK_EN>,
<&clk_vi VI_MIPI0CSI1_PCLK_EN>,
<&clk_vi VI_MIPI0CSI1_FPCLK_EN>;
power-domains = <&power_vi_isp>;
clock-names = "pixclk", "cfg_clk", "pclk", "fpclk";
phy_name = "CSI_APHY";
};
mipi1_csi0: csi@0006320000 {
compatible = "zhihe,bm-csi";
//default 2lane mode: host addr; current phy ctrl addr(csi1->aphy, csi0 bphy); mipi_ctrl addr
reg = < 0x00 0x06320000 0x0 0x10000
0x00 0x063a0034 0x0 0x4
0x00 0x063a0038 0x0 0x4>;
interrupt-parent = <&intc>;
interrupts = <194>;
clocks = <&clk_vi VI_MIPI1_CSI0_PIXCLK_EN>,
<&clk_vi VI_MIPI1B_CFGCLK_EN>,
<&clk_vi VI_MIPI1CSI0_PCLK_EN>,
<&clk_vi VI_MIPI1CSI0_FPCLK_EN>;
clock-names = "pixclk", "cfg_clk", "pclk", "fpclk";
power-domains = <&power_vi_isp>;
phy_name = "CSI_BPHY";
};
mipi1_csi1: csi@0006330000 {
//default 2lane mode: host addr; current phy ctrl addr(csi1->aphy, csi0 bphy); mipi_ctrl addr
compatible = "zhihe,bm-csi";
reg = < 0x00 0x06330000 0x0 0x10000
0x00 0x063a0030 0x0 0x4
0x00 0x063a0038 0x0 0x4>;
interrupt-parent = <&intc>;
interrupts = <195>;
clocks = <&clk_vi VI_MIPI1_CSI1_PIXCLK_EN>,
<&clk_vi VI_MIPI1A_CFGCLK_EN>,
<&clk_vi VI_MIPI1CSI1_PCLK_EN>,
<&clk_vi VI_MIPI1CSI1_FPCLK_EN>;
clock-names = "pixclk", "cfg_clk", "pclk", "fpclk";
power-domains = <&power_vi_isp>;
phy_name = "CSI_APHY";
};
vipre: vipre@0006340000 {
compatible = "zhihe,vipre";
reg = <0x00 0x06340000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <200>;
clocks = <&clk_vi VI_ARB_ACLK_EN>,
<&clk_vi VI_ARB_PCLK_EN>,
<&clk_vi VI_PTW_ACLK_EN>,
<&clk_vi VI_DFMU_ACLK_EN>,
<&clk_vi VI_DFMU_PCLK_EN>,
<&clk_vi VI_VIPRE_ACLK_EN>,
<&clk_vi VI_VIPRE_SCLK_EN>,
<&clk_vi VI_VIPRE_I0_PIXCLK_EN>,
<&clk_vi VI_VIPRE_I1_PIXCLK_EN>,
<&clk_vi VI_VIPRE_PCLK_EN>;
clock-names = "vi_arb_aclk", "vi_arb_pclk", "vi_ptw_aclk", "vi_dfmu_aclk", "vi_dfmu_pclk",
"aclk", "sclk", "i0pixclk", "i1pixclk", "pclk";
power-domains = <&power_vi_isp>;
};
dw200_vb: dw200_vb@95000000 {
compatible = "zhihe,dw200_vb";
address-cells = <2>;
size-cells = <2>;
reg = <0x00 0x95000000 0x0 0x8000000>;
};
isp8000: isp8000@06000000 {
compatible = "zhihe,isp8000";
reg = <0x00 0x06000000 0x0 0x100000
0x00 0x063A0400 0x0 0x4>;
interrupt-parent = <&intc>;
interrupts = <196>,<198>,<197>;
clocks = <&clk_vi VI_ARB_ACLK_EN>,
<&clk_vi VI_ARB_PCLK_EN>,
<&clk_vi VI_PTW_ACLK_EN>,
<&clk_vi VI_DFMU_ACLK_EN>,
<&clk_vi VI_DFMU_PCLK_EN>,
<&clk_vi VI_ISPOUT_CLK_EN>,
<&clk_vi VI_ISP_CLK_EN>,
<&clk_vi VI_FENCE_ACLK_EN>,
<&clk_vi VI_X2H1_CLK_EN>,
<&clk_vi VI_X2H0_CLK_EN>,
<&clk_vi VI_MISC_CTRL_BUS_CLK_GT_DISABLE>,
<&clk_vi VI_MISC_CTRL_ISP_MCM_CLK_EN>,
<&clk_vi VI_MISC_CTRL_ISP_FLEXA_CLK_EN>,
<&clk_vi VI_MISC_CTRL_ISP_CORE_CLK_EN>,
<&clk_vi VI_MISC_CTRL_ISP_SCLK_CLK0_EN>,
<&clk_vi VI_MISC_CTRL_ISP_SCLK_CLK1_EN>,
<&clk_vi VI_MISC_CTRL_ISP_SCLK_CLK2_EN>,
<&clk_vi VI_MISC_CTRL_ISP_SCLK_CLK3_EN>,
<&clk_vi VI_MISC_CTRL_ISP_ACLK_CLK_EN>,
<&clk_vi VI_MISC_CTRL_H1CLK_CLK_EN>,
<&clk_vi VI_MISC_CTRL_H0CLK_CLK_EN>;
clock-names = "vi_arb_aclk", "vi_arb_pclk", "vi_ptw_aclk", "vi_dfmu_aclk", "vi_dfmu_pclk",
"isp_out_clk", "isp_clk", "fence_aclk", "x2h1_clk", "x2h0_clk", "bus_clk_gt_disabled",
"isp_mcm_clk", "isp_flexa_clk", "isp_core_clk", "isp_sclk_slk0", "isp_sclk_slk1",
"isp_sclk_slk2", "isp_sclk_slk3","isp_aclk_clk", "isp_h1clk_clk", "isp_h0clk_clk";
power-domains = <&power_vi_isp>;
};
dw200_dw: dw200_dw@06200000 {
compatible = "zhihe,dw200_v30";
reg = <0x00 0x06200000 0x0 0x100000
0x00 0x063A0400 0x0 0x4
0x00 0x06350000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <209>,<211>,<210>,<199>;
clocks = <&clk_vi VI_ARB_ACLK_EN>,
<&clk_vi VI_ARB_PCLK_EN>,
<&clk_vi VI_PTW_ACLK_EN>,
<&clk_vi VI_DFMU_ACLK_EN>,
<&clk_vi VI_DFMU_PCLK_EN>,
<&clk_vi VI_DW_SCLK_EN>,
<&clk_vi VI_VSE_CLK_EN>,
<&clk_vi VI_DWE_CLK_EN>,
<&clk_vi VI_DW200_ACLK_EN>,
<&clk_vi VI_DW200_HCLK_EN>,
<&clk_vi VI_VSEOUT_CLK_EN>,
<&clk_vi VI_DECOUT_CLK_EN>,
<&clk_vi VI_X2H2_CLK_EN>;
clock-names = "vi_arb_aclk", "vi_arb_pclk", "vi_ptw_aclk", "vi_dfmu_aclk", "vi_dfmu_pclk",
"dw_sclk", "vse_clk", "dwe_clk", "dw200_aclk", "dw200_hclk", "vseout_clk", "decout_clk", "x2h2_clk";
power-domains = <&power_vi_isp>;
};
bmu0: ddr-bmu@0004850000 {
compatible = "zhihe,a210-ddr-bmu";
reg = <0x00 0x04850000 0x0 0x10000>,
<0x00 0x05850000 0x0 0x10000>;
zhihe,bm-num = <2>;
zhihe,bm-name ="bmu_ddr";
interrupt-parent = <&intc>;
interrupts = <96>,<101>,<115>,<120>;
};
bmu1: gpu-bmu@0006d14000 {
compatible = "zhihe,a210-gpu-bmu";
reg = <0x00 0x06d14000 0x0 0x400>;
zhihe,bm-num = <1>;
zhihe,bm-name ="bmu_gpu";
interrupt-parent = <&intc>;
interrupts = <54>;
power-domains = <&power_gpu>;
};
bmu2: npu-bmu@0007104000 {
compatible = "zhihe,a210-npu-bmu";
reg = <0x00 0x07104000 0x0 0x400>;
zhihe,bm-num = <1>;
zhihe,bm-name ="bmu_npu";
interrupt-parent = <&intc>;
interrupts = <65>;
power-domains = <&power_npu_ip>;
};
bmu3: pcie-bmu@000a014000 {
compatible = "zhihe,a210-pcie-bmu";
reg = <0x00 0x0a014000 0x0 0x400>;
zhihe,bm-num = <1>;
zhihe,bm-name ="bmu_pcie";
interrupt-parent = <&intc>;
interrupts = <173>;
};
bmu4: usb-bmu@0008024000 {
compatible = "zhihe,a210-usb-bmu";
reg = <0x00 0x08024000 0x0 0x400>;
zhihe,bm-num = <1>;
zhihe,bm-name ="bmu_usb";
interrupt-parent = <&intc>;
interrupts = <186>;
};
bmu5: vo-bmu@0006714000 {
compatible = "zhihe,a210-vo-bmu";
reg = <0x00 0x06714000 0x0 0x400>;
zhihe,bm-num = <1>;
zhihe,bm-name ="bmu_vo";
interrupt-parent = <&intc>;
interrupts = <222>;
power-domains = <&power_vo>;
};
bmu6: vi-bmu@0006374000 {
compatible = "zhihe,a210-vi-bmu";
reg = <0x00 0x06374000 0x0 0x400>;
zhihe,bm-num = <1>;
zhihe,bm-name ="bmu_vi";
interrupt-parent = <&intc>;
interrupts = <203>;
power-domains = <&power_vi_isp>;
};
bmu7: vp-bmu@0006b14000 {
compatible = "zhihe,a210-vp-bmu";
reg = <0x00 0x06b14000 0x0 0x400>;
zhihe,bm-num = <1>;
zhihe,bm-name ="bmu_vp";
interrupt-parent = <&intc>;
interrupts = <234>;
power-domains = <&power_venc>;
};
bmu8: peri-bmu@0002034000 {
compatible = "zhihe,a210-peri-bmu";
reg = <0x00 0x02034000 0x0 0x400>;
zhihe,bm-num = <1>;
zhihe,bm-name ="bmu_peri";
interrupt-parent = <&intc>;
interrupts = <343>;
};
bmu9: d2d-bmu@0009034000 {
compatible = "zhihe,a210-d2d-bmu";
reg = <0x00 0x09034000 0x0 0x400>;
zhihe,bm-num = <1>;
zhihe,bm-name ="bmu_d2d";
interrupt-parent = <&intc>;
interrupts = <124>;
};
};
};
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