kernel-zhihe-a210/drivers/phy/synopsys/phy-dw-e16.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Rockchip PCIE3.0 phy driver
 *
 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy/pcie.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>

/* Register for A210 */
#define E16PHY_GLB_CTRL_REG             0x00000000
#define E16PHY_SRC_SEL_REG              0x00000004
#define E16PHY_PROTLCOL_REG             0x00000008
#define E16PHY_RES_RTURN_REG            0x00000048

/* Register for RK3568 */
#define GRF_PCIE30PHY_CON1			0x4
#define GRF_PCIE30PHY_CON6			0x18
#define GRF_PCIE30PHY_CON9			0x24
#define GRF_PCIE30PHY_DA_OCM			(BIT(15) | BIT(31))
#define GRF_PCIE30PHY_STATUS0			0x80
#define GRF_PCIE30PHY_WR_EN			(0xf << 16)
#define SRAM_INIT_DONE(reg)			(reg & BIT(14))

#define RK3568_BIFURCATION_LANE_0_1		BIT(0)

/* Register for RK3588 */
#define PHP_GRF_PCIESEL_CON			0x100
#define RK3588_PCIE3PHY_GRF_CMN_CON0		0x0
#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1	0x904
#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1	0xa04
#define RK3588_SRAM_INIT_DONE(reg)		(reg & BIT(0))

#define RK3588_BIFURCATION_LANE_0_1		BIT(0)
#define RK3588_BIFURCATION_LANE_2_3		BIT(1)
#define RK3588_LANE_AGGREGATION		BIT(2)

struct zhihe_p3phy_ops;

struct zhihe_p3phy_priv {
	const struct zhihe_p3phy_ops *ops;
	void __iomem *mmio;
	/* mode: RC, EP */
	int mode;
	/* pcie30_phymode: Aggregation, Bifurcation */
	int pcie30_phymode;
	struct reset_control *apb_rst;
	struct reset_control *phy_rst;
	struct phy *phy;
	struct clk_bulk_data *clks;
	int num_clks;
	int num_lanes;
	u32 lanes[4];
};

struct zhihe_p3phy_ops {
	int (*phy_init)(struct zhihe_p3phy_priv *priv);
};

static int zhihe_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
{
	struct zhihe_p3phy_priv *priv = phy_get_drvdata(phy);

	/* Actually We don't care EP/RC mode, but just record it */
	switch (mode) {
	case PHY_MODE_SATA:
		priv->mode = PHY_MODE_SATA;
		break;
	default:
		dev_err(&phy->dev, "%s, invalid mode, submode %d\n", __func__, submode);
		return -EINVAL;
	}

	return 0;
}

static int zhihe_p3phy_a210_init(struct zhihe_p3phy_priv *priv)
{
	int ret = 0;

	// dev_info(&priv->phy->dev, "%s mmio=%px\n", __func__, priv->mmio);
	writel(0x00110101, priv->mmio + 0);
	writel(0x00001100, priv->mmio + 4);
	writel(0x00002200, priv->mmio + 8);
	writel(0x00000011, priv->mmio + 108);
	writel(0x00010001, priv->mmio + 48);
	// dma_mb();

	return ret;
}

static const struct zhihe_p3phy_ops a210_ops = {
	.phy_init = zhihe_p3phy_a210_init,
};

static int rochchip_p3phy_init(struct phy *phy)
{
	struct zhihe_p3phy_priv *priv = phy_get_drvdata(phy);
	int ret;

	ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
	if (ret) {
		dev_err(&priv->phy->dev, "failed to enable PCIe bulk clks %d\n", ret);
		return ret;
	}
	udelay(10);
	reset_control_assert(priv->apb_rst);
	reset_control_assert(priv->phy_rst);
	if (priv->ops->phy_init) {
		ret = priv->ops->phy_init(priv);
		if (ret) {
			clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
			reset_control_assert(priv->apb_rst);
			return ret;
		}
	}
	// reset_control_deassert(priv->apb_rst);
	udelay(1);
	reset_control_deassert(priv->phy_rst);

	return ret;
}

static int rochchip_p3phy_exit(struct phy *phy)
{
	struct zhihe_p3phy_priv *priv = phy_get_drvdata(phy);

	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
	reset_control_assert(priv->phy_rst);
	reset_control_assert(priv->apb_rst);

	return 0;
}

static const struct phy_ops rochchip_p3phy_ops = {
	.init = rochchip_p3phy_init,
	.exit = rochchip_p3phy_exit,
	.set_mode = zhihe_p3phy_set_mode,
	.owner = THIS_MODULE,
};

static int zhihe_p3phy_probe(struct platform_device *pdev)
{
	struct phy_provider *phy_provider;
	struct device *dev = &pdev->dev;
	struct zhihe_p3phy_priv *priv;
	struct resource *res;
	int ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
	if (IS_ERR(priv->mmio)) {
		ret = PTR_ERR(priv->mmio);
		return ret;
	}
	dev_info(&pdev->dev,
			"E16PHY mapped: phys=%pa, virt=%px, size=%zu\n",
			&res->start, priv->mmio, (size_t)resource_size(res));

	priv->ops = of_device_get_match_data(&pdev->dev);
	if (!priv->ops) {
		dev_err(dev, "no of match data provided\n");
		return -EINVAL;
	}

	priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops);
	if (IS_ERR(priv->phy)) {
		dev_err(dev, "failed to create combphy\n");
		return PTR_ERR(priv->phy);
	}

	priv->apb_rst = devm_reset_control_get_shared(dev, "apb");
	if (IS_ERR(priv->apb_rst)) {
		return dev_err_probe(dev, PTR_ERR(priv->apb_rst),
				     "failed to get apb rst control\n");
	}
	if (!priv->apb_rst)
		dev_info(dev, "no apb reset control specified\n");

	priv->phy_rst = devm_reset_control_get_shared(dev, "phy");
	if (IS_ERR(priv->phy_rst)) {
		return dev_err_probe(dev, PTR_ERR(priv->phy_rst),
				     "failed to get phy rst control\n");
	}
	if (!priv->phy_rst)
		dev_info(dev, "no phy reset control specified\n");

	priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
	if (priv->num_clks < 1)
		return -ENODEV;

	dev_info(dev, "num_clks = %d\n", priv->num_clks);
	dev_set_drvdata(dev, priv);
	phy_set_drvdata(priv->phy, priv);

	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);

	return PTR_ERR_OR_ZERO(phy_provider);
}

static const struct of_device_id zhihe_p3phy_of_match[] = {
	{ .compatible = "zhihe,a210-pcie-phy", .data = &a210_ops },
	{ },
};
MODULE_DEVICE_TABLE(of, zhihe_p3phy_of_match);

static struct platform_driver zhihe_p3phy_driver = {
	.probe	= zhihe_p3phy_probe,
	.driver = {
		.name = "zhihe-snps-pcie3-phy",
		.of_match_table = zhihe_p3phy_of_match,
	},
};
module_platform_driver(zhihe_p3phy_driver);
MODULE_DESCRIPTION("Zhihe Synopsys PCIe 3.0 PHY driver");
MODULE_LICENSE("GPL");