345 lines
11 KiB
C
345 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2025 Zhihe Computing Limited.
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*/
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#ifndef __MACH_ZHIHE_CLK_H
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#define __MACH_ZHIHE_CLK_H
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#include <linux/spinlock.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/a210-clock.h>
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extern spinlock_t zhihe_clk_lock;
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#define ZHIHE_CLK_NAME_SIZE 40
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#define PLL_RATE(_vco, _rate, _r, _b, _f, _p, _k) \
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{ \
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.vco_rate = (_vco), \
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.rate = (_rate), \
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.refdiv = (_r), \
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.fbdiv = (_b), \
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.frac = (_f), \
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.postdiv1 = (_p), \
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.postdiv2 = (_k), \
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}
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#define REG(n) [(n)] = {.name = #n}
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#define CLK(_type, _id, _name, _parent) \
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.type = (_type), \
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.id = (_id), \
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.name = (_name), \
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.parent = (_parent)
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#define FIXED(_id, _name, _parent, _freq) { \
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CLK(CLK_TYPE_FIXED, (_id), (_name), (_parent)), \
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.fixed = {.freq = (_freq),}, \
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}
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#define PLL(_id, _name, _parent, _reg, _shift, _pll) { \
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CLK(CLK_TYPE_PLL, (_id), (_name), (_parent)), \
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.reg = (_reg), \
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.shift = (_shift), \
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.pll = (_pll), \
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}
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#define FIXED_FACTOR(_id, _name, _parent, _mult, _div) { \
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CLK(CLK_TYPE_FIXED_FACTOR, (_id), (_name), (_parent)), \
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.fixed_factor = {.mult = (_mult), .div = (_div),}, \
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}
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#define DIV(_id, _name, _parent, _reg, _shift, _bit_idx, _width, _sync, _div_type, _min, _max) { \
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CLK(CLK_TYPE_DIVIDER, (_id), (_name), (_parent)), \
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.reg = (_reg), \
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.shift = (_shift), \
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.bit_idx = (_bit_idx), \
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.width = (_width), \
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.divider = {.sync = (_sync), .div_type = (_div_type), .min = (_min), .max = (_max)} \
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}
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#define DIV_CLOSEST(_id, _name, _parent, _reg, _shift, _bit_idx, _width, _sync, _div_type, _min, _max) { \
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CLK(CLK_TYPE_DIVIDER_CLOSEST, (_id), (_name), (_parent)), \
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.reg = (_reg), \
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.shift = (_shift), \
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.bit_idx = (_bit_idx), \
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.width = (_width), \
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.divider = {.sync = (_sync), .div_type = (_div_type), .min = (_min), .max = (_max)} \
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}
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#define GATE(_id, _name, _parent, _reg, _shift, _bit_idx) { \
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CLK(CLK_TYPE_GATE, (_id), (_name), (_parent)), \
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.reg = (_reg), \
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.shift = (_shift), \
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.bit_idx = (_bit_idx), \
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}
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#define GATE_SHARED(_id, _name, _parent, _reg, _shift, _bit_idx, _count) { \
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CLK(CLK_TYPE_GATE_SHARED, (_id), (_name), (_parent)), \
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.reg = (_reg), \
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.shift = (_shift), \
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.bit_idx = (_bit_idx), \
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.gate_shared = {.share_count = (_count)}, \
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}
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#define MUX(_id, _name, _reg, _shift, _bit_idx, _width, _parents, _num, _flags) { \
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CLK(CLK_TYPE_MUX, (_id), (_name), ""), \
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.reg = (_reg), \
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.shift = (_shift), \
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.bit_idx = (_bit_idx), \
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.width = (_width), \
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.mux = {.parents = (_parents), .num_parents = (_num), .flags = (_flags)}, \
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}
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#define PLL_PARAM(_pll, _out, _table, _count, _cfg0, _sts, _lock, _bypass, _rst, _mode, _name) \
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[(_pll)] = { \
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.out_type = (_out), \
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.clk_type = (_pll), \
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.rate_table = (_table), \
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.rate_count = (_count), \
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.cfg0_reg_off = (_cfg0), \
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.pll_sts_off = (_sts), \
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.pll_lock_bit = (_lock), \
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.pll_bypass_bit = (_bypass), \
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.pll_rst_bit = (_rst), \
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.pll_mode = (_mode), \
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.name = (_name), \
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}
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#define CLK_SUBSYS(_name, _regs, _num_reg, _info, _num_info, _pll, _num_pll, _is_fpga, _die_num) { \
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.name = (_name), \
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.regs = (_regs), \
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.num_regs = (_num_reg), \
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.info = (_info), \
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.num_info = (_num_info), \
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.plls = (_pll), \
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.num_plls = (_num_pll), \
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.is_fpga = (_is_fpga), \
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.die_num = (_die_num), \
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}
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enum zhihe_pll_outtype {
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ZHIHE_PLL_VCO,
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ZHIHE_PLL_DIV,
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};
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enum zhihe_div_type {
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MUX_TYPE_DIV,
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MUX_TYPE_CDE,
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};
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enum zhihe_div_sync_type {
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NO_DIV_EN = 255,
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};
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enum zhihe_clk_types {
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CLK_TYPE_FIXED,
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CLK_TYPE_PLL,
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CLK_TYPE_FIXED_FACTOR,
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CLK_TYPE_DIVIDER,
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CLK_TYPE_DIVIDER_CLOSEST,
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CLK_TYPE_GATE,
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CLK_TYPE_GATE_SHARED,
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CLK_TYPE_MUX,
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};
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enum zhihe_pll_mode {
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PLL_MODE_FRAC,
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PLL_MODE_INT,
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};
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struct zhihe_clk_reg {
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void __iomem *base;
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char name[ZHIHE_CLK_NAME_SIZE];
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};
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/* clk summary info at subsys level */
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struct zhihe_clk_subsys {
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char name[ZHIHE_CLK_NAME_SIZE];
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struct zhihe_clk_reg *regs;
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u32 num_regs;
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struct zhihe_clk_info *info;
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u32 num_info;
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struct zhihe_clk_info_pll *plls;
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u32 num_plls;
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bool is_fpga;
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struct clk_onecell_data *clk_data;
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char die_num;
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};
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struct clk_zhihepll {
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struct clk_hw hw;
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void __iomem *base;
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unsigned int clk_type;
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enum zhihe_pll_outtype out_type;
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enum zhihe_pll_mode pll_mode;
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const struct zhihe_pll_rate_table *rate_table;
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int rate_count;
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u32 cfg0_reg_off;
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u32 pll_sts_off;
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int pll_lock_bit;
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int pll_rst_bit;
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int pll_bypass_bit;
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};
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struct clk_zhihediv {
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struct clk_divider divider;
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enum zhihe_div_type div_type;
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u16 min_div;
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u16 max_div;
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u8 sync_en;
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const struct clk_ops *ops;
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};
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struct clk_zhihegate {
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struct clk_gate gate;
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unsigned int *share_count;
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const struct clk_ops *ops;
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};
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struct zhihe_pll_rate_table {
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unsigned long vco_rate;
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unsigned long rate;
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unsigned int refdiv;
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unsigned int fbdiv;
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unsigned int frac;
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unsigned int postdiv1;
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unsigned int postdiv2;
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};
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/* detailed clk info for each clk */
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struct zhihe_clk_info_pll {
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enum zhihe_pll_outtype out_type;
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unsigned int clk_type;
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struct zhihe_pll_rate_table *rate_table;
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int rate_count;
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int flags;
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char name[ZHIHE_CLK_NAME_SIZE];
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u32 cfg0_reg_off;
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u32 pll_sts_off;
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int pll_lock_bit;
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int pll_rst_bit;
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int pll_bypass_bit;
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enum zhihe_pll_mode pll_mode;
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};
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struct zhihe_clk_info_fixed {
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unsigned int freq;
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};
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struct zhihe_clk_info_fixed_factor {
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unsigned int mult;
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unsigned int div;
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};
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struct zhihe_clk_info_divider {
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u8 sync;
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enum zhihe_div_type div_type;
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u16 min;
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u16 max;
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};
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struct zhihe_clk_info_gate_shared {
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unsigned int *share_count;
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};
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struct zhihe_clk_info_mux {
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const char * const *parents;
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int num_parents;
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unsigned long flags;
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};
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struct zhihe_clk_info {
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enum zhihe_clk_types type;
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u32 id;
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char name[ZHIHE_CLK_NAME_SIZE];
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char parent[ZHIHE_CLK_NAME_SIZE];
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u8 reg;
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u32 shift;
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u8 width;
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u8 bit_idx;
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union {
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struct zhihe_clk_info_fixed fixed;
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struct zhihe_clk_info_fixed_factor fixed_factor;
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struct zhihe_clk_info_pll *pll;
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struct zhihe_clk_info_divider divider;
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struct zhihe_clk_info_gate_shared gate_shared;
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struct zhihe_clk_info_mux mux;
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};
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};
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static inline struct clk *zhihe_clk_fixed_factor(struct device *dev, const char *name,
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const char *parent, unsigned int mult, unsigned int div)
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{
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return clk_register_fixed_factor(dev, name, parent,
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CLK_SET_RATE_PARENT, mult, div);
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}
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struct clk *zhihe_pll(struct device *dev, const char *name, const char *parent_name,
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void __iomem *base,
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const struct zhihe_clk_info_pll *pll_clk);
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static inline struct clk *zhihe_clk_gate(struct device *dev, const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, 0, &zhihe_clk_lock);
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}
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struct clk *zhihe_clk_register_gate_shared(struct device *dev, const char *name, const char *parent,
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unsigned long flags, void __iomem *reg,
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u8 shift, spinlock_t *lock,
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unsigned int *share_count);
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struct clk *zhihe_clk_divider(struct device *dev, const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width,
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u8 sync, enum zhihe_div_type div_type,
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u16 min, u16 max);
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/**
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* By default, the clk framework calculates frequency by rounding downwards.
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* This function is to achieve closest frequency.
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*/
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struct clk *zhihe_clk_divider_closest(struct device *dev, const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width,
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u8 sync, enum zhihe_div_type div_type,
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u16 min, u16 max);
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static inline struct clk *zhihe_clk_fixed(struct device *dev, const char *name, const char *parent, unsigned long rate)
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{
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return clk_register_fixed_rate(dev, name, parent, 0, rate);
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}
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static inline struct clk *zhihe_clk_gate_shared(struct device *dev, const char *name, const char *parent,
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void __iomem *reg, u8 shift,
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unsigned int *share_count)
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{
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return zhihe_clk_register_gate_shared(dev, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, &zhihe_clk_lock, share_count);
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}
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static inline struct clk *zhihe_clk_mux_flags(struct device *dev, const char *name,
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void __iomem *reg, u8 shift, u8 width,
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const char * const *parents, int num_parents,
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unsigned long flags)
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{
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return clk_register_mux(dev, name, parents, num_parents,
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flags , reg, shift, width, 0,
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&zhihe_clk_lock);
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}
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void zhihe_clk_fake_pll_fixed_ops(void);
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int zhihe_clk_set_round_rate(struct device *dev, struct clk *clk, unsigned int freq);
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int zhihe_clk_of_bulk_init(struct device *dev, struct clk **clks);
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int add_die_suffix(struct platform_device *pdev);
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void zhihe_register_clock(struct platform_device *pdev);
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void zhihe_unregister_clocks(struct clk *clks[], unsigned int count);
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int zhihe_parse_regbase(struct platform_device *pdev);
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#endif
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