248 lines
6.5 KiB
Plaintext
248 lines
6.5 KiB
Plaintext
#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/a210-clock.h>
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/ {
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soc {
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dmac0_die1: dmac@2000520000 {
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compatible = "zhihe,axi-dma";
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reg = <0x20 0x00520000 0x0 0x4000>;
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interrupt-parent = <&intc_die1>;
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interrupts = <264>;
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clocks = <&apb_clk>, <&apb_clk>;
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clock-names = "core-clk", "cfgr-clk";
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#dma-cells = <1>;
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dma-channels = <16>;
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snps,block-size = <65536 65536 65536 65536 65536 65536 65536 65536
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65536 65536 65536 65536 65536 65536 65536 65536>;
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snps,priority = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>;
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snps,dma-masters = <1>;
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snps,data-width = <4>;
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snps,axi-max-burst-len = <16>;
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status = "okay";
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};
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peri1_padctrl_die1: peri1-padctrl@2002026000 {
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compatible = "zhihe,a210-group1-pinctrl";
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reg = <0x20 0x02026000 0x0 0x1000>;
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clocks = <&clk_peri_die1 PERI1_PAD_CTRL_PCLK_EN>;
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clock-names = "pclk";
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status = "okay";
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};
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peri2_padctrl_die1: peri2-padctrl@2008411000 {
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compatible = "zhihe,a210-group2-pinctrl";
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reg = <0x20 0x08411000 0x0 0x1000>;
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clocks = <&clk_peri_die1 PERI2_PAD_CTRL_PCLK_EN>;
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clock-names = "pclk";
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status = "okay";
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};
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gpio@2002012000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x20 0x02012000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk_peri_die1 PERI1_GPIO0_PCLK_EN>,
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<&clk_peri_die1 PERI1_GPIO0_DBCLK_EN>;
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clock-names = "bus", "db";
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status = "okay";
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gpio0_die1: gpio0-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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gpio-ranges = <&peri1_padctrl_die1 0 0 32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc_die1>;
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interrupts = <289>;
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};
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};
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gpio@2002013000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x20 0x02013000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk_peri_die1 PERI1_GPIO1_PCLK_EN>,
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<&clk_peri_die1 PERI1_GPIO1_DBCLK_EN>;
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clock-names = "bus", "db";
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status = "okay";
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gpio1_die1: gpio1-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <18>;
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gpio-ranges = <&peri1_padctrl_die1 0 32 18>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc_die1>;
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interrupts = <290>;
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};
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};
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gpio@2008410000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x20 0x08410000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk_peri_die1 PERI2_GPIO2_PCLK_EN>,
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<&clk_peri_die1 PERI2_GPIO2_DBCLK_EN>;
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clock-names = "bus", "db";
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status = "okay";
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gpio2_die1: gpio2-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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gpio-ranges = <&peri2_padctrl_die1 0 0 32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc_die1>;
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interrupts = <291>;
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};
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};
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gpio@2008412000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x20 0x08412000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk_peri_die1 PERI2_GPIO3_PCLK_EN>,
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<&clk_peri_die1 PERI2_GPIO3_DBCLK_EN>;
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clock-names = "bus", "db";
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status = "okay";
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gpio3_die1: gpio3-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <11>;
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gpio-ranges = <&peri2_padctrl_die1 0 32 11>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc_die1>;
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interrupts = <292>;
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};
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};
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qspi0_die1: spi@2001000000 {
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compatible = "snps,dw-apb-ssi-quad";
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reg = <0x20 0x01000000 0x0 0x4000>;
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interrupt-parent = <&intc_die1>;
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interrupts = <308>;
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clocks = <&clk_peri_die1 PERI1_QSPI0_SSI_CLK_EN>;
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clock-names = "sclk";
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num-cs = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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};
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qspi1_die1: spi@2008428000 {
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compatible = "snps,dw-apb-ssi-quad";
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reg = <0x20 0x08428000 0x0 0x4000>;
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interrupt-parent = <&intc_die1>;
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interrupts = <309>;
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clocks = <&clk_peri_die1 PERI2_QSPI1_SSI_CLK_EN>;
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clock-names = "sclk";
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num-cs = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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};
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uart4_die1: serial@2008401000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x20 0x08401000 0x0 0x400>;
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interrupt-parent = <&intc_die1>;
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interrupts = <325>;
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clocks = <&clk_peri_die1 PERI2_UART4_PCLK_EN>, <&clk_peri_die1 PERI2_UART4_SCLK_EN>;
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clock-names = "apb_pclk", "baudclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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hw-flow-control = "unsupport";
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status = "okay";
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};
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mbox_920_die1: mbox@2000320000 {
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compatible = "zhihe,mailbox";
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reg = <0x20 0x00321000 0x0 0x1000>,
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<0x20 0x00320000 0x0 0x1000>,
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<0x20 0x00311000 0x0 0x1000>;
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reg-names = "interrupt_addr",
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"local_addr0",
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"remote_icu0";
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interrupt-parent = <&intc_die1>;
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interrupts = <336 IRQ_TYPE_LEVEL_HIGH>;
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icu_cpu_id = <1>;
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#mbox-cells = <2>;
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version = <1>;
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status = "okay";
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};
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aon_die1: aon_subsys1@20308f8000 {
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compatible = "zhihe,aon";
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reg = <0x20 0x308f8000 0x0 0x10000>,
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<0x20 0x30842018 0x0 0x4>,
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<0x20 0x30846144 0x0 0x4>;
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reg-names = "aon_base_addr",
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"aon_reset_reg",
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"aon_sync_reg";
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firmware-name = "a210-aon.bin";
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mboxes = <&mbox_920_die1 1 0>; //parent / channel / type
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mbox-names = "aon1";
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#mbox-cells = <2>;
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version = <1>;
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status = "okay";
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};
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npu1: vipcore1@0x2007000000 {
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compatible = "verisilicon,vipcore1";
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reg = <0x20 0x07000000 0x00 0x10000>;
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interrupt-parent = <&intc>;
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interrupts = <71>;
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clocks = <&clk_die1 TOP_NPU_CCLK_DIV>,
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<&clk_die1 TOP_NPU_ACLK_DIV>;
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clock-names = "npu_cclk", "npu_aclk";
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power-domains = <&power_npu_ip>;
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status = "okay";
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};
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npu2: vipcore2@0x4007000000 {
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compatible = "verisilicon,vipcore2";
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reg = <0x40 0x07000000 0x00 0x10000>;
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interrupt-parent = <&intc>;
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interrupts = <71>;
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clocks = <&clk_die2 TOP_NPU_CCLK_DIV>,
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<&clk_die2 TOP_NPU_ACLK_DIV>;
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clock-names = "npu_cclk", "npu_aclk";
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power-domains = <&power_npu_ip>;
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status = "okay";
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};
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npu3: vipcore3@0x6007000000 {
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compatible = "verisilicon,vipcore3";
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reg = <0x60 0x07000000 0x00 0x10000>;
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interrupt-parent = <&intc>;
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interrupts = <71>;
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clocks = <&clk_die3 TOP_NPU_CCLK_DIV>,
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<&clk_die3 TOP_NPU_ACLK_DIV>;
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clock-names = "npu_cclk", "npu_aclk";
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power-domains = <&power_npu_ip>;
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status = "okay";
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};
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};
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};
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